coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

1 participants
1011 discussions

Patch merged into coreboot/master: 63e1948 intel/fsp_bd82x6x: Fix cycle error
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 63e1948643fcbd763c83b6baa6cd9a077d49f1fc Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:41:29 2014 +0200 intel/fsp_bd82x6x: Fix cycle error Some copy-pasta snuck in that reintroduced an error already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071) Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6479 for details. -gerrit

1 0

Patch merged into coreboot/master: 38fa6ed ifdtool: Check if file was opened
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 38fa6edf2db155383e04bf8427377b7b684cede3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:18:45 2014 +0200 ifdtool: Check if file was opened Check if the new file could in fact be opened before writing to it. Change-Id: I6b2d31bf5c18f657fca4dc14fee2f2d5a2e33080 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6477 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6477 for details. -gerrit

1 0

Patch merged into coreboot/master: 440daf7 ifdtool: Avoid potential buffer overflow
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 440daf786a85f8c1f4959c519811e3d6e10586bc Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:14:25 2014 +0200 ifdtool: Avoid potential buffer overflow Filenames of 4091 bytes or more lead to a buffer overflow. Change-Id: I1b4b3932af096f0fcbfb783ab708ed273d3a844e Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6476 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6476 for details. -gerrit

1 0

Patch merged into coreboot/master: edb0a61 nvramtool: Close file after use
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit edb0a61be4030cc6bdc605332204bb27c9f1b98f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:10:53 2014 +0200 nvramtool: Close file after use mmap builds a new reference to the file, so the file descriptor isn't necessary anymore. Close it. Change-Id: I639fd13ff8f13cbdfce1d199d75744e56f2b19b3 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6475 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6475 for details. -gerrit

1 0

New patch to review for coreboot: 0ad8ce6 lenovo/x201: Enable pcie lanes in wwan slot.
by Vladimir Serbinenko 03 Aug '14

03 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6482 -gerrit commit 0ad8ce6e0411d42c8a10335f29a09e681ccd560b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 14:55:14 2014 +0200 lenovo/x201: Enable pcie lanes in wwan slot. Change-Id: I7332eeed244877252074e661f1c256a69a9b428a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 1db5bf0..21e328a 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -135,8 +135,9 @@ chip northbridge/intel/nehalem end device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wwan) device pci 1c.3 on end # PCIe Port #4 (Expresscard) - device pci 1c.4 on end # PCIe Port #4 (wlan) + device pci 1c.4 on end # PCIe Port #5 (wlan) device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163

1 0

New patch to review for coreboot: 8aa0579 nehalem: Make UMA size configurable in CMOS.
by Vladimir Serbinenko 03 Aug '14

03 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6481 -gerrit commit 8aa0579e5000182bb57e20ca17f9ad3c2dee5bbc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 14:51:00 2014 +0200 nehalem: Make UMA size configurable in CMOS. All modes tested on X201. Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/cmos.layout | 15 ++++++++++++++- src/mainboard/packardbell/ms2290/cmos.layout | 9 +++++++++ src/northbridge/intel/nehalem/raminit.c | 20 +++++++++++--------- 3 files changed, 34 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index a0670cc..cba457f 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -97,7 +97,13 @@ entries 419 1 e 1 power_management_beeps 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode -#422 562 r 0 unused + +#422 2 r 0 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + +#427 557 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -138,6 +144,13 @@ enumerations 8 1 Primary 9 0 AHCI 9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index 6a8aa18..7f73e5f 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -84,6 +84,9 @@ entries 409 2 e 7 power_on_after_fail 411 1 e 9 sata_mode +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -123,6 +126,12 @@ enumerations 8 1 Primary 9 0 AHCI 9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b1356c2..74ddb4b 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3796,6 +3796,8 @@ static void dmi_setup(void) void chipset_init(const int s3resume) { u8 x2ca8; + u16 ggc; + u8 gfxsize; x2ca8 = read_mchbar8(0x2ca8); if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { @@ -3825,13 +3827,15 @@ void chipset_init(const int s3resume) write_mchbar16(0x1170, 0xb880); read_mchbar8(0x1210); write_mchbar8(0x1210, 0x84); - pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x52 - pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x2); - pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x2 - pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x52); - pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52 - pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb52); + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 0 for 32MB */ + gfxsize = 0; + } + + ggc = 0xb00 | ((gfxsize + 5) << 4); + + pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); u16 deven; deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 @@ -3854,9 +3858,7 @@ void chipset_init(const int s3resume) read_mchbar32(0x30); write_mchbar32(0x30, 0x40); - pcie_read_config8(SOUTHBRIDGE, 0x8); // = 0x6 - pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52 - pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50); + pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); gav(read32(DEFAULT_RCBA | 0x3428)); write32(DEFAULT_RCBA | 0x3428, 0x1d); }

1 0

Patch merged into coreboot/master: 5fc04d1 sandy/ivybridge: Make UMA size configurable.
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 5fc04d1fdd2d4c763ba39c3d90e487e9f773b122 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 01:59:38 2014 +0200 sandy/ivybridge: Make UMA size configurable. Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6470 for details. -gerrit

1 0

Patch set updated for coreboot: af542ae intel/fsp_bd82x6x: Fix cycle error
by Patrick Georgi 03 Aug '14

03 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6479 -gerrit commit af542ae9bccf870fb44b8e9ad269ad1a587eb875 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:41:29 2014 +0200 intel/fsp_bd82x6x: Fix cycle error Some copy-pasta snuck in that reintroduced an error already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071) Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index bc47395..97d0ce4 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -172,7 +172,7 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i<= 0; i--) { + for (i=15; i>= 0; i--) { if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 8ff36e6..b4fe557 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -165,7 +165,7 @@ static void dump_gpe0_status(u32 gpe0_sts) { int i; printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i<= 16; i--) { + for (i=31; i >= 16; i--) { if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");

1 0

Patch set updated for coreboot: a71d7f1 intel/fsp_bd82x6x: Fix cycle error
by Patrick Georgi 03 Aug '14

03 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6479 -gerrit commit a71d7f1649f2aa6cc54e96820119978d5f14f740 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 12:41:29 2014 +0200 intel/fsp_bd82x6x: Fix cycle error Some copy-pasta snuck in that reintroduced an error already fixed in #3435. Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index bc47395..97d0ce4 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -172,7 +172,7 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i<= 0; i--) { + for (i=15; i>= 0; i--) { if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 8ff36e6..b4fe557 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -165,7 +165,7 @@ static void dump_gpe0_status(u32 gpe0_sts) { int i; printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i<= 16; i--) { + for (i=31; i >= 16; i--) { if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");

1 0

Patch set updated for coreboot: 1dce3c9 southbridge/amd/cimx/sb800: Uninitialized variables in config func
by Edward O'Callaghan 03 Aug '14

03 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6474 -gerrit commit 1dce3c9c71ce8e439e4ba0ba91e304b66d92ee09 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 19:42:02 2014 +1000 southbridge/amd/cimx/sb800: Uninitialized variables in config func Both 'SbSpiSpeedSupport' and 'UsbRxMode' are uninitiated upon return from a 'sb800_cimx_config()' call. Change-Id: I32237ff97fafc3e69627d427e54268dcb039e12c Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cimx/sb800/cfg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 78aab79..91b6067 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -122,10 +122,13 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SpreadSpectrum = SPREAD_SPECTRUM; sb_config->PciClks = PCI_CLOCK_CTRL; sb_config->HpetTimer = HPET_TIMER; + sb_config->SbSpiSpeedSupport = 1; /* USB */ sb_config->USBMODE.UsbModeReg = USB_CONFIG; sb_config->SbUsbPll = 0; + /* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */ + sb_config->UsbRxMode = 1; /* SATA */ sb_config->SataClass = SATA_MODE;

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2014