coreboot-gerrit August 2014

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New patch to review for coreboot: 3619302 resource: Provide interface for indexed resource access
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6493 -gerrit commit 3619302dcc37238826af3087f4384d0048ce45a7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Aug 4 17:18:06 2014 +0200 resource: Provide interface for indexed resource access Provide means to read, write and read/modify/write registers behind resources. This is compatible with what reg_scripts is now doing, but should be replaced with something more efficient. Change-Id: Ic40f2d9e2e20f22a2a3f9838d5eacca63b0da6b0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/device/resource.h | 115 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 2d64c80..88eca81 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -3,6 +3,7 @@ #include <stdint.h> #include <stddef.h> +#include <arch/io.h> #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ @@ -74,4 +75,118 @@ extern void search_global_resources( #define RESOURCE_TYPE_MAX 20 extern const char *resource_type(struct resource *resource); +/* temporary API for simplified resource access + FIXME: we should work from struct resource *, instead of + resolving these all the time. + for now, that's what the ex-reg_script stuff is using, + so we'll have to live with it for a while +*/ +static inline u8 read_res8(struct device *dev, unsigned index, u32 offset) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return 0; + if (res->flags & IORESOURCE_IO) { + return inb(res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + return read8(res->base + offset); + } + return 0; +} + +static inline u16 read_res16(struct device *dev, unsigned index, u32 offset) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return 0; + if (res->flags & IORESOURCE_IO) { + return inw(res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + return read16(res->base + offset); + } + return 0; +} + +static inline u32 read_res32(struct device *dev, unsigned index, u32 offset) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return 0; + if (res->flags & IORESOURCE_IO) { + return inl(res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + return read32(res->base + offset); + } + return 0; +} + +static inline void write_res8(struct device *dev, unsigned index, u32 offset, u8 val) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return; + if (res->flags & IORESOURCE_IO) { + outb(val, res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + write8(res->base + offset, val); + } +} + +static inline void write_res16(struct device *dev, unsigned index, u32 offset, u16 val) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return; + if (res->flags & IORESOURCE_IO) { + outw(val, res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + write16(res->base + offset, val); + } +} + +static inline void write_res32(struct device *dev, unsigned index, u32 offset, u32 val) +{ + struct resource *res = find_resource(dev, index); + if (res == NULL) return; + if (res->flags & IORESOURCE_IO) { + outl(val, res->base + offset); + } else if (res->flags & IORESOURCE_MEM) { + write32(res->base + offset, val); + } +} + +static inline void rmw_res8(struct device *dev, unsigned index, u32 offset, u8 mask, u8 val) +{ + u8 tmp = read_res8(dev, index, offset); + tmp &= mask; + tmp |= val; + write_res8(dev, index, offset, tmp); +} + +static inline void rmw_res16(struct device *dev, unsigned index, u32 offset, u16 mask, u16 val) +{ + u16 tmp = read_res16(dev, index, offset); + tmp &= mask; + tmp |= val; + write_res16(dev, index, offset, tmp); +} + +static inline void rmw_res32(struct device *dev, unsigned index, u32 offset, u32 mask, u32 val) +{ + u32 tmp = read_res32(dev, index, offset); + tmp &= mask; + tmp |= val; + write_res32(dev, index, offset, tmp); +} + +static inline void or_res8(struct device *dev, unsigned index, u32 offset, u8 val) +{ + rmw_res8(dev, index, offset, ~0, val); +} + +static inline void or_res16(struct device *dev, unsigned index, u32 offset, u16 val) +{ + rmw_res16(dev, index, offset, ~0, val); +} + +static inline void or_res32(struct device *dev, unsigned index, u32 offset, u32 val) +{ + rmw_res32(dev, index, offset, ~0, val); +} + #endif /* DEVICE_RESOURCE_H */

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New patch to review for coreboot: 39e8e0c Provide helpers for read/modify/write access to registers
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6492 -gerrit commit 39e8e0c32404a691834c9f00e4025bb0f82cdfae Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Aug 4 17:17:24 2014 +0200 Provide helpers for read/modify/write access to registers These are provided for IO, memory access and PCI config space Change-Id: I491d857fe68f2bbd3de9deb3fd05c5c193378bbe Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/include/arch/io.h | 22 ++++++++++++++++++++++ src/include/device/pci_ops.h | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b6d82f9..4479f58 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -77,6 +77,15 @@ static inline uint32_t inl(uint16_t port) __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } + +static inline void rmw_io16(uint16_t port, uint16_t mask, uint16_t val) +{ + uint16_t tmp = inw(port); + tmp &= mask; + tmp |= val; + outw(tmp, port); +} + #endif /* __ROMCC__ */ static inline void outsb(uint16_t port, const void *addr, unsigned long count) @@ -167,6 +176,19 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui *((volatile uint32_t *)(addr)) = value; } +static inline void rmw_mem32(unsigned long addr, uint32_t mask, uint32_t val) +{ + uint32_t tmp = read32(addr); + tmp &= mask; + tmp |= val; + write32(addr, tmp); +} + +static inline void or_mem32(unsigned long addr, uint32_t val) +{ + rmw_mem32(addr, ~0, val); +} + /* Conflicts with definition in lib.h */ #if defined(__ROMCC__) || defined(__SMM__) static inline int log2(int value) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..84b1a7d 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -13,6 +13,45 @@ void pci_write_config8(device_t dev, unsigned int where, u8 val); void pci_write_config16(device_t dev, unsigned int where, u16 val); void pci_write_config32(device_t dev, unsigned int where, u32 val); +static inline void pci_rmw_config8(device_t dev, unsigned int reg, u8 mask, u8 val) +{ + u8 tmp = pci_read_config8(dev, reg); + tmp &= mask; + tmp |= val; + pci_write_config8(dev, reg, tmp); +} + +static inline void pci_rmw_config16(device_t dev, unsigned int reg, u16 mask, u16 val) +{ + u16 tmp = pci_read_config16(dev, reg); + tmp &= mask; + tmp |= val; + pci_write_config16(dev, reg, tmp); +} + +static inline void pci_rmw_config32(device_t dev, unsigned int reg, u32 mask, u32 val) +{ + u32 tmp = pci_read_config32(dev, reg); + tmp &= mask; + tmp |= val; + pci_write_config32(dev, reg, tmp); +} + +static inline void pci_or_config8(device_t dev, unsigned int reg, u8 val) +{ + pci_rmw_config8(dev, reg, ~0, val); +} + +static inline void pci_or_config16(device_t dev, unsigned int reg, u16 val) +{ + pci_rmw_config16(dev, reg, ~0, val); +} + +static inline void pci_or_config32(device_t dev, unsigned int reg, u32 val) +{ + pci_rmw_config32(dev, reg, ~0, val); +} + #if CONFIG_MMCONF_SUPPORT u8 pci_mmio_read_config8(device_t dev, unsigned int where); u16 pci_mmio_read_config16(device_t dev, unsigned int where);

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New patch to review for coreboot: 2520baa baytrail: add abstraction for IOSF accesses
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6491 -gerrit commit 2520baac202ab4b401f0e536c3c103628863ee1d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Aug 4 16:41:05 2014 +0200 baytrail: add abstraction for IOSF accesses Change-Id: Icbb95aae7ed3b5b5ce02a11b4c058b5598f110c0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/soc/intel/baytrail/baytrail/iosf.h | 18 +++++ src/soc/intel/baytrail/iosf.c | 127 +++++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index e936072..b8b2e59 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -101,6 +101,24 @@ void iosf_porta2_write(int reg, uint32_t val); uint32_t iosf_ssus_read(int reg); void iosf_ssus_write(int reg, uint32_t val); +uint32_t read_iosf(uint32_t port, uint32_t reg); +void write_iosf(uint32_t port, uint32_t reg, uint32_t val); + +#ifndef __ROMCC__ +static inline void rmw_iosf(uint32_t port, uint32_t reg, uint32_t mask, uint32_t val) +{ + uint32_t tmp = read_iosf(port, reg); + tmp &= mask; + tmp |= val; + write_iosf(port, reg, tmp); +} + +static inline void or_iosf(uint32_t port, uint32_t reg, uint32_t val) +{ + rmw_iosf(port, reg, ~0, val); +} +#endif + /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 2b07e2b..63c4b6a 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <baytrail/iosf.h> +#include <console/console.h> #if !defined(__PRE_RAM__) #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) @@ -285,3 +286,129 @@ void iosf_ssus_write(int reg, uint32_t val) { return iosf_write_port(IOSF_WRITE(SSUS), reg, val); } + +uint32_t read_iosf(uint32_t port, uint32_t reg) +{ + switch (port) { + case IOSF_PORT_AUNIT: + return iosf_aunit_read(reg); + case IOSF_PORT_CPU_BUS: + return iosf_cpu_bus_read(reg); + case IOSF_PORT_BUNIT: + return iosf_bunit_read(reg); + case IOSF_PORT_DUNIT_CH0: + return iosf_dunit_ch0_read(reg); + case IOSF_PORT_PMC: + return iosf_punit_read(reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(reg); + case IOSF_PORT_SEC: + return iosf_sec_read(reg); + case IOSF_PORT_0x45: + return iosf_port45_read(reg); + case IOSF_PORT_0x46: + return iosf_port46_read(reg); + case IOSF_PORT_0x47: + return iosf_port47_read(reg); + case IOSF_PORT_SCORE: + return iosf_score_read(reg); + case IOSF_PORT_0x55: + return iosf_port55_read(reg); + case IOSF_PORT_0x58: + return iosf_port58_read(reg); + case IOSF_PORT_0x59: + return iosf_port59_read(reg); + case IOSF_PORT_0x5a: + return iosf_port5a_read(reg); + case IOSF_PORT_USHPHY: + return iosf_ushphy_read(reg); + case IOSF_PORT_SCC: + return iosf_scc_read(reg); + case IOSF_PORT_LPSS: + return iosf_lpss_read(reg); + case IOSF_PORT_0xa2: + return iosf_porta2_read(reg); + case IOSF_PORT_CCU: + return iosf_ccu_read(reg); + case IOSF_PORT_SSUS: + return iosf_ssus_read(reg); + default: + printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", + port); + break; + } + return 0; +} + +void write_iosf(uint32_t port, uint32_t reg, uint32_t val) +{ + switch (port) { + case IOSF_PORT_AUNIT: + iosf_aunit_write(reg, val); + break; + case IOSF_PORT_CPU_BUS: + iosf_cpu_bus_write(reg, val); + break; + case IOSF_PORT_BUNIT: + iosf_bunit_write(reg, val); + break; + case IOSF_PORT_DUNIT_CH0: + iosf_dunit_write(reg, val); + break; + case IOSF_PORT_PMC: + iosf_punit_write(reg, val); + break; + case IOSF_PORT_USBPHY: + iosf_usbphy_write(reg, val); + break; + case IOSF_PORT_SEC: + iosf_sec_write(reg, val); + break; + case IOSF_PORT_0x45: + iosf_port45_write(reg, val); + break; + case IOSF_PORT_0x46: + iosf_port46_write(reg, val); + break; + case IOSF_PORT_0x47: + iosf_port47_write(reg, val); + break; + case IOSF_PORT_SCORE: + iosf_score_write(reg, val); + break; + case IOSF_PORT_0x55: + iosf_port55_write(reg, val); + break; + case IOSF_PORT_0x58: + iosf_port58_write(reg, val); + break; + case IOSF_PORT_0x59: + iosf_port59_write(reg, val); + break; + case IOSF_PORT_0x5a: + iosf_port5a_write(reg, val); + break; + case IOSF_PORT_USHPHY: + iosf_ushphy_write(reg, val); + break; + case IOSF_PORT_SCC: + iosf_scc_write(reg, val); + break; + case IOSF_PORT_LPSS: + iosf_lpss_write(reg, val); + break; + case IOSF_PORT_0xa2: + iosf_porta2_write(reg, val); + break; + case IOSF_PORT_CCU: + iosf_ccu_write(reg, val); + break; + case IOSF_PORT_SSUS: + iosf_ssus_write(reg, val); + break; + default: + printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", + port); + break; + } +}

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New patch to review for coreboot: a06021b baytrail: remove uses to MSR regscript opcodes
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6490 -gerrit commit a06021b990a92b2ac7301e29b0e1d2f201e18b56 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Aug 4 13:57:03 2014 +0200 baytrail: remove uses to MSR regscript opcodes MSR related opcodes were used only in CPU configuration, so it's easy to get rid of them. Change-Id: I57c3b537f02920f46974a5a77cce3e1115e0cd3e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/soc/intel/baytrail/cpu.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 15efab9..f2b816f 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -28,7 +28,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <reg_script.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> @@ -51,26 +50,6 @@ static int adjust_apic_id(int index, int apic_id) return 2 * index; } -/* Package level MSRs */ -const struct reg_script package_msr_script[] = { - /* Set Package TDP to ~7W */ - REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), - REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), - REG_SCRIPT_END -}; - -/* Core level MSRs */ -const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -89,8 +68,11 @@ void baytrail_init_cpus(device_t dev) mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; - /* Set package MSRs */ - reg_script_run(package_msr_script); + /* Set Package TDP to ~7W */ + wrmsr(MSR_PKG_POWER_LIMIT, (msr_t){.lo = 0x3880fa}); + wrmsr(MSR_PKG_TURBO_CFG1, (msr_t){.lo = 0x702}); + wrmsr(MSR_CPU_TURBO_WKLD_CFG1, (msr_t){.lo = 0x200b}); + wrmsr(MSR_CPU_TURBO_WKLD_CFG2, (msr_t){.lo = 0}); /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ enable_turbo(); @@ -112,7 +94,12 @@ static void baytrail_core_init(device_t cpu) enable_turbo(); /* Set core MSRs */ - reg_script_run(core_msr_script); + /* Dynamic L2 shrink enable and threshold */ + rmw_msr(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008); + /* Disable C1E */ + rmw_msr(MSR_POWER_CTL, ~0x2, 0); + or_msr(MSR_POWER_MISC, 0x44); + /* Set this core to max frequency ratio */ set_max_freq();

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Patch set updated for coreboot: b5582a1 reg_scripts: move them to soc/intel/baytrail
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6298 -gerrit commit b5582a1d192d95a102a98dcdeb00177ffcd7dbb9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jul 16 19:39:02 2014 +0200 reg_scripts: move them to soc/intel/baytrail The baytrail code is the only user of this API, and with its #if CONFIG_$CONCRETE_HARDWARE blocks, it was a bit of a sore spot in src/lib. Change-Id: I10f5f74188aa83f2e747503b5cd4b28dba5f4012 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/Kconfig | 7 - src/include/reg_script.h | 339 ---------------------- src/lib/Makefile.inc | 2 - src/lib/reg_script.c | 551 ------------------------------------ src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/reg_script.c | 538 +++++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/reg_script.h | 339 ++++++++++++++++++++++ src/soc/intel/fsp_baytrail/Kconfig | 1 - 8 files changed, 878 insertions(+), 900 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index af82353..ecc2757 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1102,13 +1102,6 @@ config POWER_BUTTON_IS_OPTIONAL help Internal option that controls ENABLE_POWER_BUTTON visibility. -config REG_SCRIPT - bool - default y if ARCH_X86 - default n - help - Internal option that controls whether we compile in register scripts. - # Maximum reboot count # TODO: Improve description. config MAX_REBOOT_CNT diff --git a/src/include/reg_script.h b/src/include/reg_script.h deleted file mode 100644 index 72e1e96..0000000 --- a/src/include/reg_script.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef REG_SCRIPT_H -#define REG_SCRIPT_H - -#include <stdint.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/resource.h> - -/* - * The reg script library is a way to provide data-driven I/O accesses for - * initializing devices. It currently supports PCI, legacy I/O, - * memory-mapped I/O, and IOSF accesses. - * - * In order to simplify things for the developer the following features - * are employed: - * - Chaining of tables that allow runtime tables to chain to compile-time - * tables. - * - Notion of current device (device_t) being worked on. This allows for - * PCI config, io, and mmio on a particular device's resources. - * - * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push - * and pop of the context. A chained reg_script inherits the previous - * context (such as current device), but it does not impact the previous - * context in any way. - */ - -enum { - REG_SCRIPT_COMMAND_READ, - REG_SCRIPT_COMMAND_WRITE, - REG_SCRIPT_COMMAND_RMW, - REG_SCRIPT_COMMAND_POLL, - REG_SCRIPT_COMMAND_SET_DEV, - REG_SCRIPT_COMMAND_NEXT, - REG_SCRIPT_COMMAND_END, -}; - -enum { - REG_SCRIPT_TYPE_PCI, - REG_SCRIPT_TYPE_IO, - REG_SCRIPT_TYPE_MMIO, - REG_SCRIPT_TYPE_RES, - REG_SCRIPT_TYPE_IOSF, - REG_SCRIPT_TYPE_MSR, -}; - -enum { - REG_SCRIPT_SIZE_8, - REG_SCRIPT_SIZE_16, - REG_SCRIPT_SIZE_32, - REG_SCRIPT_SIZE_64, -}; - -struct reg_script { - uint32_t command; - uint32_t type; - uint32_t size; - uint32_t reg; - uint64_t mask; - uint64_t value; - uint32_t timeout; - union { - uint32_t id; - const struct reg_script *next; - device_t dev; - unsigned int res_index; - }; -}; - -/* Internal helper Macros. */ - -#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ - mask_, value_, timeout_, id_) \ - { .command = cmd_, \ - .type = type_, \ - .size = size_, \ - .reg = reg_, \ - .mask = mask_, \ - .value = value_, \ - .timeout = timeout_, \ - .id = id_, \ - } - -#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \ - mask_, value_, timeout_) \ - { .command = cmd_, \ - .type = type_, \ - .size = size_, \ - .reg = reg_, \ - .mask = mask_, \ - .value = value_, \ - .timeout = timeout_, \ - .res_index = res_index_, \ - } - -/* - * PCI - */ - -#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_PCI, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_PCI_READ8(reg_) \ - REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0) -#define REG_PCI_READ16(reg_) \ - REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0) -#define REG_PCI_READ32(reg_) \ - REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0) -#define REG_PCI_WRITE8(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0) -#define REG_PCI_WRITE16(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0) -#define REG_PCI_WRITE32(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0) -#define REG_PCI_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0) -#define REG_PCI_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) -#define REG_PCI_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) -#define REG_PCI_OR8(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) -#define REG_PCI_OR16(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0) -#define REG_PCI_OR32(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0) -#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Legacy IO - */ - -#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_IO, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_IO_READ8(reg_) \ - REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0) -#define REG_IO_READ16(reg_) \ - REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0) -#define REG_IO_READ32(reg_) \ - REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0) -#define REG_IO_WRITE8(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0) -#define REG_IO_WRITE16(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0) -#define REG_IO_WRITE32(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0) -#define REG_IO_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0) -#define REG_IO_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) -#define REG_IO_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) -#define REG_IO_OR8(reg_, value_) \ - REG_SCRIPT_IO_RMW8(_reg, 0xff, value) -#define REG_IO_OR16(reg_, value_) \ - REG_SCRIPT_IO_RMW16(_reg, 0xffff, value) -#define REG_IO_OR32(reg_, value_) \ - REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value) -#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Memory Mapped IO - */ - -#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_MMIO, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_MMIO_READ8(reg_) \ - REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0) -#define REG_MMIO_READ16(reg_) \ - REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0) -#define REG_MMIO_READ32(reg_) \ - REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0) -#define REG_MMIO_WRITE8(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0) -#define REG_MMIO_WRITE16(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0) -#define REG_MMIO_WRITE32(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0) -#define REG_MMIO_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0) -#define REG_MMIO_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) -#define REG_MMIO_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) -#define REG_MMIO_OR8(reg_, value_) \ - REG_MMIO_RMW8(reg_, 0xff, value_) -#define REG_MMIO_OR16(reg_, value_) \ - REG_MMIO_RMW16(reg_, 0xffff, value_) -#define REG_MMIO_OR32(reg_, value_) \ - REG_MMIO_RMW32(reg_, 0xffffffff, value_) -#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Access through a device's resource such as a Base Address Register (BAR) - */ - -#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_RES, bar_, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_) -#define REG_RES_READ8(bar_, reg_) \ - REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0) -#define REG_RES_READ16(bar_, reg_) \ - REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0) -#define REG_RES_READ32(bar_, reg_) \ - REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0) -#define REG_RES_WRITE8(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0) -#define REG_RES_WRITE16(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0) -#define REG_RES_WRITE32(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0) -#define REG_RES_RMW8(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0) -#define REG_RES_RMW16(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) -#define REG_RES_RMW32(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) -#define REG_RES_OR8(bar_, reg_, value_) \ - REG_RES_RMW8(bar_, reg_, 0xff, value_) -#define REG_RES_OR16(bar_, reg_, value_) \ - REG_RES_RMW16(bar_, reg_, 0xffff, value_) -#define REG_RES_OR32(bar_, reg_, value_) \ - REG_RES_RMW32(bar_, reg_, 0xffffffff, value_) -#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_) -#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) -#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) - -/* - * IO Sideband Function - */ - -#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_IOSF, \ - REG_SCRIPT_SIZE_32, \ - reg_, mask_, value_, timeout_, unit_) -#define REG_IOSF_READ(unit_, reg_) \ - REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) -#define REG_IOSF_WRITE(unit_, reg_, value_) \ - REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) -#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ - REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) -#define REG_IOSF_OR(unit_, reg_, value_) \ - REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) -#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) - -/* - * CPU Model Specific Register - */ - -#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_MSR, \ - REG_SCRIPT_SIZE_64, \ - reg_, mask_, value_, timeout_, 0) -#define REG_MSR_READ(reg_) \ - REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) -#define REG_MSR_WRITE(reg_, value_) \ - REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) -#define REG_MSR_RMW(reg_, mask_, value_) \ - REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) -#define REG_MSR_OR(reg_, value_) \ - REG_MSR_RMW(reg_, -1ULL, value_) -#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) - -/* - * Chain to another table. - */ -#define REG_SCRIPT_NEXT(next_) \ - { .command = REG_SCRIPT_COMMAND_NEXT, \ - .next = next_, \ - } - -/* - * Set current device - */ -#define REG_SCRIPT_SET_DEV(dev_) \ - { .command = REG_SCRIPT_COMMAND_SET_DEV, \ - .dev = dev_, \ - } - -/* - * Last script entry. All tables need to end with REG_SCRIPT_END. - */ -#define REG_SCRIPT_END \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) - -void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); - -#endif /* REG_SCRIPT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5298bbe..9da90d1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -83,8 +83,6 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c -ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c - romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c smm-y += cbfs.c memcmp.c diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c deleted file mode 100644 index 647723b..0000000 --- a/src/lib/reg_script.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/resource.h> -#include <device/pci.h> -#include <stdint.h> -#include <reg_script.h> - -#if CONFIG_ARCH_X86 -#include <cpu/x86/msr.h> -#endif - -#if CONFIG_SOC_INTEL_BAYTRAIL -#include <baytrail/iosf.h> -#endif - -#define POLL_DELAY 100 /* 100us */ -#if defined(__PRE_RAM__) -#define EMPTY_DEV 0 -#else -#define EMPTY_DEV NULL -#endif - -struct reg_script_context { - device_t dev; - struct resource *res; - const struct reg_script *step; -}; - -static inline void reg_script_set_dev(struct reg_script_context *ctx, - device_t dev) -{ - ctx->dev = dev; - ctx->res = NULL; -} - -static inline void reg_script_set_step(struct reg_script_context *ctx, - const struct reg_script *step) -{ - ctx->step = step; -} - -static inline const struct reg_script * -reg_script_get_step(struct reg_script_context *ctx) -{ - return ctx->step; -} - -static struct resource *reg_script_get_resource(struct reg_script_context *ctx) -{ -#if defined(__PRE_RAM__) - return NULL; -#else - struct resource *res; - const struct reg_script *step = reg_script_get_step(ctx); - - res = ctx->res; - - if (res != NULL && res->index == step->res_index) - return res; - - res = find_resource(ctx->dev, step->res_index); - ctx->res = res; - return res; -#endif -} - -static uint32_t reg_script_read_pci(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return pci_read_config8(ctx->dev, step->reg); - case REG_SCRIPT_SIZE_16: - return pci_read_config16(ctx->dev, step->reg); - case REG_SCRIPT_SIZE_32: - return pci_read_config32(ctx->dev, step->reg); - } - return 0; -} - -static void reg_script_write_pci(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - pci_write_config8(ctx->dev, step->reg, step->value); - break; - case REG_SCRIPT_SIZE_16: - pci_write_config16(ctx->dev, step->reg, step->value); - break; - case REG_SCRIPT_SIZE_32: - pci_write_config32(ctx->dev, step->reg, step->value); - break; - } -} - -static uint32_t reg_script_read_io(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return inb(step->reg); - case REG_SCRIPT_SIZE_16: - return inw(step->reg); - case REG_SCRIPT_SIZE_32: - return inl(step->reg); - } - return 0; -} - -static void reg_script_write_io(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - outb(step->value, step->reg); - break; - case REG_SCRIPT_SIZE_16: - outw(step->value, step->reg); - break; - case REG_SCRIPT_SIZE_32: - outl(step->value, step->reg); - break; - } -} - -static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return read8(step->reg); - case REG_SCRIPT_SIZE_16: - return read16(step->reg); - case REG_SCRIPT_SIZE_32: - return read32(step->reg); - } - return 0; -} - -static void reg_script_write_mmio(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - write8(step->reg, step->value); - break; - case REG_SCRIPT_SIZE_16: - write16(step->reg, step->value); - break; - case REG_SCRIPT_SIZE_32: - write32(step->reg, step->value); - break; - } -} - -static uint32_t reg_script_read_res(struct reg_script_context *ctx) -{ - struct resource *res; - uint32_t val = 0; - const struct reg_script *step = reg_script_get_step(ctx); - - res = reg_script_get_resource(ctx); - - if (res == NULL) - return val; - - if (res->flags & IORESOURCE_IO) { - const struct reg_script io_step = { - .size = step->size, - .reg = res->base + step->reg, - }; - reg_script_set_step(ctx, &io_step); - val = reg_script_read_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { - const struct reg_script mmio_step = { - .size = step->size, - .reg = res->base + step->reg, - }; - reg_script_set_step(ctx, &mmio_step); - val = reg_script_read_mmio(ctx); - } - reg_script_set_step(ctx, step); - return val; -} - -static void reg_script_write_res(struct reg_script_context *ctx) -{ - struct resource *res; - const struct reg_script *step = reg_script_get_step(ctx); - - res = reg_script_get_resource(ctx); - - if (res == NULL) - return; - - if (res->flags & IORESOURCE_IO) { - const struct reg_script io_step = { - .size = step->size, - .reg = res->base + step->reg, - .value = step->value, - }; - reg_script_set_step(ctx, &io_step); - reg_script_write_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { - const struct reg_script mmio_step = { - .size = step->size, - .reg = res->base + step->reg, - .value = step->value, - }; - reg_script_set_step(ctx, &mmio_step); - reg_script_write_mmio(ctx); - } - reg_script_set_step(ctx, step); -} - -static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) -{ -#if CONFIG_SOC_INTEL_BAYTRAIL - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->id) { - case IOSF_PORT_AUNIT: - return iosf_aunit_read(step->reg); - case IOSF_PORT_CPU_BUS: - return iosf_cpu_bus_read(step->reg); - case IOSF_PORT_BUNIT: - return iosf_bunit_read(step->reg); - case IOSF_PORT_DUNIT_CH0: - return iosf_dunit_ch0_read(step->reg); - case IOSF_PORT_PMC: - return iosf_punit_read(step->reg); - case IOSF_PORT_USBPHY: - return iosf_usbphy_read(step->reg); - case IOSF_PORT_SEC: - return iosf_sec_read(step->reg); - case IOSF_PORT_0x45: - return iosf_port45_read(step->reg); - case IOSF_PORT_0x46: - return iosf_port46_read(step->reg); - case IOSF_PORT_0x47: - return iosf_port47_read(step->reg); - case IOSF_PORT_SCORE: - return iosf_score_read(step->reg); - case IOSF_PORT_0x55: - return iosf_port55_read(step->reg); - case IOSF_PORT_0x58: - return iosf_port58_read(step->reg); - case IOSF_PORT_0x59: - return iosf_port59_read(step->reg); - case IOSF_PORT_0x5a: - return iosf_port5a_read(step->reg); - case IOSF_PORT_USHPHY: - return iosf_ushphy_read(step->reg); - case IOSF_PORT_SCC: - return iosf_scc_read(step->reg); - case IOSF_PORT_LPSS: - return iosf_lpss_read(step->reg); - case IOSF_PORT_0xa2: - return iosf_porta2_read(step->reg); - case IOSF_PORT_CCU: - return iosf_ccu_read(step->reg); - case IOSF_PORT_SSUS: - return iosf_ssus_read(step->reg); - default: - printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", - step->id); - break; - } -#endif - return 0; -} - -static void reg_script_write_iosf(struct reg_script_context *ctx) -{ -#if CONFIG_SOC_INTEL_BAYTRAIL - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->id) { - case IOSF_PORT_AUNIT: - iosf_aunit_write(step->reg, step->value); - break; - case IOSF_PORT_CPU_BUS: - iosf_cpu_bus_write(step->reg, step->value); - break; - case IOSF_PORT_BUNIT: - iosf_bunit_write(step->reg, step->value); - break; - case IOSF_PORT_DUNIT_CH0: - iosf_dunit_write(step->reg, step->value); - break; - case IOSF_PORT_PMC: - iosf_punit_write(step->reg, step->value); - break; - case IOSF_PORT_USBPHY: - iosf_usbphy_write(step->reg, step->value); - break; - case IOSF_PORT_SEC: - iosf_sec_write(step->reg, step->value); - break; - case IOSF_PORT_0x45: - iosf_port45_write(step->reg, step->value); - break; - case IOSF_PORT_0x46: - iosf_port46_write(step->reg, step->value); - break; - case IOSF_PORT_0x47: - iosf_port47_write(step->reg, step->value); - break; - case IOSF_PORT_SCORE: - iosf_score_write(step->reg, step->value); - break; - case IOSF_PORT_0x55: - iosf_port55_write(step->reg, step->value); - break; - case IOSF_PORT_0x58: - iosf_port58_write(step->reg, step->value); - break; - case IOSF_PORT_0x59: - iosf_port59_write(step->reg, step->value); - break; - case IOSF_PORT_0x5a: - iosf_port5a_write(step->reg, step->value); - break; - case IOSF_PORT_USHPHY: - iosf_ushphy_write(step->reg, step->value); - break; - case IOSF_PORT_SCC: - iosf_scc_write(step->reg, step->value); - break; - case IOSF_PORT_LPSS: - iosf_lpss_write(step->reg, step->value); - break; - case IOSF_PORT_0xa2: - iosf_porta2_write(step->reg, step->value); - break; - case IOSF_PORT_CCU: - iosf_ccu_write(step->reg, step->value); - break; - case IOSF_PORT_SSUS: - iosf_ssus_write(step->reg, step->value); - break; - default: - printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", - step->id); - break; - } -#endif -} - -static uint64_t reg_script_read_msr(struct reg_script_context *ctx) -{ -#if CONFIG_ARCH_X86 - const struct reg_script *step = reg_script_get_step(ctx); - msr_t msr = rdmsr(step->reg); - uint64_t value = msr.hi; - value = msr.hi; - value <<= 32; - value |= msr.lo; - return value; -#endif -} - -static void reg_script_write_msr(struct reg_script_context *ctx) -{ -#if CONFIG_ARCH_X86 - const struct reg_script *step = reg_script_get_step(ctx); - msr_t msr; - msr.hi = step->value >> 32; - msr.lo = step->value & 0xffffffff; - wrmsr(step->reg, msr); -#endif -} - -static uint64_t reg_script_read(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->type) { - case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); - case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); - case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); - case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); - case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); - case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); - } - return 0; -} - -static void reg_script_write(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->type) { - case REG_SCRIPT_TYPE_PCI: - reg_script_write_pci(ctx); - break; - case REG_SCRIPT_TYPE_IO: - reg_script_write_io(ctx); - break; - case REG_SCRIPT_TYPE_MMIO: - reg_script_write_mmio(ctx); - break; - case REG_SCRIPT_TYPE_RES: - reg_script_write_res(ctx); - break; - case REG_SCRIPT_TYPE_IOSF: - reg_script_write_iosf(ctx); - break; - case REG_SCRIPT_TYPE_MSR: - reg_script_write_msr(ctx); - break; - } -} - -static void reg_script_rmw(struct reg_script_context *ctx) -{ - uint64_t value; - const struct reg_script *step = reg_script_get_step(ctx); - struct reg_script write_step = *step; - - value = reg_script_read(ctx); - value &= step->mask; - value |= step->value; - write_step.value = value; - reg_script_set_step(ctx, &write_step); - reg_script_write(ctx); - reg_script_set_step(ctx, step); -} - -/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT - * as recursive call with a new context that has the same dev and resource - * as the previous one. That will run to completion and then move on to the - * next step of the previous context. */ -static void reg_script_run_next(struct reg_script_context *ctx, - const struct reg_script *step); - - -static void reg_script_run_step(struct reg_script_context *ctx, - const struct reg_script *step) -{ - uint64_t value = 0, try; - - switch (step->command) { - case REG_SCRIPT_COMMAND_READ: - (void)reg_script_read(ctx); - break; - case REG_SCRIPT_COMMAND_WRITE: - reg_script_write(ctx); - break; - case REG_SCRIPT_COMMAND_RMW: - reg_script_rmw(ctx); - break; - case REG_SCRIPT_COMMAND_POLL: - for (try = 0; try < step->timeout; try += POLL_DELAY) { - value = reg_script_read(ctx) & step->mask; - if (value == step->value) - break; - udelay(POLL_DELAY); - } - if (try >= step->timeout) - printk(BIOS_WARNING, "%s: POLL timeout waiting for " - "0x%x to be 0x%lx, got 0x%lx\n", __func__, - step->reg, (unsigned long)step->value, - (unsigned long)value); - break; - case REG_SCRIPT_COMMAND_SET_DEV: - reg_script_set_dev(ctx, step->dev); - break; - case REG_SCRIPT_COMMAND_NEXT: - reg_script_run_next(ctx, step->next); - break; - default: - printk(BIOS_WARNING, "Invalid command: %08x\n", - step->command); - break; - } -} - -static void reg_script_run_with_context(struct reg_script_context *ctx) -{ - while (1) { - const struct reg_script *step = reg_script_get_step(ctx); - - if (step->command == REG_SCRIPT_COMMAND_END) - break; - - reg_script_run_step(ctx, step); - reg_script_set_step(ctx, step + 1); - } -} - -static void reg_script_run_next(struct reg_script_context *prev_ctx, - const struct reg_script *step) -{ - struct reg_script_context ctx; - - /* Use prev context as a basis but start at a new step. */ - ctx = *prev_ctx; - reg_script_set_step(&ctx, step); - reg_script_run_with_context(&ctx); -} - -void reg_script_run_on_dev(device_t dev, const struct reg_script *step) -{ - struct reg_script_context ctx; - - reg_script_set_dev(&ctx, dev); - reg_script_set_step(&ctx, step); - reg_script_run_with_context(&ctx); -} - -void reg_script_run(const struct reg_script *step) -{ - reg_script_run_on_dev(EMPTY_DEV, step); -} diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d4f653e..886caf4 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += reg_script.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/reg_script.c b/src/soc/intel/baytrail/reg_script.c new file mode 100644 index 0000000..78749fd --- /dev/null +++ b/src/soc/intel/baytrail/reg_script.c @@ -0,0 +1,538 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/resource.h> +#include <device/pci.h> +#include <stdint.h> +#include <reg_script.h> + +#include <cpu/x86/msr.h> +#include <baytrail/iosf.h> + +#define POLL_DELAY 100 /* 100us */ +#if defined(__PRE_RAM__) +#define EMPTY_DEV 0 +#else +#define EMPTY_DEV NULL +#endif + +struct reg_script_context { + device_t dev; + struct resource *res; + const struct reg_script *step; +}; + +static inline void reg_script_set_dev(struct reg_script_context *ctx, + device_t dev) +{ + ctx->dev = dev; + ctx->res = NULL; +} + +static inline void reg_script_set_step(struct reg_script_context *ctx, + const struct reg_script *step) +{ + ctx->step = step; +} + +static inline const struct reg_script * +reg_script_get_step(struct reg_script_context *ctx) +{ + return ctx->step; +} + +static struct resource *reg_script_get_resource(struct reg_script_context *ctx) +{ +#if defined(__PRE_RAM__) + return NULL; +#else + struct resource *res; + const struct reg_script *step = reg_script_get_step(ctx); + + res = ctx->res; + + if (res != NULL && res->index == step->res_index) + return res; + + res = find_resource(ctx->dev, step->res_index); + ctx->res = res; + return res; +#endif +} + +static uint32_t reg_script_read_pci(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + return pci_read_config8(ctx->dev, step->reg); + case REG_SCRIPT_SIZE_16: + return pci_read_config16(ctx->dev, step->reg); + case REG_SCRIPT_SIZE_32: + return pci_read_config32(ctx->dev, step->reg); + } + return 0; +} + +static void reg_script_write_pci(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + pci_write_config8(ctx->dev, step->reg, step->value); + break; + case REG_SCRIPT_SIZE_16: + pci_write_config16(ctx->dev, step->reg, step->value); + break; + case REG_SCRIPT_SIZE_32: + pci_write_config32(ctx->dev, step->reg, step->value); + break; + } +} + +static uint32_t reg_script_read_io(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + return inb(step->reg); + case REG_SCRIPT_SIZE_16: + return inw(step->reg); + case REG_SCRIPT_SIZE_32: + return inl(step->reg); + } + return 0; +} + +static void reg_script_write_io(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + outb(step->value, step->reg); + break; + case REG_SCRIPT_SIZE_16: + outw(step->value, step->reg); + break; + case REG_SCRIPT_SIZE_32: + outl(step->value, step->reg); + break; + } +} + +static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + return read8(step->reg); + case REG_SCRIPT_SIZE_16: + return read16(step->reg); + case REG_SCRIPT_SIZE_32: + return read32(step->reg); + } + return 0; +} + +static void reg_script_write_mmio(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->size) { + case REG_SCRIPT_SIZE_8: + write8(step->reg, step->value); + break; + case REG_SCRIPT_SIZE_16: + write16(step->reg, step->value); + break; + case REG_SCRIPT_SIZE_32: + write32(step->reg, step->value); + break; + } +} + +static uint32_t reg_script_read_res(struct reg_script_context *ctx) +{ + struct resource *res; + uint32_t val = 0; + const struct reg_script *step = reg_script_get_step(ctx); + + res = reg_script_get_resource(ctx); + + if (res == NULL) + return val; + + if (res->flags & IORESOURCE_IO) { + const struct reg_script io_step = { + .size = step->size, + .reg = res->base + step->reg, + }; + reg_script_set_step(ctx, &io_step); + val = reg_script_read_io(ctx); + } + else if (res->flags & IORESOURCE_MEM) { + const struct reg_script mmio_step = { + .size = step->size, + .reg = res->base + step->reg, + }; + reg_script_set_step(ctx, &mmio_step); + val = reg_script_read_mmio(ctx); + } + reg_script_set_step(ctx, step); + return val; +} + +static void reg_script_write_res(struct reg_script_context *ctx) +{ + struct resource *res; + const struct reg_script *step = reg_script_get_step(ctx); + + res = reg_script_get_resource(ctx); + + if (res == NULL) + return; + + if (res->flags & IORESOURCE_IO) { + const struct reg_script io_step = { + .size = step->size, + .reg = res->base + step->reg, + .value = step->value, + }; + reg_script_set_step(ctx, &io_step); + reg_script_write_io(ctx); + } + else if (res->flags & IORESOURCE_MEM) { + const struct reg_script mmio_step = { + .size = step->size, + .reg = res->base + step->reg, + .value = step->value, + }; + reg_script_set_step(ctx, &mmio_step); + reg_script_write_mmio(ctx); + } + reg_script_set_step(ctx, step); +} + +static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->id) { + case IOSF_PORT_AUNIT: + return iosf_aunit_read(step->reg); + case IOSF_PORT_CPU_BUS: + return iosf_cpu_bus_read(step->reg); + case IOSF_PORT_BUNIT: + return iosf_bunit_read(step->reg); + case IOSF_PORT_DUNIT_CH0: + return iosf_dunit_ch0_read(step->reg); + case IOSF_PORT_PMC: + return iosf_punit_read(step->reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(step->reg); + case IOSF_PORT_SEC: + return iosf_sec_read(step->reg); + case IOSF_PORT_0x45: + return iosf_port45_read(step->reg); + case IOSF_PORT_0x46: + return iosf_port46_read(step->reg); + case IOSF_PORT_0x47: + return iosf_port47_read(step->reg); + case IOSF_PORT_SCORE: + return iosf_score_read(step->reg); + case IOSF_PORT_0x55: + return iosf_port55_read(step->reg); + case IOSF_PORT_0x58: + return iosf_port58_read(step->reg); + case IOSF_PORT_0x59: + return iosf_port59_read(step->reg); + case IOSF_PORT_0x5a: + return iosf_port5a_read(step->reg); + case IOSF_PORT_USHPHY: + return iosf_ushphy_read(step->reg); + case IOSF_PORT_SCC: + return iosf_scc_read(step->reg); + case IOSF_PORT_LPSS: + return iosf_lpss_read(step->reg); + case IOSF_PORT_0xa2: + return iosf_porta2_read(step->reg); + case IOSF_PORT_CCU: + return iosf_ccu_read(step->reg); + case IOSF_PORT_SSUS: + return iosf_ssus_read(step->reg); + default: + printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", + step->id); + break; + } + return 0; +} + +static void reg_script_write_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->id) { + case IOSF_PORT_AUNIT: + iosf_aunit_write(step->reg, step->value); + break; + case IOSF_PORT_CPU_BUS: + iosf_cpu_bus_write(step->reg, step->value); + break; + case IOSF_PORT_BUNIT: + iosf_bunit_write(step->reg, step->value); + break; + case IOSF_PORT_DUNIT_CH0: + iosf_dunit_write(step->reg, step->value); + break; + case IOSF_PORT_PMC: + iosf_punit_write(step->reg, step->value); + break; + case IOSF_PORT_USBPHY: + iosf_usbphy_write(step->reg, step->value); + break; + case IOSF_PORT_SEC: + iosf_sec_write(step->reg, step->value); + break; + case IOSF_PORT_0x45: + iosf_port45_write(step->reg, step->value); + break; + case IOSF_PORT_0x46: + iosf_port46_write(step->reg, step->value); + break; + case IOSF_PORT_0x47: + iosf_port47_write(step->reg, step->value); + break; + case IOSF_PORT_SCORE: + iosf_score_write(step->reg, step->value); + break; + case IOSF_PORT_0x55: + iosf_port55_write(step->reg, step->value); + break; + case IOSF_PORT_0x58: + iosf_port58_write(step->reg, step->value); + break; + case IOSF_PORT_0x59: + iosf_port59_write(step->reg, step->value); + break; + case IOSF_PORT_0x5a: + iosf_port5a_write(step->reg, step->value); + break; + case IOSF_PORT_USHPHY: + iosf_ushphy_write(step->reg, step->value); + break; + case IOSF_PORT_SCC: + iosf_scc_write(step->reg, step->value); + break; + case IOSF_PORT_LPSS: + iosf_lpss_write(step->reg, step->value); + break; + case IOSF_PORT_0xa2: + iosf_porta2_write(step->reg, step->value); + break; + case IOSF_PORT_CCU: + iosf_ccu_write(step->reg, step->value); + break; + case IOSF_PORT_SSUS: + iosf_ssus_write(step->reg, step->value); + break; + default: + printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", + step->id); + break; + } +} + +static uint64_t reg_script_read_msr(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr = rdmsr(step->reg); + uint64_t value = msr.hi; + value = msr.hi; + value <<= 32; + value |= msr.lo; + return value; +} + +static void reg_script_write_msr(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr; + msr.hi = step->value >> 32; + msr.lo = step->value & 0xffffffff; + wrmsr(step->reg, msr); +} + +static uint64_t reg_script_read(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->type) { + case REG_SCRIPT_TYPE_PCI: + return reg_script_read_pci(ctx); + case REG_SCRIPT_TYPE_IO: + return reg_script_read_io(ctx); + case REG_SCRIPT_TYPE_MMIO: + return reg_script_read_mmio(ctx); + case REG_SCRIPT_TYPE_RES: + return reg_script_read_res(ctx); + case REG_SCRIPT_TYPE_IOSF: + return reg_script_read_iosf(ctx); + case REG_SCRIPT_TYPE_MSR: + return reg_script_read_msr(ctx); + } + return 0; +} + +static void reg_script_write(struct reg_script_context *ctx) +{ + const struct reg_script *step = reg_script_get_step(ctx); + + switch (step->type) { + case REG_SCRIPT_TYPE_PCI: + reg_script_write_pci(ctx); + break; + case REG_SCRIPT_TYPE_IO: + reg_script_write_io(ctx); + break; + case REG_SCRIPT_TYPE_MMIO: + reg_script_write_mmio(ctx); + break; + case REG_SCRIPT_TYPE_RES: + reg_script_write_res(ctx); + break; + case REG_SCRIPT_TYPE_IOSF: + reg_script_write_iosf(ctx); + break; + case REG_SCRIPT_TYPE_MSR: + reg_script_write_msr(ctx); + break; + } +} + +static void reg_script_rmw(struct reg_script_context *ctx) +{ + uint64_t value; + const struct reg_script *step = reg_script_get_step(ctx); + struct reg_script write_step = *step; + + value = reg_script_read(ctx); + value &= step->mask; + value |= step->value; + write_step.value = value; + reg_script_set_step(ctx, &write_step); + reg_script_write(ctx); + reg_script_set_step(ctx, step); +} + +/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT + * as recursive call with a new context that has the same dev and resource + * as the previous one. That will run to completion and then move on to the + * next step of the previous context. */ +static void reg_script_run_next(struct reg_script_context *ctx, + const struct reg_script *step); + + +static void reg_script_run_step(struct reg_script_context *ctx, + const struct reg_script *step) +{ + uint64_t value = 0, try; + + switch (step->command) { + case REG_SCRIPT_COMMAND_READ: + (void)reg_script_read(ctx); + break; + case REG_SCRIPT_COMMAND_WRITE: + reg_script_write(ctx); + break; + case REG_SCRIPT_COMMAND_RMW: + reg_script_rmw(ctx); + break; + case REG_SCRIPT_COMMAND_POLL: + for (try = 0; try < step->timeout; try += POLL_DELAY) { + value = reg_script_read(ctx) & step->mask; + if (value == step->value) + break; + udelay(POLL_DELAY); + } + if (try >= step->timeout) + printk(BIOS_WARNING, "%s: POLL timeout waiting for " + "0x%x to be 0x%lx, got 0x%lx\n", __func__, + step->reg, (unsigned long)step->value, + (unsigned long)value); + break; + case REG_SCRIPT_COMMAND_SET_DEV: + reg_script_set_dev(ctx, step->dev); + break; + case REG_SCRIPT_COMMAND_NEXT: + reg_script_run_next(ctx, step->next); + break; + default: + printk(BIOS_WARNING, "Invalid command: %08x\n", + step->command); + break; + } +} + +static void reg_script_run_with_context(struct reg_script_context *ctx) +{ + while (1) { + const struct reg_script *step = reg_script_get_step(ctx); + + if (step->command == REG_SCRIPT_COMMAND_END) + break; + + reg_script_run_step(ctx, step); + reg_script_set_step(ctx, step + 1); + } +} + +static void reg_script_run_next(struct reg_script_context *prev_ctx, + const struct reg_script *step) +{ + struct reg_script_context ctx; + + /* Use prev context as a basis but start at a new step. */ + ctx = *prev_ctx; + reg_script_set_step(&ctx, step); + reg_script_run_with_context(&ctx); +} + +void reg_script_run_on_dev(device_t dev, const struct reg_script *step) +{ + struct reg_script_context ctx; + + reg_script_set_dev(&ctx, dev); + reg_script_set_step(&ctx, step); + reg_script_run_with_context(&ctx); +} + +void reg_script_run(const struct reg_script *step) +{ + reg_script_run_on_dev(EMPTY_DEV, step); +} diff --git a/src/soc/intel/baytrail/reg_script.h b/src/soc/intel/baytrail/reg_script.h new file mode 100644 index 0000000..72e1e96 --- /dev/null +++ b/src/soc/intel/baytrail/reg_script.h @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef REG_SCRIPT_H +#define REG_SCRIPT_H + +#include <stdint.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/resource.h> + +/* + * The reg script library is a way to provide data-driven I/O accesses for + * initializing devices. It currently supports PCI, legacy I/O, + * memory-mapped I/O, and IOSF accesses. + * + * In order to simplify things for the developer the following features + * are employed: + * - Chaining of tables that allow runtime tables to chain to compile-time + * tables. + * - Notion of current device (device_t) being worked on. This allows for + * PCI config, io, and mmio on a particular device's resources. + * + * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push + * and pop of the context. A chained reg_script inherits the previous + * context (such as current device), but it does not impact the previous + * context in any way. + */ + +enum { + REG_SCRIPT_COMMAND_READ, + REG_SCRIPT_COMMAND_WRITE, + REG_SCRIPT_COMMAND_RMW, + REG_SCRIPT_COMMAND_POLL, + REG_SCRIPT_COMMAND_SET_DEV, + REG_SCRIPT_COMMAND_NEXT, + REG_SCRIPT_COMMAND_END, +}; + +enum { + REG_SCRIPT_TYPE_PCI, + REG_SCRIPT_TYPE_IO, + REG_SCRIPT_TYPE_MMIO, + REG_SCRIPT_TYPE_RES, + REG_SCRIPT_TYPE_IOSF, + REG_SCRIPT_TYPE_MSR, +}; + +enum { + REG_SCRIPT_SIZE_8, + REG_SCRIPT_SIZE_16, + REG_SCRIPT_SIZE_32, + REG_SCRIPT_SIZE_64, +}; + +struct reg_script { + uint32_t command; + uint32_t type; + uint32_t size; + uint32_t reg; + uint64_t mask; + uint64_t value; + uint32_t timeout; + union { + uint32_t id; + const struct reg_script *next; + device_t dev; + unsigned int res_index; + }; +}; + +/* Internal helper Macros. */ + +#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ + mask_, value_, timeout_, id_) \ + { .command = cmd_, \ + .type = type_, \ + .size = size_, \ + .reg = reg_, \ + .mask = mask_, \ + .value = value_, \ + .timeout = timeout_, \ + .id = id_, \ + } + +#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \ + mask_, value_, timeout_) \ + { .command = cmd_, \ + .type = type_, \ + .size = size_, \ + .reg = reg_, \ + .mask = mask_, \ + .value = value_, \ + .timeout = timeout_, \ + .res_index = res_index_, \ + } + +/* + * PCI + */ + +#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_PCI, \ + REG_SCRIPT_SIZE_##bits_, \ + reg_, mask_, value_, timeout_, 0) +#define REG_PCI_READ8(reg_) \ + REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0) +#define REG_PCI_READ16(reg_) \ + REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0) +#define REG_PCI_READ32(reg_) \ + REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0) +#define REG_PCI_WRITE8(reg_, value_) \ + REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0) +#define REG_PCI_WRITE16(reg_, value_) \ + REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0) +#define REG_PCI_WRITE32(reg_, value_) \ + REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0) +#define REG_PCI_RMW8(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0) +#define REG_PCI_RMW16(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) +#define REG_PCI_RMW32(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) +#define REG_PCI_OR8(reg_, value_) \ + REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) +#define REG_PCI_OR16(reg_, value_) \ + REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0) +#define REG_PCI_OR32(reg_, value_) \ + REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0) +#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_) +#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) +#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) + +/* + * Legacy IO + */ + +#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_IO, \ + REG_SCRIPT_SIZE_##bits_, \ + reg_, mask_, value_, timeout_, 0) +#define REG_IO_READ8(reg_) \ + REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0) +#define REG_IO_READ16(reg_) \ + REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0) +#define REG_IO_READ32(reg_) \ + REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0) +#define REG_IO_WRITE8(reg_, value_) \ + REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0) +#define REG_IO_WRITE16(reg_, value_) \ + REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0) +#define REG_IO_WRITE32(reg_, value_) \ + REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0) +#define REG_IO_RMW8(reg_, mask_, value_) \ + REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0) +#define REG_IO_RMW16(reg_, mask_, value_) \ + REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) +#define REG_IO_RMW32(reg_, mask_, value_) \ + REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) +#define REG_IO_OR8(reg_, value_) \ + REG_SCRIPT_IO_RMW8(_reg, 0xff, value) +#define REG_IO_OR16(reg_, value_) \ + REG_SCRIPT_IO_RMW16(_reg, 0xffff, value) +#define REG_IO_OR32(reg_, value_) \ + REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value) +#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_) +#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) +#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) + +/* + * Memory Mapped IO + */ + +#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_MMIO, \ + REG_SCRIPT_SIZE_##bits_, \ + reg_, mask_, value_, timeout_, 0) +#define REG_MMIO_READ8(reg_) \ + REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0) +#define REG_MMIO_READ16(reg_) \ + REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0) +#define REG_MMIO_READ32(reg_) \ + REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0) +#define REG_MMIO_WRITE8(reg_, value_) \ + REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0) +#define REG_MMIO_WRITE16(reg_, value_) \ + REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0) +#define REG_MMIO_WRITE32(reg_, value_) \ + REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0) +#define REG_MMIO_RMW8(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0) +#define REG_MMIO_RMW16(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) +#define REG_MMIO_RMW32(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) +#define REG_MMIO_OR8(reg_, value_) \ + REG_MMIO_RMW8(reg_, 0xff, value_) +#define REG_MMIO_OR16(reg_, value_) \ + REG_MMIO_RMW16(reg_, 0xffff, value_) +#define REG_MMIO_OR32(reg_, value_) \ + REG_MMIO_RMW32(reg_, 0xffffffff, value_) +#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_) +#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) +#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) + +/* + * Access through a device's resource such as a Base Address Register (BAR) + */ + +#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_RES, bar_, \ + REG_SCRIPT_SIZE_##bits_, \ + reg_, mask_, value_, timeout_) +#define REG_RES_READ8(bar_, reg_) \ + REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0) +#define REG_RES_READ16(bar_, reg_) \ + REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0) +#define REG_RES_READ32(bar_, reg_) \ + REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0) +#define REG_RES_WRITE8(bar_, reg_, value_) \ + REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0) +#define REG_RES_WRITE16(bar_, reg_, value_) \ + REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0) +#define REG_RES_WRITE32(bar_, reg_, value_) \ + REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0) +#define REG_RES_RMW8(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0) +#define REG_RES_RMW16(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) +#define REG_RES_RMW32(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) +#define REG_RES_OR8(bar_, reg_, value_) \ + REG_RES_RMW8(bar_, reg_, 0xff, value_) +#define REG_RES_OR16(bar_, reg_, value_) \ + REG_RES_RMW16(bar_, reg_, 0xffff, value_) +#define REG_RES_OR32(bar_, reg_, value_) \ + REG_RES_RMW32(bar_, reg_, 0xffffffff, value_) +#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_) +#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) +#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) + +/* + * IO Sideband Function + */ + +#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_IOSF, \ + REG_SCRIPT_SIZE_32, \ + reg_, mask_, value_, timeout_, unit_) +#define REG_IOSF_READ(unit_, reg_) \ + REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) +#define REG_IOSF_WRITE(unit_, reg_, value_) \ + REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) +#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ + REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) +#define REG_IOSF_OR(unit_, reg_, value_) \ + REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) +#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) + +/* + * CPU Model Specific Register + */ + +#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_MSR, \ + REG_SCRIPT_SIZE_64, \ + reg_, mask_, value_, timeout_, 0) +#define REG_MSR_READ(reg_) \ + REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) +#define REG_MSR_WRITE(reg_, value_) \ + REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) +#define REG_MSR_RMW(reg_, mask_, value_) \ + REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) +#define REG_MSR_OR(reg_, value_) \ + REG_MSR_RMW(reg_, -1ULL, value_) +#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) + +/* + * Chain to another table. + */ +#define REG_SCRIPT_NEXT(next_) \ + { .command = REG_SCRIPT_COMMAND_NEXT, \ + .next = next_, \ + } + +/* + * Set current device + */ +#define REG_SCRIPT_SET_DEV(dev_) \ + { .command = REG_SCRIPT_COMMAND_SET_DEV, \ + .dev = dev_, \ + } + +/* + * Last script entry. All tables need to end with REG_SCRIPT_END. + */ +#define REG_SCRIPT_END \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) + +void reg_script_run(const struct reg_script *script); +void reg_script_run_on_dev(device_t dev, const struct reg_script *step); + +#endif /* REG_SCRIPT_H */ diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index cb4757b..c2b747c 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP - select REG_SCRIPT select SMP select SPI_FLASH select SSE2

1 0

Patch set updated for coreboot: ae9291b intel/fsp_baytrail: remove sole use of reg_script
by Patrick Georgi 04 Aug '14

04 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6297 -gerrit commit ae9291b2f6251d0f58bd9ab07f184be5a652fa6a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jul 16 19:30:18 2014 +0200 intel/fsp_baytrail: remove sole use of reg_script It's a baytrail specific API that snuck in, removing sole non-FSP-baytrail use. Change-Id: Iece1ec6c97172680c874ef9de7b90a8d5d5357af Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/cpu/x86/msr.h | 17 +++++++++++++++++ src/soc/intel/fsp_baytrail/cpu.c | 17 +++++------------ 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 40926df..6cba326 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -17,6 +17,8 @@ static void wrmsr(unsigned long index, msr_t msr) #else +#include <stdint.h> + typedef struct msr_struct { unsigned lo; @@ -59,6 +61,21 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms ); } +static inline void rmw_msr(unsigned index, u64 mask, u64 value) +{ + msr_t tmp = rdmsr(index); + tmp.lo &= mask; + tmp.hi &= mask >> 32; + tmp.lo |= value; + tmp.hi |= value >> 32; + wrmsr(index, tmp); +} + +static inline void or_msr(unsigned index, u64 value) +{ + rmw_msr(index, ~0, value); +} + #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index f260880..1243632 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -29,7 +29,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <reg_script.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> @@ -58,16 +57,6 @@ static int adjust_apic_id(int index, int apic_id) return 2 * index; } -/* Core level MSRs */ -const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -103,7 +92,11 @@ static void baytrail_core_init(device_t cpu) enable_turbo(); /* Set core MSRs */ - reg_script_run(core_msr_script); + /* Dynamic L2 shrink enable and threshold */ + rmw_msr(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008); + /* Disable C1E */ + rmw_msr(MSR_POWER_CTL, ~0x2, 0); + or_msr(MSR_POWER_MISC, 0x44); /* Set this core to max frequency ratio */ set_max_freq();

1 0

Patch merged into coreboot/master: 2b48b65 northbridge/intel: Out of bounds write to array in gma.h
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 2b48b65b1980c4edb6391e4ccf6b1bd8313be944 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 23:38:17 2014 +1000 northbridge/intel: Out of bounds write to array in gma.h The signature[] array in the mailbox struct opregion_header_t has IGD_OPREGION_SIGNATURE written to it with a sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This resulted in a silent off-by-one out of bounds illegal write. Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6473 for details. -gerrit

1 0

Patch merged into coreboot/master: 5cfef13 cpu/intel: Fix out-of-bounds read due to off-by-one in condition
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 5cfef13f8d13b378f72b61ba3e4d7eee065f6d26 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 20:00:47 2014 +1000 cpu/intel: Fix out-of-bounds read due to off-by-one in condition If power_limit_1_time > 129 is false then power_limit_1_time can have a value of up to 129 leading to an out-of-bounds illegal read indexing the power_limit_time_sec_to_msr[] array. Thankfully all call sites have been doing the right thing up until now so the issue has not been visible. Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6478 for details. -gerrit

1 0

Patch set updated for coreboot: f88f785 mainboards: Add missing header guards
by HAOUAS Elyes 04 Aug '14

04 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6489 -gerrit commit f88f78505b5f200ef78b73446c2a6778b5a8269c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Aug 4 09:19:27 2014 +0200 mainboards: Add missing header guards Change-Id: If93f5663fce9cc9b1675badcbf9f88525d875e76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/mahogany_fam10/mb_sysconf.h | 7 +++---- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 7 +++---- src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h | 7 +++---- src/mainboard/amd/tilapia_fam10/mb_sysconf.h | 7 +++---- src/mainboard/amd/torpedo/Oem.h | 6 ++++++ src/mainboard/artecgroup/dbe61/spd_table.h | 5 +++++ src/mainboard/asus/m2n-e/hda_verb.h | 5 +++++ src/mainboard/asus/m4a78-em/mb_sysconf.h | 7 +++---- src/mainboard/asus/m4a785-m/mb_sysconf.h | 7 +++---- src/mainboard/dmp/vortex86ex/hda_verb.h | 5 +++++ src/mainboard/getac/p470/hda_verb.h | 5 +++++ src/mainboard/gigabyte/ma785gm/mb_sysconf.h | 7 +++---- src/mainboard/google/bolt/hda_verb.h | 5 +++++ src/mainboard/google/butterfly/hda_verb.h | 4 ++++ src/mainboard/google/falco/hda_verb.h | 5 +++++ src/mainboard/google/link/hda_verb.h | 5 +++++ src/mainboard/google/link/i915io.h | 5 +++++ src/mainboard/google/parrot/hda_verb.h | 5 +++++ src/mainboard/google/peppy/hda_verb.h | 5 +++++ src/mainboard/google/slippy/hda_verb.h | 5 +++++ src/mainboard/google/stout/hda_verb.h | 5 +++++ src/mainboard/hp/dl145_g1/mb_sysconf.h | 6 +++--- src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h | 7 +++---- src/mainboard/intel/baskingridge/hda_verb.h | 5 +++++ src/mainboard/intel/cougar_canyon2/hda_verb.h | 5 +++++ src/mainboard/intel/eagleheights/ioapic.h | 5 +++++ src/mainboard/intel/emeraldlake2/hda_verb.h | 5 +++++ src/mainboard/intel/wtm2/hda_verb.h | 5 +++++ src/mainboard/intel/xe7501devkit/ioapic.h | 5 +++++ src/mainboard/iwave/iWRainbowG6/hda_verb.h | 5 +++++ src/mainboard/iwill/dk8_htx/mb_sysconf.h | 7 +++---- src/mainboard/kontron/ktqm77/hda_verb.h | 6 ++++++ src/mainboard/lenovo/t520/hda_verb.h | 4 ++++ src/mainboard/lenovo/t530/hda_verb.h | 4 ++++ src/mainboard/lenovo/x201/hda_verb.h | 5 +++++ src/mainboard/lenovo/x230/hda_verb.h | 4 ++++ src/mainboard/msi/ms9282/mb_sysconf.h | 7 +++---- src/mainboard/nvidia/l1_2pvv/hda_verb.h | 5 +++++ src/mainboard/packardbell/ms2290/hda_verb.h | 5 +++++ src/mainboard/rca/rm4100/spd_table.h | 5 +++++ src/mainboard/roda/rk9/hda_verb.h | 5 +++++ src/mainboard/samsung/lumpy/hda_verb.h | 5 +++++ src/mainboard/samsung/stumpy/hda_verb.h | 5 +++++ src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h | 7 +++---- src/mainboard/technexion/tim5690/speaker.h | 5 +++++ src/mainboard/technexion/tim5690/tn_post_code.h | 6 +++++- src/mainboard/technexion/tim5690/vgabios.h | 5 +++++ src/mainboard/thomson/ip1000/spd_table.h | 5 +++++ 48 files changed, 214 insertions(+), 48 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h index 25d63d5..ee80c3a 100644 --- a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h +++ b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_AMD_MAHOGANY_FAM10_MB_SYSCONF_H +#define MAINBOARD_AMD_MAHOGANY_FAM10_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_AMD_MAHOGANY_FAM10_MB_SYSCONF_H */ diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index ef3dace..98b142a 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -1,6 +1,5 @@ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_AMD_SERENGETI_CHEETAH_MB_SYSCONF_H +#define MAINBOARD_AMD_SERENGETI_CHEETAH_MB_SYSCONF_H struct mb_sysconf_t { unsigned char bus_8132_0; @@ -24,4 +23,4 @@ struct mb_sysconf_t { }; -#endif +#endif /* MAINBOARD_AMD_SERENGETI_CHEETAH_MB_SYSCONF_H */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h index 4fb3f18..d87c3b9 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_AMD_SERENGETI_CHEETAH_FAM10_MB_SYSCONF_H +#define MAINBOARD_AMD_SERENGETI_CHEETAH_FAM10_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_8132_0; @@ -39,4 +38,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_AMD_SERENGETI_CHEETAH_FAM10_MB_SYSCONF_H */ diff --git a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h index 25d63d5..b684f75 100644 --- a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h +++ b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_AMD_TILAPIA_FAM10_MB_SYSCONF_H +#define MAINBOARD_AMD_TILAPIA_FAM10_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_AMD_TILAPIA_FAM10_MB_SYSCONF_H */ diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 915182e..0be9abe 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,6 +16,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +#ifndef MAINBOARD_AMD_TORPEDO_OEM_H +#define MAINBOARD_AMD_TORPEDO_OEM_H + #ifndef BIOS_SIZE #define BIOS_SIZE 0x04 //04 - 1MB #endif @@ -221,3 +225,5 @@ * */ #define PCIB_SSID 0x780F1022 + +#endif /* MAINBOARD_AMD_TORPEDO_OEM_H */ diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 3d45b6f..a24f5e7 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H +#define MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H + #include <spd.h> struct spd_entry { @@ -51,3 +54,5 @@ const struct spd_entry spd_table [] = {SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ {SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ }; + +#endif /* MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H */ diff --git a/src/mainboard/asus/m2n-e/hda_verb.h b/src/mainboard/asus/m2n-e/hda_verb.h index ec288ba..1ae213c 100644 --- a/src/mainboard/asus/m2n-e/hda_verb.h +++ b/src/mainboard/asus/m2n-e/hda_verb.h @@ -24,6 +24,9 @@ * http://www.analog.com/static/imported-files/data_sheets/AD1988A_1988B.pdf */ +#ifndef MAINBOARD_ASUS_M2N_E_HDA_VERB_H +#define MAINBOARD_ASUS_M2N_E_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x11d4198b, /* Codec Vendor / Device ID: Analog Devices AD1988B */ @@ -120,3 +123,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_ASUS_M2N_E_HDA_VERB_H */ diff --git a/src/mainboard/asus/m4a78-em/mb_sysconf.h b/src/mainboard/asus/m4a78-em/mb_sysconf.h index 25d63d5..cd76936 100644 --- a/src/mainboard/asus/m4a78-em/mb_sysconf.h +++ b/src/mainboard/asus/m4a78-em/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_ASUS_M4A78_EM_MB_SYSCONF_H +#define MAINBOARD_ASUS_M4A78_EM_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_ASUS_M4A78_EM_MB_SYSCONF_H */ diff --git a/src/mainboard/asus/m4a785-m/mb_sysconf.h b/src/mainboard/asus/m4a785-m/mb_sysconf.h index 25d63d5..32e7eef 100644 --- a/src/mainboard/asus/m4a785-m/mb_sysconf.h +++ b/src/mainboard/asus/m4a785-m/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_ASUS_M4A785_M_MB_SYSCONF_H +#define MAINBOARD_ASUS_M4A785_M_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_ASUS_M4A785_M_MB_SYSCONF_H */ diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h index 0556315..67b1e12 100644 --- a/src/mainboard/dmp/vortex86ex/hda_verb.h +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H +#define MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 @@ -105,3 +108,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H */ diff --git a/src/mainboard/getac/p470/hda_verb.h b/src/mainboard/getac/p470/hda_verb.h index b7578cc..52d16ba 100644 --- a/src/mainboard/getac/p470/hda_verb.h +++ b/src/mainboard/getac/p470/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GETAC_P470_HDA_VERB_H +#define MAINBOARD_GETAC_P470_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 @@ -106,3 +109,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_GETAC_P470_HDA_VERB_H */ diff --git a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h index 25d63d5..6892d16 100644 --- a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h +++ b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_GIGABYTE_MA785GM_MB_SYSCONF_H +#define MAINBOARD_GIGABYTE_MA785GM_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_GIGABYTE_MA785GM_MB_SYSCONF_H */ diff --git a/src/mainboard/google/bolt/hda_verb.h b/src/mainboard/google/bolt/hda_verb.h index f27480d..653c777 100644 --- a/src/mainboard/google/bolt/hda_verb.h +++ b/src/mainboard/google/bolt/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_BOLT_HDA_VERB_H +#define MAINBOARD_GOOGLE_BOLT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_BOLT_HDA_VERB_H */ diff --git a/src/mainboard/google/butterfly/hda_verb.h b/src/mainboard/google/butterfly/hda_verb.h index 89a81fe..759153b 100644 --- a/src/mainboard/google/butterfly/hda_verb.h +++ b/src/mainboard/google/butterfly/hda_verb.h @@ -23,6 +23,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H +#define MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -262,3 +264,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H */ diff --git a/src/mainboard/google/falco/hda_verb.h b/src/mainboard/google/falco/hda_verb.h index f27480d..d1039ec 100644 --- a/src/mainboard/google/falco/hda_verb.h +++ b/src/mainboard/google/falco/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_FALCO_HDA_VERB_H +#define MAINBOARD_GOOGLE_FALCO_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_FALCO_HDA_VERB_H */ diff --git a/src/mainboard/google/link/hda_verb.h b/src/mainboard/google/link/hda_verb.h index ed18d63..4a6ba76 100644 --- a/src/mainboard/google/link/hda_verb.h +++ b/src/mainboard/google/link/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_LINK_HDA_VERB_H +#define MAINBOARD_GOOGLE_LINK_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x11020011, // Codec Vendor / Device ID: Creative CA0132 @@ -179,3 +182,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_LINK_HDA_VERB_H */ diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h index 6533c81..533bf14 100644 --- a/src/mainboard/google/link/i915io.h +++ b/src/mainboard/google/link/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_LINK_I915IO_H +#define MAINBOARD_GOOGLE_LINK_I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* MAINBOARD_GOOGLE_LINK_I915IO_H */ diff --git a/src/mainboard/google/parrot/hda_verb.h b/src/mainboard/google/parrot/hda_verb.h index ca68ad3..0bbb01d 100644 --- a/src/mainboard/google/parrot/hda_verb.h +++ b/src/mainboard/google/parrot/hda_verb.h @@ -32,6 +32,9 @@ * HDMI PatherPoint */ +#ifndef MAINBOARD_GOOGLE_PARROT_HDA_VERB_H +#define MAINBOARD_GOOGLE_PARROT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 @@ -167,3 +170,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_PARROT_HDA_VERB_H */ diff --git a/src/mainboard/google/peppy/hda_verb.h b/src/mainboard/google/peppy/hda_verb.h index d3a63bf..adadf88 100644 --- a/src/mainboard/google/peppy/hda_verb.h +++ b/src/mainboard/google/peppy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H +#define MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -97,3 +100,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H */ diff --git a/src/mainboard/google/slippy/hda_verb.h b/src/mainboard/google/slippy/hda_verb.h index f27480d..c6351e1 100644 --- a/src/mainboard/google/slippy/hda_verb.h +++ b/src/mainboard/google/slippy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H +#define MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H */ diff --git a/src/mainboard/google/stout/hda_verb.h b/src/mainboard/google/stout/hda_verb.h index 08fc10c..2bd99c0 100644 --- a/src/mainboard/google/stout/hda_verb.h +++ b/src/mainboard/google/stout/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_STOUT_HDA_VERB_H +#define MAINBOARD_GOOGLE_STOUT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek @@ -137,3 +140,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_STOUT_HDA_VERB_H */ diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h index 3dfd5de..168b94b 100644 --- a/src/mainboard/hp/dl145_g1/mb_sysconf.h +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -2,9 +2,9 @@ * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> * Subject to the GNU GPL v2, or (at your option) any later version. */ -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H +#ifndef MAINBOARD_HP_DL145_G1_MB_SYSCONF_H +#define MAINBOARD_HP_DL145_G1_MB_SYSCONF_H struct mb_sysconf_t { unsigned char bus_8131_0; @@ -20,4 +20,4 @@ struct mb_sysconf_t { unsigned sbdn3; }; -#endif +#endif /* MAINBOARD_HP_DL145_G1_MB_SYSCONF_H */ diff --git a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h index 25d63d5..643feae 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h +++ b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_IEI_KINO_780AM2_FAM10_MB_SYSCONF_H +#define MAINBOARD_IEI_KINO_780AM2_FAM10_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_IEI_KINO_780AM2_FAM10_MB_SYSCONF_H */ diff --git a/src/mainboard/intel/baskingridge/hda_verb.h b/src/mainboard/intel/baskingridge/hda_verb.h index 52e5a3d..86a7434 100644 --- a/src/mainboard/intel/baskingridge/hda_verb.h +++ b/src/mainboard/intel/baskingridge/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H +#define MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H */ diff --git a/src/mainboard/intel/cougar_canyon2/hda_verb.h b/src/mainboard/intel/cougar_canyon2/hda_verb.h index f8e83b4..f844e60 100644 --- a/src/mainboard/intel/cougar_canyon2/hda_verb.h +++ b/src/mainboard/intel/cougar_canyon2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H +#define MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI @@ -47,3 +50,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H */ diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h index 4ac7d62..c0d173d 100644 --- a/src/mainboard/intel/eagleheights/ioapic.h +++ b/src/mainboard/intel/eagleheights/ioapic.h @@ -1,2 +1,7 @@ +#ifndef MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H +#define MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H + #define IOAPIC_I3100 2 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 + +#endif /* MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H */ diff --git a/src/mainboard/intel/emeraldlake2/hda_verb.h b/src/mainboard/intel/emeraldlake2/hda_verb.h index 52e5a3d..41c03c5 100644 --- a/src/mainboard/intel/emeraldlake2/hda_verb.h +++ b/src/mainboard/intel/emeraldlake2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H +#define MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H */ diff --git a/src/mainboard/intel/wtm2/hda_verb.h b/src/mainboard/intel/wtm2/hda_verb.h index cb33add..0505e92 100644 --- a/src/mainboard/intel/wtm2/hda_verb.h +++ b/src/mainboard/intel/wtm2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_WTM2_HDA_VERB_H +#define MAINBOARD_INTEL_WTM2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_WTM2_HDA_VERB_H */ diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 9ac2aee..9cdd4a7 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,3 +1,6 @@ +#ifndef MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H +#define MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H + // IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. @@ -9,3 +12,5 @@ #define P64H2_IOAPIC_VERSION 0x20 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2 + +#endif /* MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H */ diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.h b/src/mainboard/iwave/iWRainbowG6/hda_verb.h index 80ed21d..c1c4f4a 100644 --- a/src/mainboard/iwave/iWRainbowG6/hda_verb.h +++ b/src/mainboard/iwave/iWRainbowG6/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H +#define MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H + static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x111d76d5, // Codec Vendor / Device ID: IDT 92HD81 @@ -92,3 +95,5 @@ static u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H */ diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h index ef3dace..4a80bdb 100644 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ b/src/mainboard/iwill/dk8_htx/mb_sysconf.h @@ -1,6 +1,5 @@ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_IWILL_DK8_HTX_MB_SYSCONF_H +#define MAINBOARD_IWILL_DK8_HTX_MB_SYSCONF_H struct mb_sysconf_t { unsigned char bus_8132_0; @@ -24,4 +23,4 @@ struct mb_sysconf_t { }; -#endif +#endif /* MAINBOARD_IWILL_DK8_HTX_MB_SYSCONF_H */ diff --git a/src/mainboard/kontron/ktqm77/hda_verb.h b/src/mainboard/kontron/ktqm77/hda_verb.h index 53b3fc9..fde7f6c 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.h +++ b/src/mainboard/kontron/ktqm77/hda_verb.h @@ -24,6 +24,10 @@ * Port-Con. Location Def.-Dev. Con.-Type Color Misc Def.-Aso. Seq * 31..30 29..24 23..20 19..16 15..12 11..00 07..04 03..00 */ + +#ifndef MAINBOARD_KONTRON_KTQM77_HDA_VERB_H +#define MAINBOARD_KONTRON_KTQM77_HDA_VERB_H + #define PIN_CFG(pin, val) \ (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ @@ -140,3 +144,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_KONTRON_KTQM77_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/t520/hda_verb.h b/src/mainboard/lenovo/t520/hda_verb.h index 7d5e75a..a841423 100644 --- a/src/mainboard/lenovo/t520/hda_verb.h +++ b/src/mainboard/lenovo/t520/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_T520_HDA_VERB_H +#define MAINBOARD_LENOVO_T520_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_T520_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/t530/hda_verb.h b/src/mainboard/lenovo/t530/hda_verb.h index cc280a1..6ebf2a0 100644 --- a/src/mainboard/lenovo/t530/hda_verb.h +++ b/src/mainboard/lenovo/t530/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_T530_HDA_VERB_H +#define MAINBOARD_LENOVO_T530_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_T530_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/x201/hda_verb.h b/src/mainboard/lenovo/x201/hda_verb.h index d5a8e7c..db10142 100644 --- a/src/mainboard/lenovo/x201/hda_verb.h +++ b/src/mainboard/lenovo/x201/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_LENOVO_X201_HDA_VERB_H +#define MAINBOARD_LENOVO_X201_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ @@ -118,3 +121,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30671E56, 0x30671F58, }; + +#endif /* MAINBOARD_LENOVO_X201_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h index cc280a1..fdb0924 100644 --- a/src/mainboard/lenovo/x230/hda_verb.h +++ b/src/mainboard/lenovo/x230/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_X230_HDA_VERB_H +#define MAINBOARD_LENOVO_X230_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_X230_HDA_VERB_H */ diff --git a/src/mainboard/msi/ms9282/mb_sysconf.h b/src/mainboard/msi/ms9282/mb_sysconf.h index 4b15168..2a6e547 100644 --- a/src/mainboard/msi/ms9282/mb_sysconf.h +++ b/src/mainboard/msi/ms9282/mb_sysconf.h @@ -21,13 +21,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_MSI_MS9282_MB_SYSCONF_H +#define MAINBOARD_MSI_MS9282_MB_SYSCONF_H struct mb_sysconf_t { unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; }; -#endif +#endif /* MAINBOARD_MSI_MS9282_MB_SYSCONF_H */ diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.h b/src/mainboard/nvidia/l1_2pvv/hda_verb.h index 763840b..398dc97 100644 --- a/src/mainboard/nvidia/l1_2pvv/hda_verb.h +++ b/src/mainboard/nvidia/l1_2pvv/hda_verb.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H +#define MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H + static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 @@ -106,3 +109,5 @@ static u32 mainboard_cim_verb_data[] = { extern u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H */ diff --git a/src/mainboard/packardbell/ms2290/hda_verb.h b/src/mainboard/packardbell/ms2290/hda_verb.h index 1e3ccc4..7cc4ddf 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.h +++ b/src/mainboard/packardbell/ms2290/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H +#define MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ @@ -88,3 +91,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30671E56, 0x30671F58, }; + +#endif /* MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H */ diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h index 050bf72..79f5b1c 100644 --- a/src/mainboard/rca/rm4100/spd_table.h +++ b/src/mainboard/rca/rm4100/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_RCA_RM4100_SPD_TABLE_H +#define MAINBOARD_RCA_RM4100_SPD_TABLE_H + #include <spd.h> struct spd_entry { @@ -38,3 +41,5 @@ const struct spd_entry spd_table [] = { {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ }; + +#endif /* MAINBOARD_RCA_RM4100_SPD_TABLE_H */ diff --git a/src/mainboard/roda/rk9/hda_verb.h b/src/mainboard/roda/rk9/hda_verb.h index f99d097..598e141 100644 --- a/src/mainboard/roda/rk9/hda_verb.h +++ b/src/mainboard/roda/rk9/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_RODA_RK9_HDA_VERB_H +#define MAINBOARD_RODA_RK9_HDA_VERB_H + #define PIN_CFG(pin, val) \ (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ @@ -72,3 +75,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; extern const u32 * pc_beep_verbs; extern u32 pc_beep_verbs_size; + +#endif /* MAINBOARD_RODA_RK9_HDA_VERB_H */ diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h index dfadf55..03f8c0a 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.h +++ b/src/mainboard/samsung/lumpy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H +#define MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Realtek ALC262 @@ -79,3 +82,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H */ diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h index b263fbe..851516f 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.h +++ b/src/mainboard/samsung/stumpy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H +#define MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -106,3 +109,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H */ diff --git a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h index 25d63d5..32fe09e 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H +#ifndef MAINBOARD_SUPERMICRO_H8SCM_FAM10_MB_SYSCONF_H +#define MAINBOARD_SUPERMICRO_H8SCM_FAM10_MB_SYSCONF_H struct mb_sysconf_t { u8 bus_isa; @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MAINBOARD_SUPERMICRO_H8SCM_FAM10_MB_SYSCONF_H */ diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h index e4a5fd0..6bee5f5 100644 --- a/src/mainboard/technexion/tim5690/speaker.h +++ b/src/mainboard/technexion/tim5690/speaker.h @@ -18,8 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H +#define MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H + void speaker_init(uint8_t time); void speaker_on_nodelay(void); void speaker_off_nodelay(void); void speaker_on_delay(void); void speaker_off_delay(void); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H */ diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h index 46d7382..a6ae304 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ b/src/mainboard/technexion/tim5690/tn_post_code.h @@ -18,11 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H +#define MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H + #define LED_MESSAGE_START 0xFF #define LED_MESSAGE_FINISH 0x99 #define LED_MESSAGE_RAM 0x01 - #ifdef __PRE_RAM__ // TechNexion's Post Code Initially. @@ -31,3 +33,5 @@ void technexion_post_code_init(void); #endif void technexion_post_code(uint8_t udata8); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H */ diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h index a353011..55b5b46 100644 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ b/src/mainboard/technexion/tim5690/vgabios.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H +#define MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H + /* AMD Chipset */ #define AMD_RS690_INT15 0x4E08 @@ -35,3 +38,5 @@ typedef struct __rs690_vbios_regs__ /* Initialization VBIOS function */ extern void vgabios_init(rs690_vbios_regs *vbios_regs); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H */ diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h index a92a6cb..93945a5 100644 --- a/src/mainboard/thomson/ip1000/spd_table.h +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_THOMSON_IP1000_SPD_TABLE_H +#define MAINBOARD_THOMSON_IP1000_SPD_TABLE_H + #include <spd.h> #if CONFIG_ONBOARD_MEMORY_64MB @@ -48,3 +51,5 @@ const struct spd_entry spd_table [] = { {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, DENSITY}, /* Density of each row on module */ }; + +#endif /* MAINBOARD_THOMSON_IP1000_SPD_TABLE_H */

1 0

Patch set updated for coreboot: 0b0bf29 mainboards: Add missing header guards
by HAOUAS Elyes 04 Aug '14

04 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6489 -gerrit commit 0b0bf29908bd8586e84b5f3dbc7b3eeb03128f8b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Aug 4 09:19:27 2014 +0200 mainboards: Add missing header guards Change-Id: If93f5663fce9cc9b1675badcbf9f88525d875e76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/torpedo/Oem.h | 6 ++++++ src/mainboard/artecgroup/dbe61/spd_table.h | 5 +++++ src/mainboard/asus/m2n-e/hda_verb.h | 5 +++++ src/mainboard/dmp/vortex86ex/hda_verb.h | 5 +++++ src/mainboard/getac/p470/hda_verb.h | 5 +++++ src/mainboard/google/bolt/hda_verb.h | 5 +++++ src/mainboard/google/butterfly/hda_verb.h | 4 ++++ src/mainboard/google/falco/hda_verb.h | 5 +++++ src/mainboard/google/link/hda_verb.h | 5 +++++ src/mainboard/google/link/i915io.h | 5 +++++ src/mainboard/google/parrot/hda_verb.h | 5 +++++ src/mainboard/google/peppy/hda_verb.h | 5 +++++ src/mainboard/google/slippy/hda_verb.h | 5 +++++ src/mainboard/google/stout/hda_verb.h | 5 +++++ src/mainboard/intel/baskingridge/hda_verb.h | 5 +++++ src/mainboard/intel/cougar_canyon2/hda_verb.h | 5 +++++ src/mainboard/intel/eagleheights/ioapic.h | 5 +++++ src/mainboard/intel/emeraldlake2/hda_verb.h | 5 +++++ src/mainboard/intel/wtm2/hda_verb.h | 5 +++++ src/mainboard/intel/xe7501devkit/ioapic.h | 5 +++++ src/mainboard/iwave/iWRainbowG6/hda_verb.h | 5 +++++ src/mainboard/kontron/ktqm77/hda_verb.h | 6 ++++++ src/mainboard/lenovo/t520/hda_verb.h | 4 ++++ src/mainboard/lenovo/t530/hda_verb.h | 4 ++++ src/mainboard/lenovo/x201/hda_verb.h | 5 +++++ src/mainboard/lenovo/x230/hda_verb.h | 4 ++++ src/mainboard/nvidia/l1_2pvv/hda_verb.h | 5 +++++ src/mainboard/packardbell/ms2290/hda_verb.h | 5 +++++ src/mainboard/rca/rm4100/spd_table.h | 5 +++++ src/mainboard/roda/rk9/hda_verb.h | 5 +++++ src/mainboard/samsung/lumpy/hda_verb.h | 5 +++++ src/mainboard/samsung/stumpy/hda_verb.h | 5 +++++ src/mainboard/technexion/tim5690/speaker.h | 5 +++++ src/mainboard/technexion/tim5690/tn_post_code.h | 6 +++++- src/mainboard/technexion/tim5690/vgabios.h | 5 +++++ src/mainboard/thomson/ip1000/spd_table.h | 5 +++++ 36 files changed, 178 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 915182e..0be9abe 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,6 +16,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +#ifndef MAINBOARD_AMD_TORPEDO_OEM_H +#define MAINBOARD_AMD_TORPEDO_OEM_H + #ifndef BIOS_SIZE #define BIOS_SIZE 0x04 //04 - 1MB #endif @@ -221,3 +225,5 @@ * */ #define PCIB_SSID 0x780F1022 + +#endif /* MAINBOARD_AMD_TORPEDO_OEM_H */ diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 3d45b6f..a24f5e7 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H +#define MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H + #include <spd.h> struct spd_entry { @@ -51,3 +54,5 @@ const struct spd_entry spd_table [] = {SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ {SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ }; + +#endif /* MAINBOARD_ARTECGROUP_DBE61_SPD_TABLE_H */ diff --git a/src/mainboard/asus/m2n-e/hda_verb.h b/src/mainboard/asus/m2n-e/hda_verb.h index ec288ba..1ae213c 100644 --- a/src/mainboard/asus/m2n-e/hda_verb.h +++ b/src/mainboard/asus/m2n-e/hda_verb.h @@ -24,6 +24,9 @@ * http://www.analog.com/static/imported-files/data_sheets/AD1988A_1988B.pdf */ +#ifndef MAINBOARD_ASUS_M2N_E_HDA_VERB_H +#define MAINBOARD_ASUS_M2N_E_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x11d4198b, /* Codec Vendor / Device ID: Analog Devices AD1988B */ @@ -120,3 +123,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_ASUS_M2N_E_HDA_VERB_H */ diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h index 0556315..67b1e12 100644 --- a/src/mainboard/dmp/vortex86ex/hda_verb.h +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H +#define MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 @@ -105,3 +108,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_DMP_VORTEX86EX_HDA_VERB_H */ diff --git a/src/mainboard/getac/p470/hda_verb.h b/src/mainboard/getac/p470/hda_verb.h index b7578cc..52d16ba 100644 --- a/src/mainboard/getac/p470/hda_verb.h +++ b/src/mainboard/getac/p470/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GETAC_P470_HDA_VERB_H +#define MAINBOARD_GETAC_P470_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 @@ -106,3 +109,5 @@ static const u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_GETAC_P470_HDA_VERB_H */ diff --git a/src/mainboard/google/bolt/hda_verb.h b/src/mainboard/google/bolt/hda_verb.h index f27480d..653c777 100644 --- a/src/mainboard/google/bolt/hda_verb.h +++ b/src/mainboard/google/bolt/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_BOLT_HDA_VERB_H +#define MAINBOARD_GOOGLE_BOLT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_BOLT_HDA_VERB_H */ diff --git a/src/mainboard/google/butterfly/hda_verb.h b/src/mainboard/google/butterfly/hda_verb.h index 89a81fe..759153b 100644 --- a/src/mainboard/google/butterfly/hda_verb.h +++ b/src/mainboard/google/butterfly/hda_verb.h @@ -23,6 +23,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H +#define MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -262,3 +264,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_BUTTERFLY_HDA_VERB_H */ diff --git a/src/mainboard/google/falco/hda_verb.h b/src/mainboard/google/falco/hda_verb.h index f27480d..d1039ec 100644 --- a/src/mainboard/google/falco/hda_verb.h +++ b/src/mainboard/google/falco/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_FALCO_HDA_VERB_H +#define MAINBOARD_GOOGLE_FALCO_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_FALCO_HDA_VERB_H */ diff --git a/src/mainboard/google/link/hda_verb.h b/src/mainboard/google/link/hda_verb.h index ed18d63..4a6ba76 100644 --- a/src/mainboard/google/link/hda_verb.h +++ b/src/mainboard/google/link/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_LINK_HDA_VERB_H +#define MAINBOARD_GOOGLE_LINK_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x11020011, // Codec Vendor / Device ID: Creative CA0132 @@ -179,3 +182,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_LINK_HDA_VERB_H */ diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h index 6533c81..533bf14 100644 --- a/src/mainboard/google/link/i915io.h +++ b/src/mainboard/google/link/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_LINK_I915IO_H +#define MAINBOARD_GOOGLE_LINK_I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* MAINBOARD_GOOGLE_LINK_I915IO_H */ diff --git a/src/mainboard/google/parrot/hda_verb.h b/src/mainboard/google/parrot/hda_verb.h index ca68ad3..0bbb01d 100644 --- a/src/mainboard/google/parrot/hda_verb.h +++ b/src/mainboard/google/parrot/hda_verb.h @@ -32,6 +32,9 @@ * HDMI PatherPoint */ +#ifndef MAINBOARD_GOOGLE_PARROT_HDA_VERB_H +#define MAINBOARD_GOOGLE_PARROT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 @@ -167,3 +170,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_PARROT_HDA_VERB_H */ diff --git a/src/mainboard/google/peppy/hda_verb.h b/src/mainboard/google/peppy/hda_verb.h index d3a63bf..adadf88 100644 --- a/src/mainboard/google/peppy/hda_verb.h +++ b/src/mainboard/google/peppy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H +#define MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -97,3 +100,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_PEPPY_HDA_VERB_H */ diff --git a/src/mainboard/google/slippy/hda_verb.h b/src/mainboard/google/slippy/hda_verb.h index f27480d..c6351e1 100644 --- a/src/mainboard/google/slippy/hda_verb.h +++ b/src/mainboard/google/slippy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H +#define MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -92,3 +95,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x02171f03, // connector, left panel }; + +#endif /* MAINBOARD_GOOGLE_SLIPPY_HDA_VERB_H */ diff --git a/src/mainboard/google/stout/hda_verb.h b/src/mainboard/google/stout/hda_verb.h index 08fc10c..2bd99c0 100644 --- a/src/mainboard/google/stout/hda_verb.h +++ b/src/mainboard/google/stout/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_GOOGLE_STOUT_HDA_VERB_H +#define MAINBOARD_GOOGLE_STOUT_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek @@ -137,3 +140,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_GOOGLE_STOUT_HDA_VERB_H */ diff --git a/src/mainboard/intel/baskingridge/hda_verb.h b/src/mainboard/intel/baskingridge/hda_verb.h index 52e5a3d..86a7434 100644 --- a/src/mainboard/intel/baskingridge/hda_verb.h +++ b/src/mainboard/intel/baskingridge/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H +#define MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_BASKINGRIDGE_HDA_VERB_H */ diff --git a/src/mainboard/intel/cougar_canyon2/hda_verb.h b/src/mainboard/intel/cougar_canyon2/hda_verb.h index f8e83b4..f844e60 100644 --- a/src/mainboard/intel/cougar_canyon2/hda_verb.h +++ b/src/mainboard/intel/cougar_canyon2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H +#define MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI @@ -47,3 +50,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_COUGAR_CANYON2_HDA_VERB_H */ diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h index 4ac7d62..c0d173d 100644 --- a/src/mainboard/intel/eagleheights/ioapic.h +++ b/src/mainboard/intel/eagleheights/ioapic.h @@ -1,2 +1,7 @@ +#ifndef MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H +#define MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H + #define IOAPIC_I3100 2 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 + +#endif /* MAINBOARD_INTEL_EAGLEHEIGHTS_IOAPIC_H */ diff --git a/src/mainboard/intel/emeraldlake2/hda_verb.h b/src/mainboard/intel/emeraldlake2/hda_verb.h index 52e5a3d..41c03c5 100644 --- a/src/mainboard/intel/emeraldlake2/hda_verb.h +++ b/src/mainboard/intel/emeraldlake2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H +#define MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_EMERALDLAKE2_HDA_VERB_H */ diff --git a/src/mainboard/intel/wtm2/hda_verb.h b/src/mainboard/intel/wtm2/hda_verb.h index cb33add..0505e92 100644 --- a/src/mainboard/intel/wtm2/hda_verb.h +++ b/src/mainboard/intel/wtm2/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_INTEL_WTM2_HDA_VERB_H +#define MAINBOARD_INTEL_WTM2_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -96,3 +99,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_INTEL_WTM2_HDA_VERB_H */ diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 9ac2aee..9cdd4a7 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,3 +1,6 @@ +#ifndef MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H +#define MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H + // IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. @@ -9,3 +12,5 @@ #define P64H2_IOAPIC_VERSION 0x20 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2 + +#endif /* MAINBOARD_INTEL_XE7501DEVKIT_IOAPIC_H */ diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.h b/src/mainboard/iwave/iWRainbowG6/hda_verb.h index 80ed21d..c1c4f4a 100644 --- a/src/mainboard/iwave/iWRainbowG6/hda_verb.h +++ b/src/mainboard/iwave/iWRainbowG6/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H +#define MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H + static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x111d76d5, // Codec Vendor / Device ID: IDT 92HD81 @@ -92,3 +95,5 @@ static u32 mainboard_cim_verb_data[] = { extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_IWAVE_IWRAINBOWG6_HDA_VERB_H */ diff --git a/src/mainboard/kontron/ktqm77/hda_verb.h b/src/mainboard/kontron/ktqm77/hda_verb.h index 53b3fc9..fde7f6c 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.h +++ b/src/mainboard/kontron/ktqm77/hda_verb.h @@ -24,6 +24,10 @@ * Port-Con. Location Def.-Dev. Con.-Type Color Misc Def.-Aso. Seq * 31..30 29..24 23..20 19..16 15..12 11..00 07..04 03..00 */ + +#ifndef MAINBOARD_KONTRON_KTQM77_HDA_VERB_H +#define MAINBOARD_KONTRON_KTQM77_HDA_VERB_H + #define PIN_CFG(pin, val) \ (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ @@ -140,3 +144,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771e56, 0x30771f18 }; + +#endif /* MAINBOARD_KONTRON_KTQM77_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/t520/hda_verb.h b/src/mainboard/lenovo/t520/hda_verb.h index 7d5e75a..a841423 100644 --- a/src/mainboard/lenovo/t520/hda_verb.h +++ b/src/mainboard/lenovo/t520/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_T520_HDA_VERB_H +#define MAINBOARD_LENOVO_T520_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_T520_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/t530/hda_verb.h b/src/mainboard/lenovo/t530/hda_verb.h index cc280a1..6ebf2a0 100644 --- a/src/mainboard/lenovo/t530/hda_verb.h +++ b/src/mainboard/lenovo/t530/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_T530_HDA_VERB_H +#define MAINBOARD_LENOVO_T530_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_T530_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/x201/hda_verb.h b/src/mainboard/lenovo/x201/hda_verb.h index d5a8e7c..db10142 100644 --- a/src/mainboard/lenovo/x201/hda_verb.h +++ b/src/mainboard/lenovo/x201/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_LENOVO_X201_HDA_VERB_H +#define MAINBOARD_LENOVO_X201_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ @@ -118,3 +121,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30671E56, 0x30671F58, }; + +#endif /* MAINBOARD_LENOVO_X201_HDA_VERB_H */ diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h index cc280a1..fdb0924 100644 --- a/src/mainboard/lenovo/x230/hda_verb.h +++ b/src/mainboard/lenovo/x230/hda_verb.h @@ -24,6 +24,8 @@ * Revision ID : 0x100303 */ +#ifndef MAINBOARD_LENOVO_X230_HDA_VERB_H +#define MAINBOARD_LENOVO_X230_HDA_VERB_H static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ @@ -313,3 +315,5 @@ static const u32 mainboard_pc_beep_verbs[] = { static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_LENOVO_X230_HDA_VERB_H */ diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.h b/src/mainboard/nvidia/l1_2pvv/hda_verb.h index 763840b..398dc97 100644 --- a/src/mainboard/nvidia/l1_2pvv/hda_verb.h +++ b/src/mainboard/nvidia/l1_2pvv/hda_verb.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H +#define MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H + static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 @@ -106,3 +109,5 @@ static u32 mainboard_cim_verb_data[] = { extern u32 *cim_verb_data; extern u32 cim_verb_data_size; + +#endif /* MAINBOARD_NVIDIA_L1_2PVV_HDA_VERB_H */ diff --git a/src/mainboard/packardbell/ms2290/hda_verb.h b/src/mainboard/packardbell/ms2290/hda_verb.h index 1e3ccc4..7cc4ddf 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.h +++ b/src/mainboard/packardbell/ms2290/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H +#define MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ @@ -88,3 +91,5 @@ static const u32 mainboard_cim_verb_data[] = { 0x30671E56, 0x30671F58, }; + +#endif /* MAINBOARD_PACKARDBELL_MS2290_HDA_VERB_H */ diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h index 050bf72..79f5b1c 100644 --- a/src/mainboard/rca/rm4100/spd_table.h +++ b/src/mainboard/rca/rm4100/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_RCA_RM4100_SPD_TABLE_H +#define MAINBOARD_RCA_RM4100_SPD_TABLE_H + #include <spd.h> struct spd_entry { @@ -38,3 +41,5 @@ const struct spd_entry spd_table [] = { {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ }; + +#endif /* MAINBOARD_RCA_RM4100_SPD_TABLE_H */ diff --git a/src/mainboard/roda/rk9/hda_verb.h b/src/mainboard/roda/rk9/hda_verb.h index f99d097..598e141 100644 --- a/src/mainboard/roda/rk9/hda_verb.h +++ b/src/mainboard/roda/rk9/hda_verb.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_RODA_RK9_HDA_VERB_H +#define MAINBOARD_RODA_RK9_HDA_VERB_H + #define PIN_CFG(pin, val) \ (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ @@ -72,3 +75,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; extern const u32 * pc_beep_verbs; extern u32 pc_beep_verbs_size; + +#endif /* MAINBOARD_RODA_RK9_HDA_VERB_H */ diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h index dfadf55..03f8c0a 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.h +++ b/src/mainboard/samsung/lumpy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H +#define MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Realtek ALC262 @@ -79,3 +82,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_SAMSUNG_LUMPY_HDA_VERB_H */ diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h index b263fbe..851516f 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.h +++ b/src/mainboard/samsung/stumpy/hda_verb.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H +#define MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 @@ -106,3 +109,5 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* MAINBOARD_SAMSUNG_STUMPY_HDA_VERB_H */ diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h index e4a5fd0..6bee5f5 100644 --- a/src/mainboard/technexion/tim5690/speaker.h +++ b/src/mainboard/technexion/tim5690/speaker.h @@ -18,8 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H +#define MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H + void speaker_init(uint8_t time); void speaker_on_nodelay(void); void speaker_off_nodelay(void); void speaker_on_delay(void); void speaker_off_delay(void); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_SPEAKER_H */ diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h index 46d7382..a6ae304 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ b/src/mainboard/technexion/tim5690/tn_post_code.h @@ -18,11 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H +#define MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H + #define LED_MESSAGE_START 0xFF #define LED_MESSAGE_FINISH 0x99 #define LED_MESSAGE_RAM 0x01 - #ifdef __PRE_RAM__ // TechNexion's Post Code Initially. @@ -31,3 +33,5 @@ void technexion_post_code_init(void); #endif void technexion_post_code(uint8_t udata8); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_TN_POST_CODE_H */ diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h index a353011..55b5b46 100644 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ b/src/mainboard/technexion/tim5690/vgabios.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H +#define MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H + /* AMD Chipset */ #define AMD_RS690_INT15 0x4E08 @@ -35,3 +38,5 @@ typedef struct __rs690_vbios_regs__ /* Initialization VBIOS function */ extern void vgabios_init(rs690_vbios_regs *vbios_regs); + +#endif /* MAINBOARD_TECHNEXION_TIM5690_VGABIOS_H */ diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h index a92a6cb..93945a5 100644 --- a/src/mainboard/thomson/ip1000/spd_table.h +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MAINBOARD_THOMSON_IP1000_SPD_TABLE_H +#define MAINBOARD_THOMSON_IP1000_SPD_TABLE_H + #include <spd.h> #if CONFIG_ONBOARD_MEMORY_64MB @@ -48,3 +51,5 @@ const struct spd_entry spd_table [] = { {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, DENSITY}, /* Density of each row on module */ }; + +#endif /* MAINBOARD_THOMSON_IP1000_SPD_TABLE_H */

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coreboot-gerrit August 2014