coreboot-gerrit August 2014

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Patch set updated for coreboot: 2e7ff2b util/sconfig/main.c: Free memory pointed to by `devtree`
by Paul Menzel 05 Aug '14

05 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6486 -gerrit commit 2e7ff2b28a4a1615280b8a769c8707b2caf7b1a9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Aug 4 08:15:03 2014 +0200 util/sconfig/main.c: Free memory pointed to by `devtree` Cppcheck 1.65 reports the error below. [main.c:709]: (error) Memory leak: devtree So free the memory space pointed to by `devtree` to fix the memory leak. Change-Id: Ibcd93057e88544ea900d9b6261c907baa751b2f1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/sconfig/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 44d4911..91fb8cb 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -609,6 +609,7 @@ int main(int argc, char** argv) { perror(NULL); exit(1); } + free(devtree); yyrestart(filec);

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Patch set updated for coreboot: a140dc2 superio: Nuvoton NCT5577D initial support
by David Hendricks 05 Aug '14

05 Aug '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6497 -gerrit commit a140dc278ea9b74852983fa5a11d7c9d25b9b84e Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 4 18:01:00 2014 -0700 superio: Nuvoton NCT5577D initial support This adds basic support for the Nuvoton NCTT5577D SuperIO chip which is similar to the NCT5104D but with a few different logical devices and only one UART. Change-Id: I1cfc2cb3a4a029d2388308af4b0fbf268889bf09 Signed-off-by: David Hendrickss <dhendrix(a)chromium.org> --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct5577d/Makefile.inc | 22 ++++++ src/superio/nuvoton/nct5577d/chip.h | 29 ++++++++ src/superio/nuvoton/nct5577d/early_init.c | 64 ++++++++++++++++++ src/superio/nuvoton/nct5577d/nct5577d.h | 53 +++++++++++++++ src/superio/nuvoton/nct5577d/superio.c | 109 ++++++++++++++++++++++++++++++ 7 files changed, 282 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 350c8dd..2625274 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -28,3 +28,7 @@ config SUPERIO_NUVOTON_WPCM450 config SUPERIO_NUVOTON_NCT5104D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT5577D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 1ce6963..bd5b96f 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -22,3 +22,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += nct5577d diff --git a/src/superio/nuvoton/nct5577d/Makefile.inc b/src/superio/nuvoton/nct5577d/Makefile.inc new file mode 100644 index 0000000..6119ad0 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += superio.c +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += early_init.c diff --git a/src/superio/nuvoton/nct5577d/chip.h b/src/superio/nuvoton/nct5577d/chip.h new file mode 100644 index 0000000..ef0f0ca --- /dev/null +++ b/src/superio/nuvoton/nct5577d/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT5577D_CHIP_H +#define SUPERIO_NUVOTON_NCT5577D_CHIP_H + +struct superio_nuvoton_nct5577d_config { + u8 irq_trigger_type; +}; + +#endif diff --git a/src/superio/nuvoton/nct5577d/early_init.c b/src/superio/nuvoton/nct5577d/early_init.c new file mode 100644 index 0000000..92922d8 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "nct5577d.h" + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +/* NCT5577D has only UART A */ +void nct5577d_enable_uarta(device_t dev) +{ + u8 tmp; + u16 port = dev >> 8; + + pnp_enter_conf_state(dev); + pnp_set_enable(dev, 0); + + /* Select COM A function for Pins 13-20 */ + tmp = pnp_read_config(dev, GLOBAL_OPTION_CR28); + tmp &= ~CR28_PIN13_20_CFG; + pnp_write_config(dev, GLOBAL_OPTION_CR28, tmp); + + pnp_set_logical_device(NCT5577D_SP1); + /* default iobase is 0x03f8 */ + //pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/nuvoton/nct5577d/nct5577d.h b/src/superio/nuvoton/nct5577d/nct5577d.h new file mode 100644 index 0000000..84c3b1e --- /dev/null +++ b/src/superio/nuvoton/nct5577d/nct5577d.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT5577D_H +#define SUPERIO_NUVOTON_NCT5577D_H + +/* SIO global configuration */ +#define IRQ_TYPE_SEL_CR10 0x10 /* UARTA, KBC, Mouse, CIR */ +#define IRQ_TYPE_SEL_CR11 0x11 /* HM, WDTO, SMI */ + +#define GLOBAL_OPTION_CR26 0x26 +#define CR26_LOCK_REG (1 << 4) /* enable access CR10/CR11 */ +#define CR26_UARTA_LEGACY_IRQ (1 << 1) /* toggle UARTA legacy IRQ */ + +#define GLOBAL_OPTION_CR28 0x28 +#define CR28_PIN13_20_CFG (1 << 7) /* 0=COM A, 1=GPIO8 (default) */ + +/* Logical Device Numbers (LDN). */ +#define NCT5577D_SP1 0x02 /* UARTA */ +#define NCT5577D_IR 0x03 /* IR */ +#define NCT5577D_KBC 0x05 /* Keyboard Controller */ +#define NCT5577D_CIR 0x06 /* CIR */ +#define NCT5577D_GPIO7_8_9 0x07 /* GPIO7, 8, and 9 control */ +#define NCT5577D_WDT1_GPIOA 0x08 /* WDT1 and GPIOA control */ +#define NCT5577D_GPIO2_3_4_5_7 0x09 /* GPIO2, 3, 4, 5, and 7 control */ +#define NCT5577D_ACPI 0x0a /* ACPI */ +#define NCT5577D_HWM_FPLED 0x0b /* Hardware monitor, Front Panel LED */ +#define NCT5577D_CIR_WAKEUP 0x0e /* CIR wake-up */ +#define NCT5577D_GPIO_PP_OD 0x0f /* GPIO Push-Pull or Open-Drain */ +#define NCT5577D_DEEP_SLEEP 0x16 /* Deep sleep */ +#define NCT5577D_GPIOA 0x17 /* GPIOA config */ + +void nct5577d_enable_uart(device_t dev); + +#endif /* SUPERIO_NUVOTON_NCT5577D_H */ diff --git a/src/superio/nuvoton/nct5577d/superio.c b/src/superio/nuvoton/nct5577d/superio.c new file mode 100644 index 0000000..1c203a5 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/superio.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct5577d.h" +#include "chip.h" + +static void doit(device_t dev, u8 reg, u8 bit) +{ + struct superio_nuvoton_nct5577d_config *conf = dev->chip_info; + u8 val; + + val = pnp_read_config(dev, reg); + /* 0 for edge-triggered, 1 for level-triggered */ + if (conf->irq_trigger_type) + val |= (1 << bit); + else + val &= ~(1 << bit); + pnp_write_config(dev, reg, val); +} + +static void nct5577d_init(device_t dev) +{ + u8 reg26; + + if (!dev->enabled) + return; + + pnp_enter_conf_mode(dev); + + /* CR26 bit 4 must be set before accessing CR10, CR11, CR13, or CR14 */ + reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); + reg26 |= CR26_LOCK_REG; + pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); + + switch(dev->path.pnp.device) { + /* SP1 (UARTA) IRQ type selection */ + case NCT5577D_SP1: + doit(IRQ_TYPE_SEL_CR10, 5); + break; + case NCT5577D_KBC: + doit(IRQ_TYPE_SEL_CR10, 3); + break; + case NCT5577D_CIR: + doit(IRQ_TYPE_SEL_CR10, 1); + break; + case NCT5577D_HWM_FPLED: + doit(IRQ_TYPE_SEL_CR11, 7); + break; + case NCT5577D_CIR_WAKEUP: + doit(IRQ_TYPE_SEL_CR10, 0); + break; + default: + break; + } + + /* Clear access control register */ + reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); + reg26 &= ~CR26_LOCK_REG; + pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); + pnp_exit_conf_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5577d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT5577D_SP1 }, + { &ops, NCT5577D_KBC }, + { &ops, NCT5577D_ACPI }, + { &ops, NCT5577D_HWM_FPLED }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5577d_ops = { + CHIP_NAME("NUVOTON NCT5577D Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: 943f66a superio: Nuvoton NCT5577D initial support
by David Hendricks 05 Aug '14

05 Aug '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6497 -gerrit commit 943f66a32a3161c8e2190898e62804cbac7e0616 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 4 18:01:00 2014 -0700 superio: Nuvoton NCT5577D initial support This adds basic support for the Nuvoton NCTT5577D SuperIO chip which is similar to the NCT5104D but with a few different logical devices and only one UART. Change-Id: I1cfc2cb3a4a029d2388308af4b0fbf268889bf09 Signed-off-by: David Hendrickss <dhendrix(a)chromium.org> --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct5577d/Makefile.inc | 22 ++++++ src/superio/nuvoton/nct5577d/chip.h | 29 ++++++++ src/superio/nuvoton/nct5577d/early_init.c | 64 ++++++++++++++++++ src/superio/nuvoton/nct5577d/nct5104d.h | 53 +++++++++++++++ src/superio/nuvoton/nct5577d/nct5577d.h | 53 +++++++++++++++ src/superio/nuvoton/nct5577d/superio.c | 109 ++++++++++++++++++++++++++++++ 8 files changed, 335 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 350c8dd..2625274 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -28,3 +28,7 @@ config SUPERIO_NUVOTON_WPCM450 config SUPERIO_NUVOTON_NCT5104D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT5577D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 1ce6963..bd5b96f 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -22,3 +22,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += nct5577d diff --git a/src/superio/nuvoton/nct5577d/Makefile.inc b/src/superio/nuvoton/nct5577d/Makefile.inc new file mode 100644 index 0000000..6119ad0 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += superio.c +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5577D) += early_init.c diff --git a/src/superio/nuvoton/nct5577d/chip.h b/src/superio/nuvoton/nct5577d/chip.h new file mode 100644 index 0000000..ef0f0ca --- /dev/null +++ b/src/superio/nuvoton/nct5577d/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT5577D_CHIP_H +#define SUPERIO_NUVOTON_NCT5577D_CHIP_H + +struct superio_nuvoton_nct5577d_config { + u8 irq_trigger_type; +}; + +#endif diff --git a/src/superio/nuvoton/nct5577d/early_init.c b/src/superio/nuvoton/nct5577d/early_init.c new file mode 100644 index 0000000..92922d8 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "nct5577d.h" + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +/* NCT5577D has only UART A */ +void nct5577d_enable_uarta(device_t dev) +{ + u8 tmp; + u16 port = dev >> 8; + + pnp_enter_conf_state(dev); + pnp_set_enable(dev, 0); + + /* Select COM A function for Pins 13-20 */ + tmp = pnp_read_config(dev, GLOBAL_OPTION_CR28); + tmp &= ~CR28_PIN13_20_CFG; + pnp_write_config(dev, GLOBAL_OPTION_CR28, tmp); + + pnp_set_logical_device(NCT5577D_SP1); + /* default iobase is 0x03f8 */ + //pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/nuvoton/nct5577d/nct5104d.h b/src/superio/nuvoton/nct5577d/nct5104d.h new file mode 100644 index 0000000..2a74b7d --- /dev/null +++ b/src/superio/nuvoton/nct5577d/nct5104d.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT5577D_H +#define SUPERIO_NUVOTON_NCT5577D_H + +/* SIO global configuration */ +#define IRQ_TYPE_SEL_CR10 0x10 /* UARTA,UARTB */ +#define IRQ_TYPE_SEL_CR11 0x11 /* SMI,UARTC,UARTD,WDTO */ +#define GLOBAL_OPTION_CR26 0x26 +#define CR26_LOCK_REG (1 << 4) /* required to access CR10/CR11 */ + +/* Logical Device Numbers (LDN). */ +#define NCT5577D_FDC 0x00 /* FDC - not pinned out */ +#define NCT5577D_SP1 0x02 /* UARTA */ +#define NCT5577D_SP2 0x03 /* UARTB */ +#define NCT5577D_GPIO_WDT 0x08 /* GPIO WDT Interface */ +#define NCT5577D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ +#define NCT5577D_SP3 0x10 /* UARTC */ +#define NCT5577D_SP4 0x11 /* UARTD */ +#define NCT5577D_PORT80 0x14 /* PORT 80 */ + +/* Virtual Logical Device Numbers (LDN) */ +#define NCT5577D_GPIO_V 0x07 /* GPIO - 0,1,6 Interface */ + +/* Virtual devices sharing the enables are encoded as follows: + VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN +*/ +#define NCT5577D_GPIO0 ((0 << 8) | NCT5577D_GPIO_V) +#define NCT5577D_GPIO1 ((1 << 8) | NCT5577D_GPIO_V) +#define NCT5577D_GPIO6 ((6 << 8) | NCT5577D_GPIO_V) + +void NCT5577d_enable_uartd(device_t dev); + +#endif /* SUPERIO_NUVOTON_NCT5577D_H */ diff --git a/src/superio/nuvoton/nct5577d/nct5577d.h b/src/superio/nuvoton/nct5577d/nct5577d.h new file mode 100644 index 0000000..84c3b1e --- /dev/null +++ b/src/superio/nuvoton/nct5577d/nct5577d.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT5577D_H +#define SUPERIO_NUVOTON_NCT5577D_H + +/* SIO global configuration */ +#define IRQ_TYPE_SEL_CR10 0x10 /* UARTA, KBC, Mouse, CIR */ +#define IRQ_TYPE_SEL_CR11 0x11 /* HM, WDTO, SMI */ + +#define GLOBAL_OPTION_CR26 0x26 +#define CR26_LOCK_REG (1 << 4) /* enable access CR10/CR11 */ +#define CR26_UARTA_LEGACY_IRQ (1 << 1) /* toggle UARTA legacy IRQ */ + +#define GLOBAL_OPTION_CR28 0x28 +#define CR28_PIN13_20_CFG (1 << 7) /* 0=COM A, 1=GPIO8 (default) */ + +/* Logical Device Numbers (LDN). */ +#define NCT5577D_SP1 0x02 /* UARTA */ +#define NCT5577D_IR 0x03 /* IR */ +#define NCT5577D_KBC 0x05 /* Keyboard Controller */ +#define NCT5577D_CIR 0x06 /* CIR */ +#define NCT5577D_GPIO7_8_9 0x07 /* GPIO7, 8, and 9 control */ +#define NCT5577D_WDT1_GPIOA 0x08 /* WDT1 and GPIOA control */ +#define NCT5577D_GPIO2_3_4_5_7 0x09 /* GPIO2, 3, 4, 5, and 7 control */ +#define NCT5577D_ACPI 0x0a /* ACPI */ +#define NCT5577D_HWM_FPLED 0x0b /* Hardware monitor, Front Panel LED */ +#define NCT5577D_CIR_WAKEUP 0x0e /* CIR wake-up */ +#define NCT5577D_GPIO_PP_OD 0x0f /* GPIO Push-Pull or Open-Drain */ +#define NCT5577D_DEEP_SLEEP 0x16 /* Deep sleep */ +#define NCT5577D_GPIOA 0x17 /* GPIOA config */ + +void nct5577d_enable_uart(device_t dev); + +#endif /* SUPERIO_NUVOTON_NCT5577D_H */ diff --git a/src/superio/nuvoton/nct5577d/superio.c b/src/superio/nuvoton/nct5577d/superio.c new file mode 100644 index 0000000..1c203a5 --- /dev/null +++ b/src/superio/nuvoton/nct5577d/superio.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct5577d.h" +#include "chip.h" + +static void doit(device_t dev, u8 reg, u8 bit) +{ + struct superio_nuvoton_nct5577d_config *conf = dev->chip_info; + u8 val; + + val = pnp_read_config(dev, reg); + /* 0 for edge-triggered, 1 for level-triggered */ + if (conf->irq_trigger_type) + val |= (1 << bit); + else + val &= ~(1 << bit); + pnp_write_config(dev, reg, val); +} + +static void nct5577d_init(device_t dev) +{ + u8 reg26; + + if (!dev->enabled) + return; + + pnp_enter_conf_mode(dev); + + /* CR26 bit 4 must be set before accessing CR10, CR11, CR13, or CR14 */ + reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); + reg26 |= CR26_LOCK_REG; + pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); + + switch(dev->path.pnp.device) { + /* SP1 (UARTA) IRQ type selection */ + case NCT5577D_SP1: + doit(IRQ_TYPE_SEL_CR10, 5); + break; + case NCT5577D_KBC: + doit(IRQ_TYPE_SEL_CR10, 3); + break; + case NCT5577D_CIR: + doit(IRQ_TYPE_SEL_CR10, 1); + break; + case NCT5577D_HWM_FPLED: + doit(IRQ_TYPE_SEL_CR11, 7); + break; + case NCT5577D_CIR_WAKEUP: + doit(IRQ_TYPE_SEL_CR10, 0); + break; + default: + break; + } + + /* Clear access control register */ + reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); + reg26 &= ~CR26_LOCK_REG; + pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); + pnp_exit_conf_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5577d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT5577D_SP1 }, + { &ops, NCT5577D_KBC }, + { &ops, NCT5577D_ACPI }, + { &ops, NCT5577D_HWM_FPLED }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5577d_ops = { + CHIP_NAME("NUVOTON NCT5577D Super I/O") + .enable_dev = enable_dev, +};

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Patch merged into coreboot/master: 18fe07e northbridge/via/vx800: Fix out-of-bounds read due to off-by-one
by gerrit＠coreboot.org 05 Aug '14

05 Aug '14

the following patch was just integrated into master: commit 18fe07ed22e81c6315c199d5ae71b689163bac46 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Aug 4 09:58:30 2014 +1000 northbridge/via/vx800: Fix out-of-bounds read due to off-by-one Change-Id: Ia7fda59b60b2148dd4d246686bd94d2334b23eb5 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6485 for details. -gerrit

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New patch to review for coreboot: ccc16cf cbfstool error: -v gives THOUSANDS of lines of bad output.
by Martin Roth 05 Aug '14

05 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6496 -gerrit commit ccc16cfa1224d025d41a66978f30fc10781c8147 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Aug 4 17:23:06 2014 -0600 cbfstool error: -v gives THOUSANDS of lines of bad output. This is not intended for submission. I just ran cbfstool with the -v option, trying to debug an issue I was seeing, and suddenly I had TWO issues... There's a problem in cbfstool here, and I don't have time to debug it further than this right now. If anyone feels like looking at it, I offer this up to them. Here's part of the output: PAYLOAD build/coreboot.pre add-payload -f payloads/memtest86+/memtest.elf -n img/memtest -c LZMA -v img/memtest 0xe09700 payload 46951 0x41544144 ((unknown) compression, offset: 0x38, load: 0x10000, length: 46895/192808 0x52544e45 (none compression, offset: 0x0, load: 0x10000, length: 0/0 0x3000001 ((unknown) compression, offset: 0x0, load: 0x7e4081b787ec, length: 2020815957/363341946 0x314cc703 ((unknown) compression, offset: 0x42eeb380, load: 0x90b3ccab6100c86, length: 1916715941/-378419934 0xeb8788ab ((unknown) compression, offset: 0xf3b21c77, load: 0x62e8dea3da480ad0, length: -1342285081/-1389218217 0x246d75f4 ((unknown) compression, offset: 0xa881bd58, load: 0x6ee3e7be0c88cc21, length: -504708229/1612905668 ... (removed 400,000+ lines) 0x0 (none compression, offset: 0x0, load: 0x0, length: 0/0 0x0 (none compression, offset: 0x0, load: 0x0, length: 0/0 0x0 (none compression, offset: 0x0, load: 0x0, length: 0/0 0x0 (none compression, offset: 0x0, load: 0x0, length: 0/0 0x0 (none compression, offset: 0x0, load: 0x0, length: 0/0 make: *** [payloads/memtest86+/memtest.elf] Segmentation fault (core dumped) Change-Id: Ie2effd76894e824db4012baf9ac10dd79a79a113 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- util/cbfstool/cbfs_image.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 12bc2fe..234be5f 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -684,13 +684,13 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, case CBFS_COMPONENT_PAYLOAD: payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); - while (payload) { +// while (payload) { cbfs_print_payload_segment_info(payload, fp); - if (payload->type == PAYLOAD_SEGMENT_ENTRY) - break; - else - payload ++; - } +// if (payload->type == PAYLOAD_SEGMENT_ENTRY) +// break; +// else +// payload ++; +// } break; default: break;

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Patch merged into coreboot/master: 68a9716 lenovo/t520/mainboard.c: Include header `h8.h` for prototype
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 68a97164d3627bf277a7a5962e8006d163d40429 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 31 10:39:57 2014 +0200 lenovo/t520/mainboard.c: Include header `h8.h` for prototype Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: http://review.coreboot.org/6424 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6424 for details. -gerrit

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Patch merged into coreboot/master: 650b00c peppy: Force enable ASPM on PCIe Root Port 1
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 650b00c1bf9811f502a6da025a5c1d5f4b4b16b5 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Aug 21 11:47:11 2013 -0700 peppy: Force enable ASPM on PCIe Root Port 1 (Clone of Falco change Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8) Old-Change-Id: I5feba8fdbafba6d2de9f7d3de6170defc0d45a32 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66536 Reviewed-by: Dave Parker <dparker(a)chromium.org> (cherry picked from commit b78a872a6647d7bb82f6c06a75e4075e451a1622) peppy: Disable unused clocks CLKOUT for PCIE ports 2-5 and CLKOUT_XDP are not used and can be disabled. This change was modled after the change made in Falco: Falco-Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b The only difference per schematic for Peppy was PCIe 1 supports a NGFF interface. PCIe 0 is connected to WLAN. Old-Change-Id: Ib4871cb2655316cb260ab33ada6b9d81f271377f Signed-off-by: Steven Sherk <steven.sherk(a)se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66693 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 8f12335013a510dee3c21b55251ab00c0fbac609) Squashed two related commits. Change-Id: Ibc5b902018eec07fdccaa8c6cb066ce918f6a6b5 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6419 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6419 for details. -gerrit

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Patch set updated for coreboot: aca0130 lenovo/x201: Enable pcie lanes in wwan slot.
by Vladimir Serbinenko 04 Aug '14

04 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6482 -gerrit commit aca01303ee1b4daf3cf82f18c84e01394e1eece9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 14:55:14 2014 +0200 lenovo/x201: Enable pcie lanes in wwan slot. Change-Id: I7332eeed244877252074e661f1c256a69a9b428a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 3 ++- src/mainboard/lenovo/x201/romstage.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 1db5bf0..21e328a 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -135,8 +135,9 @@ chip northbridge/intel/nehalem end device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wwan) device pci 1c.3 on end # PCIe Port #4 (Expresscard) - device pci 1c.4 on end # PCIe Port #4 (wlan) + device pci 1c.4 on end # PCIe Port #5 (wlan) device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f129794..aa2c367 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -126,7 +126,7 @@ static void rcba_config(void) /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16e61fe1, 0xbf4f001f, + /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,

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Patch merged into coreboot/master: 6fa6843 sconfig: improve argument parsing
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 6fa6843a8d3ba9576a331c57818a5ecbe08a0f45 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 15:27:35 2014 +0200 sconfig: improve argument parsing Running sconfig with four arguments where the third does not match /-./ made sconfig use uninitialized memory to build the output filename. Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0 Found-By: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6483 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6483 for details. -gerrit

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Patch merged into coreboot/master: 80fd01d util/sconfig/main.c: Remove assigned but unused variable `link`
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 80fd01d2cc44a7a4077b5df25d5d09917e5ae04a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Aug 4 08:25:05 2014 +0200 util/sconfig/main.c: Remove assigned but unused variable `link` Cppcheck 1.65 report the style style issue below. [main.c:434]: (style) Variable 'link' is assigned a value that is never used. So remove the variable `link` as it is not needed. Change-Id: Ib77b80b74a70985a76eaa3247c4a43832ef23a59 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6488 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6488 for details. -gerrit

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coreboot-gerrit August 2014