Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6501
-gerrit
commit 19dd02bbdd176f0a9029a563fb369fde9d18ebaf
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Aug 16 15:57:56 2013 -0700
Set armv7 up for cpu_info to work as on x86 (so threads can work)
On x86, cpu_info lives at the top of stack. Make the arm do that as
well, as the threading model needs that and so will multicore support.
As part of this change, make the stack size a power of 2.
Also make it much smaller -- 2048 bytes is PLENTY for ram stage.
Note that the small stack size is counterintuitive for rom stage. How
can this work in rom stage, which needs a HUGE stack for lzma? The
main use of STACK_SIZE has always been in ram stage; since 2002 or so
it was to size per-core stacks (see, e.g.,
src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE
and, more recently, thread stacks. So, we define the STACK_TOP for rom
and ram stage, but the STACK_SIZE has no real effect on the ROM stage
(no hardware red zones on the stack) and hence we're ok with actually
defining the "wrong" stack size. In fact, the coreboot_ram ldscript
for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from
CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc
Observed stack usage in ramstage:
BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1
Jumping to boot code at 23104044
CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes
entry = 23104044
Which means we do need 2K, not 1K.
Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66135
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
Tested-by: Ronald G. Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/arch/armv7/Makefile.inc | 1 +
src/arch/armv7/bootblock.inc | 12 +++++++++--
src/arch/armv7/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++
src/arch/armv7/include/arch/cpu.h | 1 +
src/cpu/samsung/exynos5420/Kconfig | 22 ++++++++++++++++++--
5 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index a611b09..2188706 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -170,6 +170,7 @@ ramstage-y += exception_asm.S
ramstage-y += div0.c
#ramstage-y += interrupts.c
ramstage-y += cache.c
+ramstage-y += cpu.c
ramstage-y += mmu.c
ramstage-y += eabi_compat.c
ramstage-y += boot.c
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index b2c993a..c45259d 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -82,8 +82,15 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call board_init_f */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
+ /*
+ * The current design of cpu_info places the
+ * struct at the top of the stack. The number of
+ * words pushed must be at least as large as that
+ * struct.
+ */
+ push {r0-r2}
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
/*
* Use "bl" instead of "b" even though we do not intend to return.
* "bl" gets compiled to "blx" if we're transitioning from ARM to
@@ -104,5 +111,6 @@ wait_for_interrupt:
.Stack:
.word CONFIG_STACK_TOP
.align 2
+/* create this size the same way we do in coreboot_ram.ld: top-bottom */
.Stack_size:
- .word CONFIG_STACK_SIZE
+ .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
diff --git a/src/arch/armv7/cpu.c b/src/arch/armv7/cpu.c
new file mode 100644
index 0000000..f90c759
--- /dev/null
+++ b/src/arch/armv7/cpu.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include <stdlib.h>
+#include <arch/cpu.h>
+
+/* Return the cpu struct which is at the high memory address of the stack.
+ */
+struct cpu_info *cpu_info(void)
+{
+ uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),
+ CONFIG_STACK_SIZE);
+ addr -= sizeof(struct cpu_info);
+ return (void *)addr;
+}
+
diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h
index ec37a96..df44a92 100644
--- a/src/arch/armv7/include/arch/cpu.h
+++ b/src/arch/armv7/include/arch/cpu.h
@@ -104,4 +104,5 @@ inline static void set_svc32_mode(void)
asm volatile("msr cpsr_c, %0" :: "r"(0x13 | 0xc0));
}
+struct cpu_info *cpu_info(void);
#endif /* __ARCH_CPU_H__ */
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index d3eafcb..66679a0 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -69,7 +69,17 @@ config ROMSTAGE_SIZE
# at the top of IRAM for now.
#
# Stack grows downward, push operation stores register contents in
-# consecutive memory locations ending just below SP
+# consecutive memory locations ending just below SP.
+# The setup in the exynos 5420 is a new one for coreboot. We have got
+# the bootblock, romstage, and ramstage sharing the same stack space.
+# The SRAM is always there and having a known-good stack memory
+# makes for a more reliable setup.
+# Thus, in this case:
+# STACK_TOP: highest stack address in SRAM
+# STACK_BOTTOM: lowest stack address in SRAM
+# STACK_SIZE: as in standard coreboot usage, size of thread stacks in ramstage
+# ROMSTAGE_STACK_SIZE: size of the single stack in romstage
+
config STACK_TOP
hex
default 0x02073000
@@ -78,10 +88,18 @@ config STACK_BOTTOM
hex
default 0x0206f000
-config STACK_SIZE
+# The romstage stack must be large enough to contain the lzma buffer
+config ROMSTAGE_STACK_SIZE
hex
default 0x4000
+# STACK_SIZE is for the ramstage core and thread stacks.
+# It must be a power of 2, to make the cpu_info computation work,
+# and cpu_info needs to work to make SMP startup and threads work.
+config STACK_SIZE
+ hex
+ default 0x0800
+
# TODO We may probably move this to board-specific implementation files instead
# of KConfig values.
config CBFS_CACHE_ADDRESS
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6500
-gerrit
commit 0c143a40112d4ba0390e18d04e981014a159a983
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Aug 12 18:04:06 2013 -0700
exynos5420: Implement support to boot with USB A-A firmware upload
This patch ports the USB A-A firmware upload functionality from
exynos5250 over to exynos5420. Essentially just like a conflicless
cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes
the exact same bug with SPI initialization for Pit and Kirby.
Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65751
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132)
exynos5: Fix trivial style nits
A few curly braces on the wrong line.
Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66153
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb)
Squashed two related commits.
Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/alternate_cbfs.c | 15 ++--
src/cpu/samsung/exynos5420/Makefile.inc | 6 +-
src/cpu/samsung/exynos5420/alternate_cbfs.c | 115 ++++++++++++++++++++++++++++
src/cpu/samsung/exynos5420/alternate_cbfs.h | 44 +++++++++++
src/cpu/samsung/exynos5420/cpu.h | 16 ----
src/cpu/samsung/exynos5420/pinmux.c | 5 +-
src/cpu/samsung/exynos5420/spi.c | 7 --
src/mainboard/google/pit/romstage.c | 1 +
8 files changed, 177 insertions(+), 32 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c
index 1549486..49c9d4c 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c
@@ -43,7 +43,8 @@
* rest of the firmware's lifetime and all subsequent stages (which will not
* have __PRE_RAM__ defined) can just directly reference it there.
*/
-static int usb_cbfs_open(struct cbfs_media *media) {
+static int usb_cbfs_open(struct cbfs_media *media)
+{
#ifdef __PRE_RAM__
static int first_run = 1;
int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr;
@@ -72,14 +73,16 @@ static int usb_cbfs_open(struct cbfs_media *media) {
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count) {
+ size_t offset, size_t count)
+{
ASSERT(offset + count < alternate_cbfs_size);
memcpy(dest, alternate_cbfs_buffer + offset, count);
return count;
}
static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
- size_t count) {
+ size_t count)
+{
ASSERT(offset + count < alternate_cbfs_size);
return alternate_cbfs_buffer + offset;
}
@@ -87,7 +90,8 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
-static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) {
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
+{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
media->open = usb_cbfs_open;
@@ -99,7 +103,8 @@ static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) {
return 0;
}
-int init_default_cbfs_media(struct cbfs_media *media) {
+int init_default_cbfs_media(struct cbfs_media *media)
+{
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc
index 3191627..bb6d8fe 100644
--- a/src/cpu/samsung/exynos5420/Makefile.inc
+++ b/src/cpu/samsung/exynos5420/Makefile.inc
@@ -3,7 +3,7 @@
# image outside of CBFS
INTERMEDIATE += exynos5420_add_bl1
-bootblock-y += spi.c
+bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c
@@ -16,7 +16,7 @@ bootblock-y += wakeup.c
bootblock-y += gpio.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c
-romstage-y += spi.c
+romstage-y += spi.c alternate_cbfs.c
romstage-y += smp.c
romstage-y += clock.c
romstage-y += clock_init.c
@@ -36,7 +36,7 @@ romstage-y += i2c.c
#romstage-y += wdt.c
romstage-y += cbmem.c
-ramstage-y += spi.c
+ramstage-y += spi.c alternate_cbfs.c
ramstage-y += clock.c
ramstage-y += clock_init.c
ramstage-y += pinmux.c
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c
new file mode 100644
index 0000000..49c9d4c
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <assert.h>
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <stdlib.h>
+#include <string.h>
+#include <console/console.h>
+#include "alternate_cbfs.h"
+#include "spi.h"
+
+/* This allows USB A-A firmware upload from a compatible host in four parts:
+ * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * written to their respective loading addresses. These transfers are initiated
+ * by the IROM / BL1, so this code has nothing to do with them.
+ *
+ * The third transfer is a valid CBFS image that contains only the romstage,
+ * and must be small enough to fit into alternate_cbfs_size[__BOOT_BLOCK__] in
+ * IRAM. It is loaded when this function gets called in the boot block, and
+ * the normal CBFS code extracts the romstage from it.
+ *
+ * The fourth transfer is also a CBFS image, but can be of arbitrary size and
+ * should contain all available stages/payloads/etc. It is loaded when this
+ * function is called a second time at the end of the romstage, and copied to
+ * alternate_cbfs_buffer[!__BOOT_BLOCK__] in DRAM. It will reside there for the
+ * rest of the firmware's lifetime and all subsequent stages (which will not
+ * have __PRE_RAM__ defined) can just directly reference it there.
+ */
+static int usb_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ static int first_run = 1;
+ int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr;
+
+ if (!first_run)
+ return 0;
+
+ if (!irom_load_usb()) {
+ printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ return -1;
+ }
+
+ /*
+ * We need to trust the host/irom to copy the image to our
+ * alternate_cbfs_buffer address... there is no way to control or even
+ * check the transfer size or target address from our side.
+ */
+
+ printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now"
+ " be at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < alternate_cbfs_size);
+ memcpy(dest, alternate_cbfs_buffer + offset, count);
+ return count;
+}
+
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < alternate_cbfs_size);
+ return alternate_cbfs_buffer + offset;
+}
+
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
+
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
+
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
+ return initialize_exynos_usb_cbfs_media(media);
+
+ /* TODO: implement SDMMC (and possibly other) boot mode */
+
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+}
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h
new file mode 100644
index 0000000..a26fe61
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
+#define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
+
+/* These are pointers to function pointers. Double indirection! */
+void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
+void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
+void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
+void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
+void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
+
+#define SECONDARY_BASE_BOOT_USB 0xfeed0002
+u32 * const iram_secondary_base = (u32 *)0x02020018;
+
+#if defined(__BOOT_BLOCK__)
+ /* A small space in IRAM to hold the romstage-only image */
+ void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
+ size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
+#else
+ /* Just put this anywhere in RAM that's far enough from anything else */
+ /* TODO: Find a better way to "reserve" this region? */
+ void * const alternate_cbfs_buffer = (void *)0x77400000;
+ size_t const alternate_cbfs_size = 0xc00000;
+#endif
+
+#endif
diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h
index 8d3d48b..44b3464 100644
--- a/src/cpu/samsung/exynos5420/cpu.h
+++ b/src/cpu/samsung/exynos5420/cpu.h
@@ -26,22 +26,6 @@
#define EXYNOS_PRO_ID 0x10000000
-/* Address of address of function that copys data from SD or MMC */
-#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030
-
-/* Address of address of function that copys data from SPI */
-#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
-
-/* Address of address of function that copys data through USB */
-#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
-
-/* Boot mode values */
-#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
-
-#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
-
-#define EXYNOS_I2C_SPACING 0x10000
-
/* EXYNOS5 */
#define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */
#define EXYNOS5_PRO_ID 0x10000000
diff --git a/src/cpu/samsung/exynos5420/pinmux.c b/src/cpu/samsung/exynos5420/pinmux.c
index 507ee86..7843487 100644
--- a/src/cpu/samsung/exynos5420/pinmux.c
+++ b/src/cpu/samsung/exynos5420/pinmux.c
@@ -139,8 +139,11 @@ static void exynos_pinmux_spi(int start, int cfg)
{
int i;
- for (i = start; i < start + 4; i++)
+ for (i = start; i < start + 4; i++) {
gpio_cfg_pin(i, cfg);
+ gpio_set_pull(i, GPIO_PULL_NONE);
+ gpio_set_drv(i, GPIO_DRV_3X);
+ }
}
void exynos_pinmux_spi0(void)
diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c
index 46b9ced..7b9febc 100644
--- a/src/cpu/samsung/exynos5420/spi.c
+++ b/src/cpu/samsung/exynos5420/spi.c
@@ -408,10 +408,3 @@ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
return 0;
}
-
-int init_default_cbfs_media(struct cbfs_media *media) {
- return initialize_exynos_spi_cbfs_media(
- media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS,
- CONFIG_CBFS_CACHE_SIZE);
-}
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 7037112..319ebf9 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -278,6 +278,7 @@ void main(void)
/* Set SPI (primary CBFS media) clock to 50MHz. */
/* if this is uncommented SPI will not work correctly. */
clock_set_rate(PERIPH_ID_SPI1, 50000000);
+ exynos_pinmux_spi1();
simple_spi_test();
cbmem_initialize_empty();
the following patch was just integrated into master:
commit 396b0722978f9254a3d012210a89ccdead23a916
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Sep 26 16:22:09 2013 -0700
tegra124: Add a stub implementation of the tegra124 SOC.
Most things still needs to be filled in, but this will allow us to build
boards which use this SOC.
Change-Id: Ic790685a78193ccb223f4d9355bd3db57812af39
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170836
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 462456fd00164c10c80eff72240226a04445fe60)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6431
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6431 for details.
-gerrit
the following patch was just integrated into master:
commit 1ee2c6dbdfe7e35ab5e25a6136eab824ed2fec8f
Author: Gabe Black <gabeblack(a)google.com>
Date: Fri Aug 9 04:27:35 2013 -0700
libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.
When libpayload header files are included in the payload itself, it's possible
that the payloads config settings will conflict with the ones in libpayload.
It's also possible for the libpayload config settings to conflict with the
payloads. To avoid that, the libpayload config settings have _LP_ (for
libpayload) added to them. The symbols themselves as defined in the Config.in files
are still the same, but the prefix added to them is now CONFIG_LP_ instead of just
CONFIG_.
Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65303
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6427
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6427 for details.
-gerrit
the following patch was just integrated into master:
commit b77431336e44ba9721f18220e2a7dedafe250528
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Fri Aug 9 18:19:29 2013 -0700
exynos5420: get rid of old exynos5420_config_l2_cache()
We set up L2 cache early in romstage now so the old
function is now redundant.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
Reviewed-on: https://gerrit.chromium.org/gerrit/65428
Reviewed-by: Hung-Te Lin <hungte(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)
exynos: stack size: Increase the stack size to 16KB.
The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
which is shared between the bootblock, rom stage, and ram stage. The stack had
been much too small and needed to be expanded.
Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65937
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)
exynos: gpio: add a bigger delay when reading board strappings
Z-state pins were not reading reliably with a 5us delay, so increase
it to 15us.
This is ported from https://gerrit.chromium.org/gerrit/64338
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
Reviewed-on: https://gerrit.chromium.org/gerrit/65727
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
Tested-by: Ronald G. Minnich <rminnich(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)
exynos5420: enable DMC internal clock gating
lets enable memory controller internal clock gating for ddr3.
with these bits enabled we save some power out of ddr3.
This is ported from https://gerrit.chromium.org/gerrit/#/c/60774
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
Reviewed-on: https://gerrit.chromium.org/gerrit/65728
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)
exynos5420: Correct the 600MHz PMS value
In UM ver0.02, 600MHz clock PMS values differs from what is programed
currently. Though this also results in 600MHz clock, but it is better to
match what UM says. This patch chnage this as per UM
This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
(Note: we already used the correct 600MHz value for KPLL)
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
Reviewed-on: https://gerrit.chromium.org/gerrit/65726
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
Tested-by: Ronald G. Minnich <rminnich(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)
Squashed five commits pertaining to exynos.
Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6425
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6425 for details.
-gerrit
Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6499
-gerrit
commit c3ab7c8d471ef08d7ce943052573e2005c2ee38a
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Tue Aug 5 10:20:59 2014 -0600
gizmosphere/gizmo: Change the PCIe GPP to two x1 ports
Gizmo sends two southbridge GPP PCIe lanes to its high speed
edge connector. This change will allow developers to create
two x1 slots on an extender card.
Change-Id: Iba6c1a4caf7846d12e3960775d7bc906ca8ff385
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/mainboard/gizmosphere/gizmo/devicetree.cb | 5 +++--
src/mainboard/gizmosphere/gizmo/platform_cfg.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb
index 301f79a..8cd4cd3 100755
--- a/src/mainboard/gizmosphere/gizmo/devicetree.cb
+++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb
@@ -50,10 +50,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.3 on end # LPC 0x439d
device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
device pci 14.5 off end # USB 2
- device pci 15.0 on end # PCIe PortA # PCIe x4 slot off of high speed edge connector
+ device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
+ device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
- register "gpp_configuration" = "0" #4:0:0:0
+ register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
device pci 18.0 on end
diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h
index 0c9fa86..401d981 100755
--- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h
+++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h
@@ -185,7 +185,7 @@
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
-#define GPP_CFGMODE GPP_CFGMODE_X4000
+#define GPP_CFGMODE GPP_CFGMODE_X1111
/**
* @def NB_SB_GEN2
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6487
-gerrit
commit c16ec26a6c7cc79319be73eb291e95fb2d09441d
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Mon Aug 4 08:22:39 2014 +0200
util/sconfig/main.c: Free memory pointed to by `outputc`
Cppcheck 1.65 reports the error below.
[main.c:709]: (error) Memory leak: outputc
So free the memory space pointed to by `outputc` to fix the memory
leak.
Change-Id: I1767cd15380832a93cc79fb515861982e3f1ee94
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
util/sconfig/main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 91fb8cb..03d7a03 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -631,6 +631,7 @@ int main(int argc, char** argv) {
perror(NULL);
exit(1);
}
+ free(outputc);
struct header *h;
if (scan_mode == STATIC_MODE) {