coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 4acd8ea slippy/flaco/peppy: setup beep verbs
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit 4acd8ea778388392475ee14cb5efe5f453da3159 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Aug 21 05:21:21 2013 -0600 slippy/flaco/peppy: setup beep verbs Add verb setting for beep during recovery and dev mode. Requires depthcharge CL. Change-Id: I13cbb4e889ebc4c27bb4ab9fa49601b03e872d09 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66519 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Dylan Reid <dgreid(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit c072543946b317192a8e80a744c1515deb414456) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6502 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6502 for details. -gerrit

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New patch to review for coreboot: 1768742 exynos: Set up caching in the bootblock.
by Isaac Christensen 06 Aug '14

06 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6511 -gerrit commit 17687426825ef28d89945e0f43b52e5424b48c78 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Aug 13 21:05:43 2013 -0700 exynos: Set up caching in the bootblock. This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/armv7/Makefile.inc | 1 + src/arch/armv7/mmu.c | 29 ++++++++--------------------- src/cpu/samsung/exynos5250/Kconfig | 9 +++++++++ src/cpu/samsung/exynos5420/Kconfig | 9 +++++++++ src/cpu/samsung/exynos5420/bootblock.c | 15 +++++++++++++++ src/cpu/samsung/exynos5420/wakeup.c | 3 +++ src/mainboard/google/pit/mainboard.c | 10 ++-------- 7 files changed, 47 insertions(+), 29 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 2188706..bf2f332 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -56,6 +56,7 @@ bootblock-y += eabi_compat.c bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S +bootblock-y += mmu.c bootblock_lds = $(src)/arch/armv7/bootblock.lds bootblock_lds += $(chipset_bootblock_lds) diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c index 7d6d46a..17ad8b7 100644 --- a/src/arch/armv7/mmu.c +++ b/src/arch/armv7/mmu.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <stdlib.h> #include <stdint.h> @@ -36,14 +37,12 @@ #include <arch/cache.h> #include <arch/io.h> -#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ - -static uintptr_t ttb_addr; +static void *const ttb_buff = (void *)CONFIG_TTB_BUFFER; void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) { unsigned int i; - uint32_t *ttb_entry = (uint32_t *)ttb_addr; + uint32_t *ttb_entry = ttb_buff; printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", start_mb*MiB, start_mb*MiB + size_mb*MiB - 1); @@ -61,7 +60,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, { unsigned int i; uint32_t attr; - uint32_t *ttb_entry = (uint32_t *)ttb_addr; + uint32_t *ttb_entry = ttb_buff; const char *str = NULL; /* @@ -116,24 +115,14 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, void mmu_init(void) { - unsigned int ttb_size; - uint32_t ttbcr; - /* * For coreboot's purposes, we will create a simple L1 page table * in RAM with 1MB section translation entries over the 4GB address * space. * (ref: section 10.2 and example 15-4 in Cortex-A series * programmer's guide) - * - * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to - * 512 bytes. So allocate some extra space in cbmem and fix-up the - * pointer. - */ - ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t); - ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB); - ttb_addr = ALIGN(ttb_addr, 16*KiB); - printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); + */ + printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff); /* * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0 @@ -141,16 +130,14 @@ void mmu_init(void) * * ref: Arch Ref. Manual for ARMv7-A, B3.5.4, */ - ttbcr = read_ttbcr(); - ttbcr &= ~(0x3); - write_ttbcr(ttbcr); + write_ttbcr(read_ttbcr() & ~0x3); /* * Translation table base 0 address is in bits 31:14-N, where N is given * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this * register should be zero for coreboot. */ - write_ttbr0(ttb_addr); + write_ttbr0((uintptr_t)ttb_buff); /* disable domain-level checking of permissions */ write_dacr(~0); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index e0e179d..f937e7b 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -85,6 +85,15 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00018000 +# TTB needs to be aligned to 16KB. +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0x02058000 + +config TTB_SIZE + hex "size of the TTB buffer" + default 0x4000 + config SYS_SDRAM_BASE hex default 0x40000000 diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 66679a0..fe475ab 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -46,6 +46,7 @@ config CBFS_ROM_OFFSET # 0x0202_4400: variable length bootblock checksum header. # 0x0202_4410: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. +# 0x0205_8000: TTB buffer. # 0x0205_c000: cache for CBFS data. # 0x0206_f000: stack bottom # 0x0207_3000: stack pointer @@ -110,6 +111,14 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00013000 +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0x02058000 + +config TTB_SIZE + hex "size of the TTB buffer" + default 0x4000 + config SYS_SDRAM_BASE hex default 0x20000000 diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index 5cc9ef6..3df51a7 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -17,10 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> + #include "clk.h" #include "wakeup.h" #include "cpu.h" +/* convenient shorthand (in MB) */ +#define SRAM_START (0x02020000 >> 20) +#define SRAM_SIZE 1 +#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ + void bootblock_cpu_init(void); void bootblock_cpu_init(void) { @@ -51,6 +58,14 @@ void bootblock_cpu_init(void) /* Never returns. */ } + /* set up dcache and MMU */ + mmu_init(); + mmu_config_range(0, SRAM_START, DCACHE_OFF); + mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); + dcache_invalidate_all(); + dcache_mmu_enable(); + /* For most ARM systems, we have to initialize firmware media source * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. diff --git a/src/cpu/samsung/exynos5420/wakeup.c b/src/cpu/samsung/exynos5420/wakeup.c index 5764c83..af7ef73 100644 --- a/src/cpu/samsung/exynos5420/wakeup.c +++ b/src/cpu/samsung/exynos5420/wakeup.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> #include <console/console.h> #include "power.h" #include "wakeup.h" @@ -27,6 +28,8 @@ void wakeup(void) power_reset(); power_init(); /* Ensure ps_hold_setup() for early wakeup. */ + dcache_mmu_disable(); + icache_invalidate_all(); power_exit_wakeup(); /* Should never return. */ die("Failed to wake up.\n"); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index e453e67..a02967b 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -43,7 +43,6 @@ /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ static struct edid edid = { .ha = 1366, @@ -432,14 +431,9 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; - /* set up dcache and MMU */ - /* FIXME: this should happen via resource allocator */ - mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); + /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); - dcache_invalidate_all(); - dcache_mmu_enable(); + tlb_invalidate_all(); /* this is going to move, but we must have it now and we're * not sure where */

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Patch merged into coreboot/master: 61fcd14 Exynos5: Remove unneeded USB delays
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit 61fcd14561b226c4cca32148629c4ed42db9f645 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Aug 14 17:14:39 2013 -0700 Exynos5: Remove unneeded USB delays Change-Id: I1144e9d6d6c4278842fdd36743c8a88555f81707 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65912 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 95b518877edc88347ce9725ffee32f3aed0de7dc) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6505 for details. -gerrit

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Patch merged into coreboot/master: bc6cc11 Exynos5420: tighten up display port delays
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit bc6cc112e2a4a2474c8ce946faea24980732762a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Aug 16 19:53:41 2013 -0700 Exynos5420: tighten up display port delays Shorten a few delays, and make some delays shorter but let the loops have a higher termination count (i.e. give it the same amount of time to warm up, but check more frequently). Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66156 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6506 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6506 for details. -gerrit

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Patch merged into coreboot/master: f2c4241 exynos5420: Fix mmc clock source.
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit f2c4241b810665bbeb5f9e2f8c00cb2d0d4e6622 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Aug 22 23:56:35 2013 +0800 exynos5420: Fix mmc clock source. The DWMMC controller internally divided clock by values in CLKSEL registers, so we must adjust MMC clock for that. Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66657 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6504 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6504 for details. -gerrit

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New patch to review for coreboot: bec2642 Exynos5420: invoke the cooperative threading in udelay
by Isaac Christensen 06 Aug '14

06 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6510 -gerrit commit bec264203778168f41b9a178a9fcb61d63bed02d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Aug 18 20:01:07 2013 -0700 Exynos5420: invoke the cooperative threading in udelay Call thread_yield_microseconds in udelay. This works with and without COOP_MULTITASKING enabled. Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66327 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5420/timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/timer.c b/src/cpu/samsung/exynos5420/timer.c index 88e1f3e..f8d3110 100644 --- a/src/cpu/samsung/exynos5420/timer.c +++ b/src/cpu/samsung/exynos5420/timer.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <timer.h> #include <delay.h> - +#include <thread.h> #include "clk.h" void init_timer(void) @@ -33,6 +33,9 @@ void udelay(unsigned usec) { struct mono_time current, end; + if (!thread_yield_microseconds(usec)) + return; + timer_monotonic_get(&current); end = current; mono_time_add_usecs(&end, usec);

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Patch merged into coreboot/master: d6b16f5 Set armv7 up for cpu_info to work as on x86 (so threads can work)
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit d6b16f54b9c34a8095a3eefbaf334150c15cecb5 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Aug 16 15:57:56 2013 -0700 Set armv7 up for cpu_info to work as on x86 (so threads can work) On x86, cpu_info lives at the top of stack. Make the arm do that as well, as the threading model needs that and so will multicore support. As part of this change, make the stack size a power of 2. Also make it much smaller -- 2048 bytes is PLENTY for ram stage. Note that the small stack size is counterintuitive for rom stage. How can this work in rom stage, which needs a HUGE stack for lzma? The main use of STACK_SIZE has always been in ram stage; since 2002 or so it was to size per-core stacks (see, e.g., src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE and, more recently, thread stacks. So, we define the STACK_TOP for rom and ram stage, but the STACK_SIZE has no real effect on the ROM stage (no hardware red zones on the stack) and hence we're ok with actually defining the "wrong" stack size. In fact, the coreboot_ram ldscript for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc Observed stack usage in ramstage: BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1 Jumping to boot code at 23104044 CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes entry = 23104044 Which means we do need 2K, not 1K. Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66135 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6501 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6501 for details. -gerrit

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Patch merged into coreboot/master: 7111835 lenovo/x201: Enable pcie lanes in wwan slot.
by gerrit＠coreboot.org 06 Aug '14

06 Aug '14

the following patch was just integrated into master: commit 7111835f3900aaf2e1a23a62029daa668963fbe1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 14:55:14 2014 +0200 lenovo/x201: Enable pcie lanes in wwan slot. Change-Id: I7332eeed244877252074e661f1c256a69a9b428a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6482 for details. -gerrit

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Patch set updated for coreboot: a149aa7 exynos5420: Implement support to boot with USB A-A firmware upload
by Isaac Christensen 06 Aug '14

06 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6500 -gerrit commit a149aa7b9759d817f359928e6756a1c3e54641f2 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 12 18:04:06 2013 -0700 exynos5420: Implement support to boot with USB A-A firmware upload This patch ports the USB A-A firmware upload functionality from exynos5250 over to exynos5420. Essentially just like a conflictless cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes the exact same bug with SPI initialization for Pit and Kirby. Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65751 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132) exynos5: Fix trivial style nits A few curly braces on the wrong line. Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66153 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb) Squashed two related commits. Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5250/alternate_cbfs.c | 15 ++-- src/cpu/samsung/exynos5420/Makefile.inc | 6 +- src/cpu/samsung/exynos5420/alternate_cbfs.c | 115 ++++++++++++++++++++++++++++ src/cpu/samsung/exynos5420/alternate_cbfs.h | 44 +++++++++++ src/cpu/samsung/exynos5420/cpu.h | 16 ---- src/cpu/samsung/exynos5420/pinmux.c | 5 +- src/cpu/samsung/exynos5420/spi.c | 7 -- src/mainboard/google/pit/romstage.c | 1 + 8 files changed, 177 insertions(+), 32 deletions(-) diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c index 1549486..49c9d4c 100644 --- a/src/cpu/samsung/exynos5250/alternate_cbfs.c +++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c @@ -43,7 +43,8 @@ * rest of the firmware's lifetime and all subsequent stages (which will not * have __PRE_RAM__ defined) can just directly reference it there. */ -static int usb_cbfs_open(struct cbfs_media *media) { +static int usb_cbfs_open(struct cbfs_media *media) +{ #ifdef __PRE_RAM__ static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -72,14 +73,16 @@ static int usb_cbfs_open(struct cbfs_media *media) { static int alternate_cbfs_close(struct cbfs_media *media) { return 0; } static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) { + size_t offset, size_t count) +{ ASSERT(offset + count < alternate_cbfs_size); memcpy(dest, alternate_cbfs_buffer + offset, count); return count; } static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) { + size_t count) +{ ASSERT(offset + count < alternate_cbfs_size); return alternate_cbfs_buffer + offset; } @@ -87,7 +90,8 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, static void *alternate_cbfs_unmap(struct cbfs_media *media, const void *buffer) { return 0; } -static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) { +static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) +{ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); media->open = usb_cbfs_open; @@ -99,7 +103,8 @@ static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) { return 0; } -int init_default_cbfs_media(struct cbfs_media *media) { +int init_default_cbfs_media(struct cbfs_media *media) +{ if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) return initialize_exynos_usb_cbfs_media(media); diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 3191627..bb6d8fe 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS INTERMEDIATE += exynos5420_add_bl1 -bootblock-y += spi.c +bootblock-y += spi.c alternate_cbfs.c bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c @@ -16,7 +16,7 @@ bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c -romstage-y += spi.c +romstage-y += spi.c alternate_cbfs.c romstage-y += smp.c romstage-y += clock.c romstage-y += clock_init.c @@ -36,7 +36,7 @@ romstage-y += i2c.c #romstage-y += wdt.c romstage-y += cbmem.c -ramstage-y += spi.c +ramstage-y += spi.c alternate_cbfs.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c new file mode 100644 index 0000000..49c9d4c --- /dev/null +++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <assert.h> +#include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include "alternate_cbfs.h" +#include "spi.h" + +/* This allows USB A-A firmware upload from a compatible host in four parts: + * The first two are the bare BL1 and the Coreboot boot block, which are just + * written to their respective loading addresses. These transfers are initiated + * by the IROM / BL1, so this code has nothing to do with them. + * + * The third transfer is a valid CBFS image that contains only the romstage, + * and must be small enough to fit into alternate_cbfs_size[__BOOT_BLOCK__] in + * IRAM. It is loaded when this function gets called in the boot block, and + * the normal CBFS code extracts the romstage from it. + * + * The fourth transfer is also a CBFS image, but can be of arbitrary size and + * should contain all available stages/payloads/etc. It is loaded when this + * function is called a second time at the end of the romstage, and copied to + * alternate_cbfs_buffer[!__BOOT_BLOCK__] in DRAM. It will reside there for the + * rest of the firmware's lifetime and all subsequent stages (which will not + * have __PRE_RAM__ defined) can just directly reference it there. + */ +static int usb_cbfs_open(struct cbfs_media *media) +{ +#ifdef __PRE_RAM__ + static int first_run = 1; + int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; + + if (!first_run) + return 0; + + if (!irom_load_usb()) { + printk(BIOS_ERR, "Unable to load CBFS image via USB!\n"); + return -1; + } + + /* + * We need to trust the host/irom to copy the image to our + * alternate_cbfs_buffer address... there is no way to control or even + * check the transfer size or target address from our side. + */ + + printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" + " be at %p\n", alternate_cbfs_buffer); + first_run = 0; +#endif + return 0; +} + +static int alternate_cbfs_close(struct cbfs_media *media) { return 0; } + +static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) +{ + ASSERT(offset + count < alternate_cbfs_size); + memcpy(dest, alternate_cbfs_buffer + offset, count); + return count; +} + +static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, + size_t count) +{ + ASSERT(offset + count < alternate_cbfs_size); + return alternate_cbfs_buffer + offset; +} + +static void *alternate_cbfs_unmap(struct cbfs_media *media, + const void *buffer) { return 0; } + +static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); + + media->open = usb_cbfs_open; + media->close = alternate_cbfs_close; + media->read = alternate_cbfs_read; + media->map = alternate_cbfs_map; + media->unmap = alternate_cbfs_unmap; + + return 0; +} + +int init_default_cbfs_media(struct cbfs_media *media) +{ + if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) + return initialize_exynos_usb_cbfs_media(media); + + /* TODO: implement SDMMC (and possibly other) boot mode */ + + return initialize_exynos_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE); +} diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h new file mode 100644 index 0000000..4e9dff9 --- /dev/null +++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H +#define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H + +/* These are pointers to function pointers. Double indirection! */ +void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030; +void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044; +void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048; +void * * const irom_spi_sf_read_ptr = (void * *)0x02020058; +void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; + +#define SECONDARY_BASE_BOOT_USB 0xfeed0002 +u32 * const iram_secondary_base = (u32 *)0x02020018; + +#if defined(__BOOT_BLOCK__) + /* A small space in IRAM to hold the romstage-only image */ + void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; + size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE; +#else + /* Just put this anywhere in RAM that's far enough from anything else */ + /* TODO: Find a better way to "reserve" this region? */ + void * const alternate_cbfs_buffer = (void *)0x77400000; + size_t const alternate_cbfs_size = 0xc00000; +#endif + +#endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */ diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 8d3d48b..44b3464 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -26,22 +26,6 @@ #define EXYNOS_PRO_ID 0x10000000 -/* Address of address of function that copys data from SD or MMC */ -#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030 - -/* Address of address of function that copys data from SPI */ -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 - -/* Address of address of function that copys data through USB */ -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 - -/* Boot mode values */ -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 - -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -#define EXYNOS_I2C_SPACING 0x10000 - /* EXYNOS5 */ #define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */ #define EXYNOS5_PRO_ID 0x10000000 diff --git a/src/cpu/samsung/exynos5420/pinmux.c b/src/cpu/samsung/exynos5420/pinmux.c index 507ee86..7843487 100644 --- a/src/cpu/samsung/exynos5420/pinmux.c +++ b/src/cpu/samsung/exynos5420/pinmux.c @@ -139,8 +139,11 @@ static void exynos_pinmux_spi(int start, int cfg) { int i; - for (i = start; i < start + 4; i++) + for (i = start; i < start + 4; i++) { gpio_cfg_pin(i, cfg); + gpio_set_pull(i, GPIO_PULL_NONE); + gpio_set_drv(i, GPIO_DRV_3X); + } } void exynos_pinmux_spi0(void) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 46b9ced..7b9febc 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -408,10 +408,3 @@ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, return 0; } - -int init_default_cbfs_media(struct cbfs_media *media) { - return initialize_exynos_spi_cbfs_media( - media, - (void*)CONFIG_CBFS_CACHE_ADDRESS, - CONFIG_CBFS_CACHE_SIZE); -} diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 7037112..319ebf9 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -278,6 +278,7 @@ void main(void) /* Set SPI (primary CBFS media) clock to 50MHz. */ /* if this is uncommented SPI will not work correctly. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); + exynos_pinmux_spi1(); simple_spi_test(); cbmem_initialize_empty();

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Patch set updated for coreboot: 7e87e64 cbfstool: process cbfs_payload_segment(s) in host byte order
by Aaron Durbin 06 Aug '14

06 Aug '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6498 -gerrit commit 7e87e64049818065f42f49dc175e1205ef5d5aed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 5 10:48:20 2014 -0500 cbfstool: process cbfs_payload_segment(s) in host byte order The printing routines of the cbfs_payload_segment assumed the type could be accessed in host order. Each of the fields need to be converted to the host order before inspecting the fields. In addition, this removes all the ntoh*() calls while processing the cbfs_payload_segment structures. cbfstool would crash adding entries or just printing entries containing a payload when -v was passed on the command line. Change-Id: Iff41c64a99001b9e3920e2e26828c5fd6e671239 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/cbfs-mkpayload.c | 17 ++++++++++++++++ util/cbfstool/cbfs.h | 2 ++ util/cbfstool/cbfs_image.c | 46 ++++++++++++++++++++++++------------------ 3 files changed, 45 insertions(+), 20 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 67002b0..adbe313 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -50,6 +50,23 @@ void xdr_segs(struct buffer *output, xdr_be.put32(&outheader, segs[i].mem_len); } } + +void xdr_get_seg(struct cbfs_payload_segment *out, + struct cbfs_payload_segment *in) +{ + struct buffer inheader; + + inheader.data = (void *)in; + inheader.size = sizeof(*in); + + out->type = xdr_be.get32(&inheader); + out->compression = xdr_be.get32(&inheader); + out->offset = xdr_be.get32(&inheader); + out->load_addr = xdr_be.get64(&inheader); + out->len = xdr_be.get32(&inheader); + out->mem_len = xdr_be.get32(&inheader); +} + int parse_elf_to_payload(const struct buffer *input, struct buffer *output, uint32_t arch, comp_algo algo) { diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 73ee49c..52a4a50 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -131,5 +131,7 @@ void cbfs_file_get_header(struct buffer *buf, struct cbfs_file *file); /* cbfs-mkpayload.c */ void xdr_segs(struct buffer *output, struct cbfs_payload_segment *segs, int nseg); +void xdr_get_seg(struct cbfs_payload_segment *out, + struct cbfs_payload_segment *in); #endif diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 12bc2fe..afe1298 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -595,34 +595,40 @@ static int cbfs_print_stage_info(struct cbfs_stage *stage, FILE* fp) return 0; } -static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *payload, +/* Return 1 when segment is of type PAYLOAD_SEGMENT_ENTRY. */ +static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *seg_be, FILE *fp) { - switch(payload->type) { + struct cbfs_payload_segment payload; + + xdr_get_seg(&payload, seg_be); + + switch(payload.type) { case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: fprintf(fp, " %s (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d)\n", - (payload->type == PAYLOAD_SEGMENT_CODE ? + (payload.type == PAYLOAD_SEGMENT_CODE ? "code " : "data"), lookup_name_by_type(types_cbfs_compression, - ntohl(payload->compression), + payload.compression, "(unknown)"), - ntohl(payload->offset), - ntohll(payload->load_addr), - ntohl(payload->len), ntohl(payload->mem_len)); + payload.offset, + payload.load_addr, + payload.len, payload.mem_len); break; case PAYLOAD_SEGMENT_ENTRY: fprintf(fp, " entry (0x%" PRIx64 ")\n", - ntohll(payload->load_addr)); + payload.load_addr); + return 1; break; case PAYLOAD_SEGMENT_BSS: fprintf(fp, " BSS (address 0x%016" PRIx64 ", " "length 0x%x)\n", - ntohll(payload->load_addr), - ntohl(payload->len)); + payload.load_addr, + payload.len); break; case PAYLOAD_SEGMENT_PARAMS: @@ -632,14 +638,14 @@ static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *payload, default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", - payload->type, + payload.type, lookup_name_by_type(types_cbfs_compression, - payload->compression, + payload.compression, "(unknown)"), - ntohl(payload->offset), - ntohll(payload->load_addr), - ntohl(payload->len), - ntohl(payload->mem_len)); + payload.offset, + payload.load_addr, + payload.len, + payload.mem_len); break; } return 0; @@ -685,11 +691,11 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); while (payload) { - cbfs_print_payload_segment_info(payload, fp); - if (payload->type == PAYLOAD_SEGMENT_ENTRY) + /* Stop when PAYLOAD_SEGMENT_ENTRY seen. */ + if (cbfs_print_payload_segment_info(payload, + fp)) break; - else - payload ++; + payload ++; } break; default:

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coreboot-gerrit August 2014