coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

1 participants
1011 discussions

Patch merged into coreboot/master: 71e1c83 Exynos 5420: skip the EDID read if there is already an EDID.
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit 71e1c8303b1c5e805f32eda5a8b5a18f9f354399 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Aug 27 14:06:19 2013 -0700 Exynos 5420: skip the EDID read if there is already an EDID. For many boards, the EDID is known and is set in the ramstage. Reading the EDID is slow and if we have it we do not want to reread it. If the raw_edid struct member is non-null, skip reading the EDID. Change-Id: I63fb11aa90b2f739a351cdc3209faac2713ea451 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/167116 Reviewed-by: Gabe Black <gabeblack(a)google.com> Tested-by: ron minnich <rminnich(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)google.com> (cherry picked from commit 80f48655570de544a7e1939c4f5f28713f11d829) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6514 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6514 for details. -gerrit

1 0

Patch merged into coreboot/master: 34352d1 Possible thread stack implementation.
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit 34352d16a96b8096094274dddae98e37939857b9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Aug 21 16:03:32 2013 -0700 Possible thread stack implementation. Architecture provides a function for thread stack base, thread code uses it. Build and boot tested on Falco with multitasking on and off. Change-Id: I5016fab47f9954379acf7702ac7965b0a70c88ed Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66578 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 3c6afef30c1a0ad6fba0fb76acc792184d924247) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6513 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6513 for details. -gerrit

1 0

Patch merged into coreboot/master: 0ffa11b exynos5420: Set the CLK_DIV_CPERI1 value as per manual
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit 0ffa11bdbba48defc55cd38fb2aa2492ca2b5492 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 22 16:52:38 2013 -0700 exynos5420: Set the CLK_DIV_CPERI1 value as per manual Set the CLK_DIV_CPERI1 value as recommended by the 0.02 UM section 7.9.1.25. This suggests to use 0x3F3F0000 as the value to be set to save power. This is ported from https://gerrit.chromium.org/gerrit/#/c/64905 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I89a6a72d20374a513019a272628a05e139b31773 Reviewed-on: https://gerrit.chromium.org/gerrit/66787 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6512 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6512 for details. -gerrit

1 0

New patch to review for coreboot: 2c68dde Falco/Slippy: remove unwanted scratchpad writes
by Isaac Christensen 07 Aug '14

07 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6525 -gerrit commit 2c68ddefaa8557939057d64162302b579c5ea561 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Aug 13 16:09:33 2013 -0700 Falco/Slippy: remove unwanted scratchpad writes Register range 0x4f000 - 0x4f08f includes scratchpad registers. Fastboot works fine with these registers removed and graphics is initialized properly Change-Id: Ic57c526a90619f4a073690440f6c5ac6ca96bf10 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65755 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7e7befdc3956cbc28d346545669cb55c566cf3ea) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/slippy/gma.c | 14 -------- src/mainboard/google/slippy/i915io.c | 67 ------------------------------------ 2 files changed, 81 deletions(-) diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index f2f93b1..b38cced 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -188,25 +188,11 @@ static void gma_fui_init(int noisy) io_i915_write32(0x8000298e,CPU_VGACNTRL); io_i915_write32(0x00000000,_DSPASIZE+0xc); io_i915_write32(0x00000000,_DSPBSURF); - io_i915_write32(0x00000000,0x4f008); - io_i915_write32(0x00000000,0x4f008); - io_i915_write32(0x00000000,0x4f008); - io_i915_write32(0x01000001,0x4f040); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000000,0x4f048); - io_i915_write32(0x03030000,0x4f04c); - io_i915_write32(0x00000000,0x4f050); - io_i915_write32(0x00000001,0x4f054); - io_i915_write32(0x00000000,0x4f058); - io_i915_write32(0x03450000,0x4f04c); - io_i915_write32(0x45450000,0x4f04c); - io_i915_write32(0x03000400,0x4f000); io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A); io_i915_write32(0x00200090,_FDI_RXA_MISC); io_i915_write32(0x0a000000,_FDI_RXA_MISC); io_i915_write32(0x00000070,0x46408); io_i915_write32(0x04000000,0x42090); - io_i915_write32(0xc0000000,0x4f050); io_i915_write32(0x00000000,0x9840); io_i915_write32(0xa4000000,0x42090); io_i915_write32(0x00001000,SOUTH_DSPCLK_GATE_D); diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c index 92cb0d3..0801122 100644 --- a/src/mainboard/google/slippy/i915io.c +++ b/src/mainboard/google/slippy/i915io.c @@ -54,35 +54,13 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00ffffff,0x64ea8); io_i915_write32(0x00040006,0x64eac); io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30); - io_i915_write32(0x0000020c,0x4f054); - intel_dp_wait_reg(0x0004f054, 0x0000020c); - io_i915_write32(0x00000000,0x4f008); - io_i915_write32(0x0000020c,0x4f054); - intel_dp_wait_reg(0x0004f054, 0x0000020c); - io_i915_write32(0x00000000,0x4f044); - intel_dp_wait_reg(0x0004f044, 0x00000000); - io_i915_write32(0x00000400,0x4f044); - intel_dp_wait_reg(0x0004f044, 0x00000400); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x01000008,0x4f040); - io_i915_write32(0x00000008,0x4f05c); - io_i915_write32(0x00000008,0x4f060); io_i915_write32(0x80000000,0x45400); intel_dp_wait_reg(0x00045400, 0xc0000000); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x45450000,0x4f04c); - io_i915_write32(0x45450000,0x4f04c); - io_i915_write32(0x03000400,0x4f000); io_i915_write32(0x8000298e,CPU_VGACNTRL); - io_i915_write32(0x00000000,0x4f044); io_i915_write32(0x00000000,_CURACNTR); io_i915_write32(0x00000000,_CURABASE); io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000400,0x4f044); io_i915_write32(0x00000000,_CURBCNTR_IVB); io_i915_write32(0x00000000,_CURBBASE_IVB); io_i915_write32(0x00000000,_DSPBCNTR); @@ -93,27 +71,13 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00000000,_DVSASURF); io_i915_write32(0x00008000,DEIIR); intel_dp_wait_reg(0x00044008, 0x00000000); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000600,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x01000008,0x4f040); - io_i915_write32(0x00000008,0x4f05c); - io_i915_write32(0x00000008,0x4f060); io_i915_write32(0x8020298e,CPU_VGACNTRL); - io_i915_write32(0x00000000,0x4f044); - intel_dp_wait_reg(0x0004f044, 0x00000000); io_i915_write32(/*0x00000800*/dp->stride,_DSPASTRIDE); io_i915_write32(0x00000000,_DSPAADDR); io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000000,0x4f044); intel_dp_sink_dpms(dp, 0); - io_i915_write32(0x00000001,0x4f008); - io_i915_write32(0x00000012,0x4f014); - intel_dp_get_max_downspread(dp, &read_val); intel_dp_set_m_n_regs(dp); @@ -133,7 +97,6 @@ void runio(struct intel_dp *dp) io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPASIZE+0xc); io_i915_write32(0x00000080,DEIIR); - intel_dp_wait_reg(0x00044008, 0x00000000); io_i915_write32(0x00230000,TRANS_DDI_FUNC_CTL_EDP); io_i915_write32(0x00000010,0x7f008); @@ -172,9 +135,6 @@ void runio(struct intel_dp *dp) io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2); io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1); - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000000,0x4f044); - /* some of this is not needed. */ io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30); io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL); @@ -183,29 +143,16 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00000000,DEIIR); io_i915_write32(0x80000000,0x45400); intel_dp_wait_reg(0x00045400, 0xc0000000); - io_i915_write32(0x03200500,0x4f000); - /* io_i915_write32(0x03000556,0x4f000); */ - io_i915_write32(0x03000400,0x4f000); io_i915_write32(0x80000000,0x45400); intel_dp_wait_reg(0x00045400, 0xc0000000); printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x6)"); - io_i915_write32(0x03000400,0x4f000); io_i915_write32(0x80000000,0x45400); intel_dp_wait_reg(0x00045400, 0xc0000000); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x45430000,0x4f04c); - io_i915_write32(0x43430000,0x4f04c); - io_i915_write32(0x02580320,0x4f000); io_i915_write32(0x8000298e,CPU_VGACNTRL); - io_i915_write32(0x00000000,0x4f044); io_i915_write32(0x00000000,_CURACNTR); io_i915_write32(0x00000000,_CURABASE); io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000400,0x4f044); io_i915_write32(0x00000000,_CURBCNTR_IVB); io_i915_write32(0x00000000,_CURBBASE_IVB); io_i915_write32(0x00000000,_DSPBCNTR); @@ -216,23 +163,12 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00000000,_DVSASURF); io_i915_write32(0x00008000,DEIIR); intel_dp_wait_reg(0x00044008, 0x00000000); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x00000000,0x4f044); /* we just turned vdd off. We're not going to wait. The panel is up. */ - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000600,0x4f044); - io_i915_write32(0x00000000,0x4f044); - io_i915_write32(0x01000008,0x4f040); - io_i915_write32(0x00000008,0x4f05c); - io_i915_write32(0x00000008,0x4f060); io_i915_write32(0x8020298e,CPU_VGACNTRL); - io_i915_write32(0x00000000,0x4f044); - intel_dp_wait_reg(0x0004f044, 0x00000000); io_i915_write32(/*0x00000640*/dp->stride,_DSPASTRIDE); io_i915_write32(0x00000000,_DSPAADDR); io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000000,0x4f044); io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPASIZE+0xc); /* io_i915_write32(dp->pfa_pos,_PFA_WIN_POS); */ @@ -250,8 +186,6 @@ void runio(struct intel_dp *dp) io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR); io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x98000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000400,0x4f044); - io_i915_write32(0x00000000,0x4f044); io_i915_write32( EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON |0x00000007,PCH_PP_CONTROL); @@ -260,5 +194,4 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00000000,SDEIIR); io_i915_write32(0x00000000,SDEIIR); io_i915_write32(0x00000000,DEIIR); - io_i915_write32(0x00001800,0x4f044); }

1 0

New patch to review for coreboot: 1b81f24 Pit: remove backlight delay
by Isaac Christensen 07 Aug '14

07 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6524 -gerrit commit 1b81f247d2243cd9452576eadde7b0401b57ec09 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Aug 21 14:37:36 2013 -0700 Pit: remove backlight delay Change-Id: Ia2e5427fec1bfff9babb9c59a3878323277f4f4c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66555 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 2b96235123d55db3ff5ae5c2454b65de831a1c18) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/pit/mainboard.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index e453e67..75d97a0 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -421,8 +421,6 @@ static void mainboard_init(device_t dev) device_info.raw_edid = panel_edid; exynos_init_dp(&device_info); - udelay(LCD_T3_DELAY_MS * 1000); - backlight_vdd(); backlight_pwm(); backlight_en();

1 0

Patch merged into coreboot/master: ee4bfbf exynos: Set up caching in the bootblock.
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit ee4bfbf3e142b17bf263f5ddb3840ed683a04635 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Aug 13 21:05:43 2013 -0700 exynos: Set up caching in the bootblock. This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6511 for details. -gerrit

1 0

Patch merged into coreboot/master: e10ef42 Exynos5420: invoke the cooperative threading in udelay
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit e10ef42a55705530f54e1f04bc25b21aeda5693a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Aug 18 20:01:07 2013 -0700 Exynos5420: invoke the cooperative threading in udelay Call thread_yield_microseconds in udelay. This works with and without COOP_MULTITASKING enabled. Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66327 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6510 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6510 for details. -gerrit

1 0

New patch to review for coreboot: d0b4140 ARMv7: Add stdint types needed for vboot library
by Isaac Christensen 07 Aug '14

07 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6523 -gerrit commit d0b41406567c8f911f71928e761980c4a4245994 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Sep 16 14:27:17 2013 -0700 ARMv7: Add stdint types needed for vboot library Change-Id: I778ea787b20a7d7d7b202b1b5e7f956d2fde6629 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/169621 (cherry picked from commit 499a4802b5ad070a0b82f3b291073aa05fa7946e) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/armv7/include/stdint.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/arch/armv7/include/stdint.h b/src/arch/armv7/include/stdint.h index a8a0230..9d41e63 100644 --- a/src/arch/armv7/include/stdint.h +++ b/src/arch/armv7/include/stdint.h @@ -75,6 +75,18 @@ typedef int8_t s8; typedef int16_t s16; typedef int32_t s32; +#ifndef UINT32_MAX +#define UINT32_MAX (4294967295U) +#endif +#ifndef UINT64_MAX +# define UINT64_MAX (18446744073709551615ULL) +#endif +#ifndef UINT64_C +#define UINT64_C(c) c ## ULL +#endif +#ifndef PRIu64 +#define PRIu64 "llu" +#endif #undef __HAVE_LONG_LONG__

1 0

New patch to review for coreboot: 46e379c chromeos: Add code to read FMAP on ARM
by Isaac Christensen 07 Aug '14

07 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6522 -gerrit commit 46e379ca62634f7917c347358cdd92ad805390b0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 17 14:15:16 2013 -0700 chromeos: Add code to read FMAP on ARM On ARM the SPI flash is not memory mapped. Use the CBFS interface to map the correct portion. Change-Id: I8ea9aa0119e90a892bf777313fdc389c4739154e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/169781 Reviewed-by: David Hendrix <dhendrix(a)chromium.org> (cherry picked from commit a263d3717e82c43fe91e7c4e82d167e74bf27527) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/vendorcode/google/chromeos/fmap.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c index 538b8c3..e0ec30b 100644 --- a/src/vendorcode/google/chromeos/fmap.c +++ b/src/vendorcode/google/chromeos/fmap.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <console/console.h> +#include <cbfs.h> #include "fmap.h" /* Find FMAP data structure in ROM. @@ -36,9 +37,19 @@ const struct fmap *fmap_find(void) * and possibly cros_bundle_firmware. */ +#if CONFIG_ARCH_X86 /* wrapping around 0x100000000 */ const struct fmap *fmap = (void *) (CONFIG_FLASHMAP_OFFSET - CONFIG_ROM_SIZE); +#elif CONFIG_ARCH_ARMV7 + struct cbfs_media default_media, *media; + media = &default_media; + init_default_cbfs_media(media); + media->open(media); + const struct fmap *fmap = (void *) + media->map(media, CONFIG_FLASHMAP_OFFSET, 4096); // FIXME size + media->close(media); +#endif if (memcmp(fmap, FMAP_SIGNATURE, sizeof(FMAP_SIGNATURE)-1)) { printk(BIOS_DEBUG, "No FMAP found at %p.\n", fmap); @@ -104,9 +115,11 @@ int find_fmap_entry(const char name[], void **pointer) base = (void *)(unsigned long)fmap->base; printk(BIOS_DEBUG, "FMAP: %s base at %p\n", name, base); } else { +#if CONFIG_ARCH_X86 base = (void *)(0 - CONFIG_ROM_SIZE); printk(BIOS_WARNING, "FMAP: No valid base address, using" " 0x%p\n", base); +#endif } *pointer = (void*) ((u32)base + area->offset);

1 0

New patch to review for coreboot: d3835cb chromeec: Implement full battery workaround at 6%
by Isaac Christensen 07 Aug '14

07 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6521 -gerrit commit d3835cb8c45a5e9ac23cf5f1eed444462a10ba13 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 16 14:22:57 2013 -0700 chromeec: Implement full battery workaround at 6% Currently the workaround for indicating a "full" battery kicks in at 3%, but this turns out to be too high for some devices. So move the workaround start point to 6% from full, or 94%. Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169549 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/ec/google/chromeec/acpi/battery.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 341911c..2ef1199 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -210,8 +210,8 @@ Device (BAT0) // https://bugzilla.kernel.org/show_bug.cgi?id=12632 Store (BTDF, Local2) - // See if within ~3% of full - ShiftRight (Local2, 5, Local3) + // See if within ~6% of full + ShiftRight (Local2, 4, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), LLess (Local1, Add (Local2, Local3)))) {

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2014