coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c14e961 falco: Remove RTD2132 chip and setup from devicetree
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit c14e961f239adb3635fb47ad4e4c5891b3b09a29 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 22 10:19:25 2013 -0700 falco: Remove RTD2132 chip and setup from devicetree This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6527 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6527 for details. -gerrit

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New patch to review for coreboot: 4561558 Falco/Slippy: Patch to remove redundant graphics initializations
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6536 -gerrit commit 45615580e163c78773c695df651aab1f3776eae9 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 15 15:23:58 2013 -0700 Falco/Slippy: Patch to remove redundant graphics initializations gma_fui_init repeats the initializations already performed in gma_setup_panel. These redundant initializations reset any gtt settings done before this call. Hence, they had to be done again after call to gma_fui_init. However, the call gma_fui_init is not required at all. Does not affect the behavior of suspend/resume. Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65997 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13) Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode Depending on the init_fb parameter: 1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this same page 2) For developer/recovery mode, we init the gtt to consecutive pages Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65633 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722) Squashed two graphics related commits for Falco/Slippy. Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/slippy/gma.c | 103 ++++++------------------------------ src/northbridge/intel/haswell/gma.c | 16 ++++-- 2 files changed, 29 insertions(+), 90 deletions(-) diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index b38cced..4b002ec 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include <drivers/intel/gma/i915.h> + /* * Here is the rough outline of how we bring up the display: * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD @@ -160,87 +161,6 @@ static void palette(void) } } -/* this is code known to be needed for FUI, and useful - * but not essential otherwise. At some point, we hope, - * it's always going to be on. It gets the chip - * into a known good state - * -- including turning on the power well -- - * which we're not sure is being done correctly. - * Does it belong here? It belongs somewhere in the - * northbridge, that we know. - */ -static void gma_fui_init(int noisy) -{ - printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x8)"); - printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x10)"); - printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x0)"); - printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x2)"); - printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x0)"); - printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x2)"); - io_i915_write32(0x80000000,0x45400); - intel_dp_wait_reg(0x00045400, 0xc0000000); - printk(BIOS_SPEW, "pci dev(0x0,0x0,0x0,0x14)"); - printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x17)"); - printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x18)"); - io_i915_write32(0x00000000,_CURACNTR); - io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR); - io_i915_write32(0x00000000,_DSPBCNTR); - io_i915_write32(0x8000298e,CPU_VGACNTRL); - io_i915_write32(0x00000000,_DSPASIZE+0xc); - io_i915_write32(0x00000000,_DSPBSURF); - io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A); - io_i915_write32(0x00200090,_FDI_RXA_MISC); - io_i915_write32(0x0a000000,_FDI_RXA_MISC); - io_i915_write32(0x00000070,0x46408); - io_i915_write32(0x04000000,0x42090); - io_i915_write32(0x00000000,0x9840); - io_i915_write32(0xa4000000,0x42090); - io_i915_write32(0x00001000,SOUTH_DSPCLK_GATE_D); - io_i915_write32(0x00004000,0x42080); - io_i915_write32(0x00ffffff,0x64f80); - io_i915_write32(0x0007000e,0x64f84); - io_i915_write32(0x00d75fff,0x64f88); - io_i915_write32(0x000f000a,0x64f8c); - io_i915_write32(0x00c30fff,0x64f90); - io_i915_write32(0x00060006,0x64f94); - io_i915_write32(0x00aaafff,0x64f98); - io_i915_write32(0x001e0000,0x64f9c); - io_i915_write32(0x00ffffff,0x64fa0); - io_i915_write32(0x000f000a,0x64fa4); - io_i915_write32(0x00d75fff,0x64fa8); - io_i915_write32(0x00160004,0x64fac); - io_i915_write32(0x00c30fff,0x64fb0); - io_i915_write32(0x001e0000,0x64fb4); - io_i915_write32(0x00ffffff,0x64fb8); - io_i915_write32(0x00060006,0x64fbc); - io_i915_write32(0x00d75fff,0x64fc0); - io_i915_write32(0x001e0000,0x64fc4); - io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A); - io_i915_write32(0x0006000e,DDI_BUF_TRANS_A+0x4); - io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x8); - io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0xc); - io_i915_write32(0x00c30fff,DDI_BUF_TRANS_A+0x10); - io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x14); - io_i915_write32(0x80aaafff,DDI_BUF_TRANS_A+0x18); - io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x1c); - io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x20); - io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0x24); - io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x28); - io_i915_write32(0x000c0004,DDI_BUF_TRANS_A+0x2c); - io_i915_write32(0x80c30fff,DDI_BUF_TRANS_A+0x30); - io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x34); - io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x38); - io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x3c); - io_i915_write32(0x80d75fff,DDI_BUF_TRANS_A+0x40); - io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x44); - io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL); - io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30); - io_i915_write32((PCH_PP_UNLOCK&0xabcd0000)| EDP_FORCE_VDD |0xabcd0008,PCH_PP_CONTROL); - mdelay(200); - io_i915_write32(0x0004af06,PCH_PP_DIVISOR); - /* we may need more but let's see. */ -} - void dp_init_dim_regs(struct intel_dp *dp); void dp_init_dim_regs(struct intel_dp *dp) { @@ -351,10 +271,9 @@ void mainboard_train_link(struct intel_dp *intel_dp) } int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); - + unsigned int gfx, unsigned int init_fb); int i915lightup(unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) + unsigned int pmmio, unsigned int pgfx, unsigned int init_fb) { int must_cycle_power = 0; struct intel_dp adp, *dp = &adp; @@ -377,6 +296,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, void runio(struct intel_dp *dp); void runlinux(struct intel_dp *dp); + dp->gen = 8; // ?? dp->is_haswell = 1; dp->DP = 0x2; @@ -396,7 +316,17 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, dp->aux_clock_divider = 0xe1; dp->precharge = 3; - gma_fui_init(0); + /* 1. Normal mode: Set the first page to zero and make + all GTT entries point to the same page + 2. Developer/Recovery mode: We do not zero out all + the pages pointed to by GTT in order to avoid wasting time */ + if (init_fb) + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); + else { + setgtt(0, FRAME_BUFFER_PAGES, physbase, 0); + memset((void*)graphics, 0, 4096); + } + //intel_prepare_ddi_buffers(0, 0); //ironlake_edp_panel_vdd_on(dp); dp->address = 0x50; @@ -426,9 +356,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, io_i915_write32(0x00000021,0x6f410); runio(dp); - palette(); - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); + palette(); pixels = dp->edid.ha * (dp->edid.va-4) * 4; printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 95c7b22..ee447bf 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -30,6 +30,10 @@ #include "chip.h" #include "haswell.h" +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif + struct gt_reg { u32 reg; u32 andmask; @@ -403,12 +407,18 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); u32 iobase, mmiobase, physbase; + /* Default set to 1 since it might be required for + stuff like seabios */ + unsigned int init_fb = 1; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base); +#ifdef CONFIG_CHROMEOS + init_fb = developer_mode_enabled() || recovery_mode_enabled(); +#endif + int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, + unsigned int gfx, unsigned int init_fb); + lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base, init_fb); if (lightup_ok) gfx_set_init_done(1); #endif

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Patch merged into coreboot/master: 45f868d Falco/Slippy: remove unwanted scratchpad writes
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 45f868d34f0116e092672b881c99a2aa0c773244 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Aug 13 16:09:33 2013 -0700 Falco/Slippy: remove unwanted scratchpad writes Register range 0x4f000 - 0x4f08f includes scratchpad registers. Fastboot works fine with these registers removed and graphics is initialized properly Change-Id: Ic57c526a90619f4a073690440f6c5ac6ca96bf10 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65755 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7e7befdc3956cbc28d346545669cb55c566cf3ea) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6525 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6525 for details. -gerrit

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Patch merged into coreboot/master: 42b1c34 ARMv7: Add stdint types needed for vboot library
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 42b1c34f7ba94fe2a615e320e126fae10e8de521 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Sep 16 14:27:17 2013 -0700 ARMv7: Add stdint types needed for vboot library Change-Id: I778ea787b20a7d7d7b202b1b5e7f956d2fde6629 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/169621 (cherry picked from commit 499a4802b5ad070a0b82f3b291073aa05fa7946e) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6523 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6523 for details. -gerrit

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New patch to review for coreboot: 4d4f25c model_106cx: don't blindly set Kconfig settings
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6535 -gerrit commit 4d4f25cf713b66abead4c9c0b6886e0baa078b24 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 17 22:01:48 2013 -0500 model_106cx: don't blindly set Kconfig settings The CPU_ADDR_BITS was being unconditionally set. Don't do that. Change-Id: Idbc63328fade8f5f05f7f46282139b86e6694989 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169711 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit 858f96d28d8d0aeffe58e1d4d1d559ad161aab66) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/intel/model_106cx/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 456c99d..3b690cf 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,7 +11,10 @@ config CPU_INTEL_MODEL_106CX select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS +if CPU_INTEL_MODEL_106CX + config CPU_ADDR_BITS int default 32 +endif

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Patch merged into coreboot/master: 9ad28b9 chromeos: Add code to read FMAP on ARM
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 9ad28b940f74a17c88069816df1f20c0b03a9552 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 17 14:15:16 2013 -0700 chromeos: Add code to read FMAP on ARM On ARM the SPI flash is not memory mapped. Use the CBFS interface to map the correct portion. Change-Id: I8ea9aa0119e90a892bf777313fdc389c4739154e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/169781 Reviewed-by: David Hendrix <dhendrix(a)chromium.org> (cherry picked from commit a263d3717e82c43fe91e7c4e82d167e74bf27527) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6522 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6522 for details. -gerrit

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New patch to review for coreboot: 4534038 vboot: Implement VbExGetTimer using monotonic timers
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6534 -gerrit commit 453403805d648ba17b22d922e5102280c4484eff Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Sep 16 14:23:16 2013 -0700 vboot: Implement VbExGetTimer using monotonic timers On x86 VbExGetTimer() uses rdtsc. However, on all other platforms, let's just use coreboot's monotonic timers. Change-Id: I0cd359f298be33776740305b111624147e2c850d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/169620 (cherry picked from commit e910bb17522d5de42c0fc3cc945278e733fa2553) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/vendorcode/google/chromeos/vboot_wrapper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot_wrapper.c b/src/vendorcode/google/chromeos/vboot_wrapper.c index fe3c022..d008de1 100644 --- a/src/vendorcode/google/chromeos/vboot_wrapper.c +++ b/src/vendorcode/google/chromeos/vboot_wrapper.c @@ -17,7 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/vtxprintf.h> +#if CONFIG_ARCH_X86 #include <cpu/x86/tsc.h> +#else +#include <timer.h> +#endif #include <rmodule.h> #include <stdlib.h> #include <string.h> @@ -123,7 +127,13 @@ void VbExDebug(const char *format, ...) uint64_t VbExGetTimer(void) { +#if CONFIG_ARCH_X86 return rdtscll(); +#else + struct mono_time mt; + timer_monotonic_get(&mt); + return mt.microseconds; +#endif } VbError_t VbExNvStorageRead(uint8_t *buf)

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New patch to review for coreboot: c3c82fa bolt: Set GPIO29 as input in S0, output+high in S3/S5
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6533 -gerrit commit c3c82fa1fc6cb1a2a6fc861834a584116141c00e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Sep 25 14:05:31 2013 -0700 bolt: Set GPIO29 as input in S0, output+high in S3/S5 This resolves WiFi issues after suspend/resume. It needs related SPI descriptor soft strap change to enable SLP_WLAN as a GPIO instead of owned by the ME. Change-Id: I03f4458d1e52a913770d391061baa6cfa41e8558 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170577 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit cf1fe0524ad4793c8c422dc3fed3007b7fc96038) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/bolt/gpio.h | 2 +- src/mainboard/google/bolt/smihandler.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/bolt/gpio.h b/src/mainboard/google/bolt/gpio.h index 4e7e8c4..ff6069c 100644 --- a/src/mainboard/google/bolt/gpio.h +++ b/src/mainboard/google/bolt/gpio.h @@ -52,7 +52,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_NATIVE, /* 29: NATIVE: WLAN_OFF_L */ + LP_GPIO_INPUT, /* 29: NATIVE: WLAN_OFF_L */ LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */ LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c index b392852..54dcb73 100644 --- a/src/mainboard/google/bolt/smihandler.c +++ b/src/mainboard/google/bolt/smihandler.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> @@ -87,6 +88,26 @@ void mainboard_smi_gpi(u32 gpi_sts) } } +static void bolt_wlan_off(void) +{ + u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u32 gpio_conf; + + /* Make sure pin is owned by GPIO subsystem and not ACPI */ + gpio_conf = inl(gpio_base + GPIO_OWNER(0)); + gpio_conf |= GPIO_OWNER_GPIO << 29; + outl(gpio_conf, gpio_base + GPIO_OWNER(0)); + + /* Set GPIO29 config to only be reset on RSMRST */ + gpio_conf = inl(gpio_base + GPIO_RESET(0)); + gpio_conf |= GPIO_RESET_RSMRST << 29; + outl(gpio_conf, gpio_base + GPIO_RESET(0)); + + /* Set WLAN_OFF_L (GPIO29) as Output GPIO driven high */ + gpio_conf = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH; + outl(gpio_conf, gpio_base + GPIO_CONFIG0(29)); +} + void mainboard_smi_sleep(u8 slp_typ) { /* Disable USB charging if required */ @@ -109,6 +130,9 @@ void mainboard_smi_sleep(u8 slp_typ) break; } + /* Set WLAN_OFF GPIO state */ + bolt_wlan_off(); + /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); google_chromeec_set_sci_mask(0);

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New patch to review for coreboot: 45c8032 Exynos5420: clean up SPI driver
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6532 -gerrit commit 45c8032f5f8cb703b587862b79345d9962f3b5a8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 17 14:08:29 2013 -0700 Exynos5420: clean up SPI driver That extra struct is not needed, we already defined it earlier on. Also fix coding style in the file. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I586d290f2f3ba2f44aca7fdee400b88547465599 Reviewed-on: https://chromium-review.googlesource.com/169780 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit f7df9f05fb707cac7976cd8a0b36bcf30cef8e0f) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5420/spi.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 7b9febc..0d2d6d7 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -342,13 +342,15 @@ struct exynos_spi_media { struct cbfs_simple_buffer buffer; }; -static int exynos_spi_cbfs_open(struct cbfs_media *media) { +static int exynos_spi_cbfs_open(struct cbfs_media *media) +{ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_open\n"); return spi_claim_bus(spi->slave); } -static int exynos_spi_cbfs_close(struct cbfs_media *media) { +static int exynos_spi_cbfs_close(struct cbfs_media *media) +{ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_close\n"); spi_release_bus(spi->slave); @@ -356,7 +358,8 @@ static int exynos_spi_cbfs_close(struct cbfs_media *media) { } static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) { + size_t offset, size_t count) +{ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; int bytes; DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count); @@ -365,7 +368,8 @@ static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest, } static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) { + size_t count) +{ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_map\n"); // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and @@ -376,7 +380,8 @@ static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset, } static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, - const void *address) { + const void *address) +{ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_unmap\n"); return cbfs_simple_buffer_unmap(&spi->buffer, address); @@ -384,18 +389,14 @@ static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, - size_t buffer_size) { + size_t buffer_size) +{ // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; - static struct exynos_spi_slave eslave = { - .slave = { .bus = 1, .rw = SPI_READ_FLAG, }, - .regs = samsung_get_base_spi1(), - .fifo_size = 64, - .half_duplex = 0, - }; + static struct exynos_spi_slave *eslave = &exynos_spi_slaves[1]; DEBUG_SPI("initialize_exynos_spi_cbfs_media\n"); - context.slave = &eslave.slave; + context.slave = &eslave->slave; context.buffer.allocated = context.buffer.last_allocate = 0; context.buffer.buffer = buffer_address; context.buffer.size = buffer_size;

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New patch to review for coreboot: e2c59e9 delay: Have mdelay() / delay() available in romstage, too
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6531 -gerrit commit e2c59e991db6461edb948fae0595741d8374d048 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 29 16:01:05 2013 -0700 delay: Have mdelay() / delay() available in romstage, too Some drivers (like the I2C TPM driver) call mdelay instead of udelay. While it's a shame that these chips are so slow, the overhead of having those functions available in romstage is minimal. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I1fa888fc5ca4489def16ac92e2f8260ccc26d792 Reviewed-on: https://chromium-review.googlesource.com/167542 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit 7083b6b843d803bd4ddbd8a5aaf9c5c05bad2044) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5298bbe..de153bb 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -25,6 +25,7 @@ bootblock-y += memcmp.c romstage-y += memchr.c romstage-y += memcmp.c rmodules-y += memcmp.c +romstage-y += delay.c romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c

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coreboot-gerrit August 2014