coreboot-gerrit August 2014

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New patch to review for coreboot: 8e69891 southbridge/amd/cs5536: Trivial style fix for trailing comment
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6557 -gerrit commit 8e698916c0d3b9941a585d26b4dbe47e0a6b0c9f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:38:56 2014 +1000 southbridge/amd/cs5536: Trivial style fix for trailing comment Change-Id: Ia3a846497c220866e950a4b0bb53cb05c0e0cee2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cs5536/chip.h | 2 +- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/amd/cs5536/smbus.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 82d9434..9e843be 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -40,4 +40,4 @@ struct southbridge_amd_cs5536_config { unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */ }; -#endif /* _SOUTHBRIDGE_AMD_CS5536 */ +#endif /* _SOUTHBRIDGE_AMD_CS5536 */ diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index c193d9d..b722560 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -451,4 +451,4 @@ void chipsetinit(void); #endif #endif -#endif /* _CS5536_H */ +#endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h index 0dd2fc5..3e72dad 100644 --- a/src/southbridge/amd/cs5536/smbus.h +++ b/src/southbridge/amd/cs5536/smbus.h @@ -33,4 +33,4 @@ unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address); -#endif /* _CS5536_SMBUS_H */ +#endif /* _CS5536_SMBUS_H */

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Patch set updated for coreboot: 95d4d9c mainboard: Remove duplicate header include
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6556 -gerrit commit 95d4d9c2ae50b3728f14b4a39d1c22732b18826b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:10:27 2014 +1000 mainboard: Remove duplicate header include Change-Id: I574b210b86e220aaa8bffe8fdce6ee2b76cac247 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 1 - src/mainboard/amd/db800/romstage.c | 1 - src/mainboard/amd/norwich/romstage.c | 1 - src/mainboard/artecgroup/dbe61/romstage.c | 1 - src/mainboard/bachmann/ot200/romstage.c | 1 - src/mainboard/digitallogic/msm800sev/romstage.c | 1 - src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 1 - src/mainboard/lippert/literunner-lx/romstage.c | 1 - src/mainboard/lippert/roadrunner-lx/romstage.c | 1 - src/mainboard/lippert/spacerunner-lx/romstage.c | 1 - src/mainboard/pcengines/alix1c/romstage.c | 1 - src/mainboard/pcengines/alix2d/romstage.c | 1 - src/mainboard/traverse/geos/romstage.c | 1 - src/mainboard/winent/pl6064/romstage.c | 1 - 15 files changed, 15 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index c6a086c..55ea4ec 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index dd6963d..fac4086 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9a4844b..35bc121 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 8023507..0e2fc4c 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 1bbbbd6..ba6cc22 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 15bdd05..56667ca 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -9,7 +9,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 1bf1d69..86eab81 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 3b91ae3..40704d8 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index da2201a..a05b56c 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 3062858..116fb0d 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 5601026..1deb8ac 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index dfb302a..c17b7d0 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 8f0fdb1..01ee2c0 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 512573c..c0bd211 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index e50fbb3..ac42315 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h>

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Patch set updated for coreboot: 39a797f southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6554 -gerrit commit 39a797f8995b4534c35690170b5b99176a8b19f2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 20:22:22 2014 +1000 southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol On some boards the SMBus is hardwired and so we need to override cs5536_enable_smbus() with a dummy function in the board support. Thus we make cs5536_enable_smbus() a weak symbol. Change-Id: Iada97edf0591556b64eb8b63752379fdf0366ece Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/southbridge/amd/cs5536/cs5536.h | 6 ++++++ src/southbridge/amd/cs5536/early_setup.c | 1 + src/southbridge/amd/cs5536/early_smbus.c | 4 +--- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 204f0bd..080553b 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 18453ac..07bf77e 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX.2D has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index b722560..530ab2e 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -451,4 +451,10 @@ void chipsetinit(void); #endif #endif +/** + * Note: Some boards do not have SMBus and are hard-wired, so we leave this + * symbol weak as to be able to override it in 'romstage.c' of board support. + */ +void cs5536_enable_smbus(void) __attribute__((weak)); + #endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..d9a042a 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -22,6 +22,7 @@ * This file implements the initialization sequence documented in section 4.2 of * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. */ +#include "cs5536.h" /** * @brief Setup PCI IDSEL for CS5536 diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c index d1483b1..853f837 100644 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ b/src/southbridge/amd/cs5536/early_smbus.c @@ -21,16 +21,14 @@ #include "smbus.h" /* initialization for SMBus Controller */ -static void cs5536_enable_smbus(void) +void cs5536_enable_smbus(void) { - /* Set SCL freq and enable SMB controller */ /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2); /* Setup SMBus host controller address to 0xEF */ outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD); - } static inline int smbus_read_byte(unsigned device, unsigned address)

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Patch set updated for coreboot: 90f025b southbridge/amd/cs5536: Use prototype for cs5536_early_setup()
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6555 -gerrit commit 90f025b7b6ea9df8fd2f9269222779c4709bd1a1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:03:38 2014 +1000 southbridge/amd/cs5536: Use prototype for cs5536_early_setup() Use a prototype for cs5536_early_setup() over using #include .c and fix mainboard's to match. Change-Id: I88d6d4abbd825d8d77dadf1755226f14f99a9b63 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 2 +- src/mainboard/amd/db800/romstage.c | 2 +- src/mainboard/amd/norwich/romstage.c | 2 +- src/mainboard/amd/rumba/romstage.c | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/bachmann/ot200/romstage.c | 2 +- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 2 +- src/mainboard/iei/pm-lx-800-r11/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/traverse/geos/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 2 +- src/mainboard/wyse/s50/romstage.c | 2 +- src/southbridge/amd/cs5536/Makefile.inc | 3 ++- src/southbridge/amd/cs5536/cs5536.h | 1 + src/southbridge/amd/cs5536/early_setup.c | 2 +- 22 files changed, 22 insertions(+), 21 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index f80ef95..c6a086c 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 564380e..dd6963d 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9322508..9a4844b 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index c5a3fc3..f57a73e 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -11,7 +11,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 7276b30..8023507 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -32,7 +32,7 @@ #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 39385c7..1bbbbd6 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 986e918..15bdd05 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -12,7 +12,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index a75691c..1bf1d69 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index bf34e9a..08ecdd3 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index b34bce4..5b02305 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -32,7 +32,6 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 063721b..3b91ae3 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 174620a..da2201a 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 2642373..3062858 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9d5539e..5601026 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 080553b..dfb302a 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -38,7 +38,7 @@ /* The ALIX1.C has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 07bf77e..8f0fdb1 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -38,7 +38,7 @@ /* The ALIX.2D has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> /* The part is a Hynix hy5du121622ctp-d43. * diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 36d55a7..512573c 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -32,7 +32,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6a38355..e50fbb3 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 9e5dd53..d3159e8 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> static inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc5..ae530f9 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -21,4 +21,5 @@ ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c \ No newline at end of file +romstage-y += smbus.c +romstage-y += early_setup.c diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 530ab2e..d4cf326 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -446,6 +446,7 @@ #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); +void cs5536_early_setup(void); #else void chipsetinit(void); #endif diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index df66bee..23b839d 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -253,7 +253,7 @@ void cs5536_setup_onchipuart(int uart) * and we don't want to hang on serial, so they are * commented out */ -static void cs5536_early_setup(void) +void cs5536_early_setup(void) { msr_t msr;

1 0

New patch to review for coreboot: c605966 mainboard: Remove duplicate header include
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6556 -gerrit commit c6059668b0fc7b8a4ae7c462b3bf105e754ef13e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:10:27 2014 +1000 mainboard: Remove duplicate header include Change-Id: I574b210b86e220aaa8bffe8fdce6ee2b76cac247 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 1 - src/mainboard/amd/db800/romstage.c | 1 - src/mainboard/amd/norwich/romstage.c | 1 - src/mainboard/artecgroup/dbe61/romstage.c | 1 - src/mainboard/bachmann/ot200/romstage.c | 1 - src/mainboard/digitallogic/msm800sev/romstage.c | 1 - src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 1 - src/mainboard/lippert/literunner-lx/romstage.c | 1 - src/mainboard/lippert/roadrunner-lx/romstage.c | 1 - src/mainboard/lippert/spacerunner-lx/romstage.c | 1 - src/mainboard/pcengines/alix1c/romstage.c | 1 - src/mainboard/pcengines/alix2d/romstage.c | 1 - src/mainboard/traverse/geos/romstage.c | 1 - src/mainboard/winent/pl6064/romstage.c | 1 - 15 files changed, 15 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index c6a086c..55ea4ec 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index dd6963d..fac4086 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9a4844b..35bc121 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 8023507..0e2fc4c 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 1bbbbd6..ba6cc22 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 15bdd05..56667ca 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -9,7 +9,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 1bf1d69..86eab81 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 3b91ae3..40704d8 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index da2201a..a05b56c 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 3062858..116fb0d 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 5601026..1deb8ac 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index dfb302a..c17b7d0 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 8f0fdb1..01ee2c0 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 512573c..c0bd211 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h> diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index e50fbb3..ac42315 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include <southbridge/amd/cs5536/cs5536.h>

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Patch set updated for coreboot: ffa62f0 southbridge/amd/cs5536: Use prototype for cs5536_early_setup()
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6555 -gerrit commit ffa62f0dee109895b85bee72d2a34cbf0d63a214 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:03:38 2014 +1000 southbridge/amd/cs5536: Use prototype for cs5536_early_setup() Use a prototype for cs5536_early_setup() over using #include .c and fix mainboard's to match. Change-Id: I88d6d4abbd825d8d77dadf1755226f14f99a9b63 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 2 +- src/mainboard/amd/db800/romstage.c | 2 +- src/mainboard/amd/norwich/romstage.c | 2 +- src/mainboard/amd/rumba/romstage.c | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/bachmann/ot200/romstage.c | 2 +- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 2 +- src/mainboard/iei/pm-lx-800-r11/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/traverse/geos/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 2 +- src/mainboard/wyse/s50/romstage.c | 2 +- src/southbridge/amd/cs5536/Makefile.inc | 3 ++- src/southbridge/amd/cs5536/cs5536.h | 1 + src/southbridge/amd/cs5536/early_setup.c | 2 +- 22 files changed, 22 insertions(+), 21 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index f80ef95..c6a086c 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 564380e..dd6963d 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9322508..9a4844b 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index c5a3fc3..f57a73e 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -11,7 +11,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 7276b30..8023507 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -32,7 +32,7 @@ #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 39385c7..1bbbbd6 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 986e918..15bdd05 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -12,7 +12,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index a75691c..1bf1d69 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index bf34e9a..08ecdd3 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index b34bce4..5b02305 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -32,7 +32,6 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 063721b..3b91ae3 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 174620a..da2201a 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 2642373..3062858 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9d5539e..5601026 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 080553b..dfb302a 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -38,7 +38,7 @@ /* The ALIX1.C has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 07bf77e..8f0fdb1 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -38,7 +38,7 @@ /* The ALIX.2D has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> /* The part is a Hynix hy5du121622ctp-d43. * diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 36d55a7..512573c 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -32,7 +32,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6a38355..e50fbb3 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 9e5dd53..d3159e8 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> static inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc5..ae530f9 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -21,4 +21,5 @@ ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c \ No newline at end of file +romstage-y += smbus.c +romstage-y += early_setup.c diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index faceec4..22ac2e1 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -446,6 +446,7 @@ #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); +void cs5536_early_setup(void); #else void chipsetinit(void); #endif diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index d9a042a..38cce1f 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -249,7 +249,7 @@ void cs5536_setup_onchipuart(int uart) * and we don't want to hang on serial, so they are * commented out */ -static void cs5536_early_setup(void) +void cs5536_early_setup(void) { msr_t msr;

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New patch to review for coreboot: cc9450c southbridge/amd/cs5536: Use prototype for cs5536_early_setup()
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6555 -gerrit commit cc9450cf94b282e3da2e8ec104747e32963f0145 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 21:03:38 2014 +1000 southbridge/amd/cs5536: Use prototype for cs5536_early_setup() Use a prototype for cs5536_early_setup() over using #include .c and fix mainboard's to match. Change-Id: I88d6d4abbd825d8d77dadf1755226f14f99a9b63 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 2 +- src/mainboard/amd/db800/romstage.c | 2 +- src/mainboard/amd/norwich/romstage.c | 2 +- src/mainboard/amd/rumba/romstage.c | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/bachmann/ot200/romstage.c | 2 +- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 2 +- src/mainboard/iei/pm-lx-800-r11/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/traverse/geos/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 2 +- src/mainboard/wyse/s50/romstage.c | 2 +- src/southbridge/amd/cs5536/cs5536.h | 1 + src/southbridge/amd/cs5536/early_setup.c | 2 +- 21 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index f80ef95..c6a086c 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 564380e..dd6963d 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9322508..9a4844b 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index c5a3fc3..f57a73e 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -11,7 +11,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 7276b30..8023507 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -32,7 +32,7 @@ #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 39385c7..1bbbbd6 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 986e918..15bdd05 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -12,7 +12,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index a75691c..1bf1d69 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -31,7 +31,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index bf34e9a..08ecdd3 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index b34bce4..5b02305 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -32,7 +32,6 @@ #include <cpu/amd/lxdef.h> #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> -#include <southbridge/amd/cs5536/early_setup.c> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <northbridge/amd/lx/raminit.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 063721b..3b91ae3 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 174620a..da2201a 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 2642373..3062858 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -34,7 +34,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9d5539e..5601026 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -34,7 +34,7 @@ #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 080553b..dfb302a 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -38,7 +38,7 @@ /* The ALIX1.C has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 07bf77e..8f0fdb1 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -38,7 +38,7 @@ /* The ALIX.2D has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> /* The part is a Hynix hy5du121622ctp-d43. * diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 36d55a7..512573c 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -32,7 +32,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6a38355..e50fbb3 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 9e5dd53..d3159e8 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" -#include "southbridge/amd/cs5536/early_setup.c" +#include <southbridge/amd/cs5536/cs5536.h> static inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index faceec4..22ac2e1 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -446,6 +446,7 @@ #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); +void cs5536_early_setup(void); #else void chipsetinit(void); #endif diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index d9a042a..38cce1f 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -249,7 +249,7 @@ void cs5536_setup_onchipuart(int uart) * and we don't want to hang on serial, so they are * commented out */ -static void cs5536_early_setup(void) +void cs5536_early_setup(void) { msr_t msr;

1 0

Patch set updated for coreboot: 6609fe8 southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6554 -gerrit commit 6609fe81eac919fb427ac1913e2cf8036b7d31c6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 20:22:22 2014 +1000 southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol On some boards the SMBus is hardwired and so we need to override cs5536_enable_smbus() with a dummy function in the board support. Thus we make cs5536_enable_smbus() a weak symbol. Change-Id: Iada97edf0591556b64eb8b63752379fdf0366ece Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/southbridge/amd/cs5536/cs5536.h | 6 ++++++ src/southbridge/amd/cs5536/early_setup.c | 1 + src/southbridge/amd/cs5536/early_smbus.c | 4 +--- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 204f0bd..080553b 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 18453ac..07bf77e 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX.2D has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index c193d9d..faceec4 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -451,4 +451,10 @@ void chipsetinit(void); #endif #endif +/** + * Note: Some boards do not have SMBus and are hard-wired, so we leave this + * symbol weak as to be able to override it in 'romstage.c' of board support. + */ +void cs5536_enable_smbus(void) __attribute__((weak)); + #endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..d9a042a 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -22,6 +22,7 @@ * This file implements the initialization sequence documented in section 4.2 of * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. */ +#include "cs5536.h" /** * @brief Setup PCI IDSEL for CS5536 diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c index d1483b1..853f837 100644 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ b/src/southbridge/amd/cs5536/early_smbus.c @@ -21,16 +21,14 @@ #include "smbus.h" /* initialization for SMBus Controller */ -static void cs5536_enable_smbus(void) +void cs5536_enable_smbus(void) { - /* Set SCL freq and enable SMB controller */ /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2); /* Setup SMBus host controller address to 0xEF */ outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD); - } static inline int smbus_read_byte(unsigned device, unsigned address)

1 0

New patch to review for coreboot: f385f4d southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6554 -gerrit commit f385f4db5c6e75e8f7e41f071641e4c0616512cc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 20:22:22 2014 +1000 southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol On some boards the SMBus is hardwired and so we need to override cs5536_enable_smbus() with a dummy function in the board support. Thus we make cs5536_enable_smbus() a weak symbol. Change-Id: Iada97edf0591556b64eb8b63752379fdf0366ece Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cs5536/cs5536.h | 6 ++++++ src/southbridge/amd/cs5536/early_setup.c | 1 + src/southbridge/amd/cs5536/early_smbus.c | 4 +--- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index c193d9d..faceec4 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -451,4 +451,10 @@ void chipsetinit(void); #endif #endif +/** + * Note: Some boards do not have SMBus and are hard-wired, so we leave this + * symbol weak as to be able to override it in 'romstage.c' of board support. + */ +void cs5536_enable_smbus(void) __attribute__((weak)); + #endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..d9a042a 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -22,6 +22,7 @@ * This file implements the initialization sequence documented in section 4.2 of * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. */ +#include "cs5536.h" /** * @brief Setup PCI IDSEL for CS5536 diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c index d1483b1..853f837 100644 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ b/src/southbridge/amd/cs5536/early_smbus.c @@ -21,16 +21,14 @@ #include "smbus.h" /* initialization for SMBus Controller */ -static void cs5536_enable_smbus(void) +void cs5536_enable_smbus(void) { - /* Set SCL freq and enable SMB controller */ /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2); /* Setup SMBus host controller address to 0xEF */ outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD); - } static inline int smbus_read_byte(unsigned device, unsigned address)

1 0

Patch set updated for coreboot: 934c50b superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit 934c50b626e20b43ae72b73d9103f99b064591ce Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/devicetree.cb | 2 +- src/mainboard/amd/dinar/romstage.c | 10 +++------ src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 31 +++++++++++++-------------- 6 files changed, 26 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459..b71c5a5 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd4..7a59fd2 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -85,7 +85,7 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end - end #SIO SMSC307 + end #SIO SMSC SCH4037 end #LPC device pci 14.4 on end # PCI bridge, 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..8cc3d9a 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,12 +33,12 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -50,11 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sch4037_early_init(0x2e); - /* Detect SMSC SIO1036 LPC Debug Card status */ - if (detect_sio1036_chip(0x4E)) { - /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); - } + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..fa52a1a 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <arch/io.h> +#include <stdint.h> + +void sio1036_enable_serial(device_t dev, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..5f10230 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,50 +20,49 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } +/* Detect SMSC SIO1036 LPC Debug Card status */ static u8 detect_sio1036_chip(unsigned port) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + device_t dev = PNP_DEV(port, SIO1036_SP1); unsigned data; + sio1036_enter_conf_state (dev); data = pnp_read_config (dev, 0x0D); sio1036_exit_conf_state(dev); - /* detect smsc sio1036 chip */ + + /* Detect SMSC SIO1036 chip */ if (data == 0x82) { /* Found SMSC SIO1036 chip */ return 0; } else { - return -1; + return 1; }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_enable_serial(device_t dev, u16 iobase) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + unsigned port = dev >> 8; - if (detect_sio1036_chip(port) != 0) { - /* Not found SMSC SIO1036 */ + if (detect_sio1036_chip(port) != 0) return; - } + sio1036_enter_conf_state (dev); /* Enable SMSC UART 0 */ @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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coreboot-gerrit August 2014