coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 4e9f5e3 superio/smsc/sio1036: Clean up RAMstage superio.c component
by gerrit＠coreboot.org 09 Aug '14

09 Aug '14

the following patch was just integrated into master: commit 4e9f5e3f36ec5b497a74e5da0c202c1b62f9e620 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:45:13 2014 +1000 superio/smsc/sio1036: Clean up RAMstage superio.c component Remove spurious includes, unused variables and some wasted new lines. Re-organise things to be consistent with other superio's. Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6465 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6465 for details. -gerrit

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Patch set updated for coreboot: 8512e12 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit 8512e12c9f8b236e9e1e2b4a99a8cfde14aaa61f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/devicetree.cb | 2 +- src/mainboard/amd/dinar/romstage.c | 10 +++------ src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 31 +++++++++++++-------------- 6 files changed, 26 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459..b71c5a5 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd4..7a59fd2 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -85,7 +85,7 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end - end #SIO SMSC307 + end #SIO SMSC SCH4037 end #LPC device pci 14.4 on end # PCI bridge, 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..8cc3d9a 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,12 +33,12 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -50,11 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sch4037_early_init(0x2e); - /* Detect SMSC SIO1036 LPC Debug Card status */ - if (detect_sio1036_chip(0x4E)) { - /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); - } + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..fa52a1a 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <arch/io.h> +#include <stdint.h> + +void sio1036_enable_serial(device_t dev, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..5f10230 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,50 +20,49 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } +/* Detect SMSC SIO1036 LPC Debug Card status */ static u8 detect_sio1036_chip(unsigned port) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + device_t dev = PNP_DEV(port, SIO1036_SP1); unsigned data; + sio1036_enter_conf_state (dev); data = pnp_read_config (dev, 0x0D); sio1036_exit_conf_state(dev); - /* detect smsc sio1036 chip */ + + /* Detect SMSC SIO1036 chip */ if (data == 0x82) { /* Found SMSC SIO1036 chip */ return 0; } else { - return -1; + return 1; }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_enable_serial(device_t dev, u16 iobase) { - device_t dev; - dev = PNP_DEV (port, SIO1036_SP1); + unsigned port = dev >> 8; - if (detect_sio1036_chip(port) != 0) { - /* Not found SMSC SIO1036 */ + if (detect_sio1036_chip(port) != 0) return; - } + sio1036_enter_conf_state (dev); /* Enable SMSC UART 0 */ @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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New patch to review for coreboot: 4323675 util/nvramtool/cli/nvramtool.c: Add newline to error message
by Paul Menzel 09 Aug '14

09 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6553 -gerrit commit 43236759b3cda1ad3190e5addc9dc92bf91854dd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Aug 9 09:33:59 2014 +0200 util/nvramtool/cli/nvramtool.c: Add newline to error message Wanting to write a non-existent CMOS parameter an error messages is shown without a newline at the end and nvramtool exits. user@lenovo_x60t$ sudo util/nvramtool/nvramtool -w touchpad=Enlable nvramtool: CMOS parameter touchpad not found.user@lenovo_x60t$ So add a newline at the end to properly format the output. user@lenovo_x60t$ sudo util/nvramtool/nvramtool -w touchpad=Enlable nvramtool: CMOS parameter touchpad not found. user@lenovo_x60t$ Change-Id: Ied431dbc9f94d82e1f4716cfb89ea3d6cf513703 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/nvramtool/cli/nvramtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index d5acc58..f83825e 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -615,7 +615,7 @@ static void set_one_param(const char name[], const char value[]) unsigned long long n; if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL) { - fprintf(stderr, "%s: CMOS parameter %s not found.", prog_name, + fprintf(stderr, "%s: CMOS parameter %s not found.\n", prog_name, name); exit(1); }

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New patch to review for coreboot: 350d0b9 mainboard/pcengines/alix1c: Collect and sort includes
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6552 -gerrit commit 350d0b9c1a5cb3053e761860a02f70499ecb7307 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 16:09:28 2014 +1000 mainboard/pcengines/alix1c: Collect and sort includes Change-Id: I1ad36bede57cf5580693287f00b78ba3e9aedee8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/pcengines/alix1c/irq_tables.c | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 40 +++++++++++++++-------------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c index 9ee8a07..df8cc53 100644 --- a/src/mainboard/pcengines/alix1c/irq_tables.c +++ b/src/mainboard/pcengines/alix1c/irq_tables.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <arch/pirq_routing.h> #include <console/console.h> -#include <arch/io.h> #include "southbridge/amd/cs5536/cs5536.h" /* Platform IRQs */ diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 204f0bd..2c4912a 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -17,31 +17,39 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/amd/car.h> +#include <cpu/amd/lxdef.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> #include <stdint.h> #include <stdlib.h> #include <spd.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" -#include <cpu/amd/lxdef.h> -#include <cpu/amd/car.h> + +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" +/* FIXME: .c includes */ +#include "southbridge/amd/cs5536/early_setup.c" +#include "northbridge/amd/lx/pll_reset.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" + + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ static void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> - /* The part is a Hynix hy5du121622ctp-d43. * * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 @@ -101,12 +109,6 @@ int spd_read_byte(unsigned int device, unsigned int address) return spdbytes[address]; } -#include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/geode_lx/cpureginit.c" -#include "cpu/amd/geode_lx/syspreinit.c" -#include "cpu/amd/geode_lx/msrinit.c" - void main(unsigned long bist) { static const struct mem_controller memctrl[] = {

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New patch to review for coreboot: 62bf4c2 mainboard/pcengines/alix2d/romstage.c: Collect includes together
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6551 -gerrit commit 62bf4c29aa0a574e2c7f71e3a34db873641b8a88 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 15:57:40 2014 +1000 mainboard/pcengines/alix2d/romstage.c: Collect includes together Change-Id: Ib1cac5bdaa5a21e32e2cbe1aa29d130d303f2d3c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/pcengines/alix2d/romstage.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 18453ac..3ed2579 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -33,12 +33,20 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" +/* FIXME: .c includes */ +#include "southbridge/amd/cs5536/early_setup.c" +#include "northbridge/amd/lx/pll_reset.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" + + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX.2D has no SMBus; the setup is hard-wired. */ static void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/early_setup.c" /* The part is a Hynix hy5du121622ctp-d43. * @@ -99,12 +107,6 @@ int spd_read_byte(unsigned int device, unsigned int address) return spdbytes[address]; } -#include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/geode_lx/cpureginit.c" -#include "cpu/amd/geode_lx/syspreinit.c" -#include "cpu/amd/geode_lx/msrinit.c" - /** Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) {

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New patch to review for coreboot: e83e5ec cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6550 -gerrit commit e83e5ecf2b99391ff76b7d050a7ffc72364b9cb7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 15:51:19 2014 +1000 cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments Lets try not to play games with the Lexer with fancy ASCII art. Doxygen has a more well defined and useful syntax for annotations. Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/geode_lx/cache_as_ram.inc | 11 +++++------ src/cpu/amd/geode_lx/cpubug.c | 28 +++++++++++++--------------- src/cpu/amd/geode_lx/cpureginit.c | 14 ++------------ src/cpu/amd/geode_lx/syspreinit.c | 16 +++++++--------- 4 files changed, 27 insertions(+), 42 deletions(-) diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index db95dee..73281a3 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -25,15 +25,14 @@ #define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ + #include <cpu/amd/lxdef.h> #include <cpu/x86/post_code.h> -/*************************************************************************** -/** -/** DCacheSetup -/** -/** Setup data cache for use as RAM for a stack. + /** -/***************************************************************************/ + * DCacheSetup + * Setup data cache for use as RAM for a stack. + */ DCacheSetup: /* Save the BIST result */ movl %eax, %ebx diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index ebadec7..acf176a 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -29,15 +29,15 @@ #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -/************************************************************************** +/** * * pcideadlock * * Bugtool #465 and #609 * PCI cache deadlock - * There is also fix code in cache and PCI functions. This bug is very is pervasive. - * - **************************************************************************/ + * There is also fix code in cache and PCI functions. + * This bug is very is pervasive. + */ static void pcideadlock(void) { msr_t msr; @@ -61,17 +61,15 @@ static void pcideadlock(void) wrmsr(CPU_RCONF_E0_FF, msr); } -/****************************************************************************/ -/***/ -/** DisableMemoryReorder*/ -/***/ -/** PBZ 3659:*/ -/** The MC reordered transactions incorrectly and breaks coherency.*/ -/** Disable reordering and take a potential performance hit.*/ -/** This is safe to do here and not in MC init since there is nothing*/ -/** to maintain coherency with and the cache is not enabled yet.*/ -/***/ -/****************************************************************************/ +/** + * DisableMemoryReorder + * + * PBZ 3659: + * The MC reordered transactions incorrectly and breaks coherency. + * Disable reordering and take a potential performance hit. + * This is safe to do here and not in MC init since there is nothing + * to maintain coherency with and the cache is not enabled yet. + */ static void disablememoryreadorder(void) { msr_t msr; diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c index 30d9595..79e0a70 100644 --- a/src/cpu/amd/geode_lx/cpureginit.c +++ b/src/cpu/amd/geode_lx/cpureginit.c @@ -20,16 +20,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/************************************************************************** -;* -;* SetDelayControl -;* -;*************************************************************************/ +/* SetDelayControl */ #include "cpu/x86/msr.h" - - /** * Delay Control Settings table from AMD (MCP 0x4C00000F). */ @@ -39,8 +33,6 @@ static const msrinit_t delay_msr_table[] = { {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}}, }; - - static const struct delay_controls { u8 dimms; u8 devices; @@ -171,9 +163,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated) wrmsr(GLCP_DELAY_CONTROLS, msr); } -/* ***************************************************************************/ -/* * cpuRegInit*/ -/* ***************************************************************************/ +/* cpuRegInit */ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) { int msrnum; diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c index a6979d7..1dcaebb 100644 --- a/src/cpu/amd/geode_lx/syspreinit.c +++ b/src/cpu/amd/geode_lx/syspreinit.c @@ -20,15 +20,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* ***************************************************************************/ -/* **/ -/* * StartTimer1*/ -/* **/ -/* * Entry: none*/ -/* * Exit: Starts Timer 1 for port 61 use*/ -/* * Destroys: Al,*/ -/* **/ -/* ***************************************************************************/ +/** + * StartTimer1 + * + * Entry: none + * Exit: Starts Timer 1 for port 61 use + * Destroys: Al, + */ static void StartTimer1(void) { outb(0x56, 0x43);

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New patch to review for coreboot: fabc98e cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs
by Edward O'Callaghan 09 Aug '14

09 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6549 -gerrit commit fabc98e9701f479a8ac4093f8221b20dabe565f2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 9 15:48:51 2014 +1000 cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/geode_lx/cache_as_ram.inc | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..db95dee 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -189,24 +189,25 @@ DCacheSetupGood: call main done_cache_as_ram_main: - /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ - - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi + /* We now run over the stack-in-cache, + * copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi /* Clear the cache out to ram */ wbinvd - /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 __main: post_code(POST_PREPARE_RAMSTAGE) @@ -227,4 +228,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt -

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New patch to review for coreboot: d48f215 Move baytrail-specific config to baytrail.
by Vladimir Serbinenko 09 Aug '14

09 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6548 -gerrit commit d48f215a1ae14d983290963961071848a35c17b6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 9 07:16:10 2014 +0200 Move baytrail-specific config to baytrail. Stop poluting first screen of all boards. Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 17 ----------------- src/soc/intel/baytrail/Kconfig | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index af82353..227bc09 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -417,23 +417,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB - config HAVE_ACPI_TABLES bool help diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a6a3a44..28658dc 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -239,4 +239,21 @@ config IFD_BIN_PATH depends on !BUILD_WITH_FAKE_IFD default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" +config HAVE_REFCODE_BLOB + depends on ARCH_X86 + bool "An external reference code blob should be put into cbfs." + default n + help + The reference code blob will be placed into cbfs. + +if HAVE_REFCODE_BLOB + +config REFCODE_BLOB_FILE + string "Path and filename to reference code blob." + default "refcode.elf" + help + The path and filename to the file to be added to cbfs. + +endif # HAVE_REFCODE_BLOB + endif

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New patch to review for coreboot: 49b8347 serial: Separate the serial hardware init and the serial console init.
by Isaac Christensen 09 Aug '14

09 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6547 -gerrit commit 49b834753cf925789fd2fdfca2a04b09671a527f Author: Gabe Black <gabeblack(a)google.com> Date: Tue Dec 3 21:25:35 2013 -0800 serial: Separate the serial hardware init and the serial console init. You might want to use the serial hardware for something other than a console, or you might want to intercede in the serial stream to wrap it in another protocol. This is what you'd do to send output to GDB while using it to debug the payload. Change-Id: I2218c0dbb988dacb64e5bdaf5d92138828eff8b6 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179559 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit da9ab46d974745125fe7d8b29ce43336c3586cd5) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/drivers/serial.c | 9 +++++++++ payloads/libpayload/include/libpayload.h | 1 + payloads/libpayload/libc/console.c | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c index 92782a0..a4c1b1a 100644 --- a/payloads/libpayload/drivers/serial.c +++ b/payloads/libpayload/drivers/serial.c @@ -117,6 +117,15 @@ void serial_init(void) #ifdef CONFIG_LP_SERIAL_SET_SPEED serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); #endif +} + +void serial_console_init(void) +{ + if (!lib_sysinfo.serial) + return; + + serial_init(); + console_add_input_driver(&consin); console_add_output_driver(&consout); serial_hardware_is_present = 1; diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 29b5629..753449d 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -163,6 +163,7 @@ int keyboard_set_layout(char *country); * @{ */ void serial_init(void); +void serial_console_init(void); void serial_putchar(unsigned int c); int serial_havechar(void); int serial_getchar(void); diff --git a/payloads/libpayload/libc/console.c b/payloads/libpayload/libc/console.c index a362481..59d5bcc 100644 --- a/payloads/libpayload/libc/console.c +++ b/payloads/libpayload/libc/console.c @@ -53,7 +53,7 @@ void console_init(void) video_console_init(); #endif #ifdef CONFIG_LP_SERIAL_CONSOLE - serial_init(); + serial_console_init(); #endif #ifdef CONFIG_LP_PC_KEYBOARD keyboard_init();

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New patch to review for coreboot: ca7897a xcompile: only enforce BFD linker on x86
by Isaac Christensen 09 Aug '14

09 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6546 -gerrit commit ca7897a763e7f88a2d4c605e4216baa63f26137e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 10 10:55:26 2013 -0700 xcompile: only enforce BFD linker on x86 The ARM linker scripts work fine with the gold linker. This also requires to enhance the LINKER_SUFFIX variable with a platform suffix so that it can be different on ARMv7 and x86 Change-Id: I7d3b57991b1e40d0305be3fc4bc63d322392d98e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/168771 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 8b2f31e7b4996aeda5976d87971afe6cf56bef83) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- util/xcompile/xcompile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 01d75bf..21d8a3b 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -125,9 +125,7 @@ detect_special_flags() { testcc "$CC" "$CFLAGS -Wno-unused-but-set-variable " && CFLAGS="$CFLAGS -Wno-unused-but-set-variable " - # Use bfd linker instead of gold if available: - testcc "$CC" "$CFLAGS -fuse-ld=bfd" && - CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' + testcc "$CC" "$CFLAGS -fno-stack-protector"&& CFLAGS="$CFLAGS -fno-stack-protector" @@ -138,6 +136,9 @@ detect_special_flags() { x86) testcc "$CC" "$CFLAGS -Wa,--divide" && CFLAGS="$CFLAGS -Wa,--divide" + # Use bfd linker instead of gold if available: + testcc "$CC" "$CFLAGS -fuse-ld=bfd" && + CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' ;; esac } @@ -150,7 +151,7 @@ CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} -LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} +LD_${TARCH}:=${GCCPREFIX}ld$(eval echo \${LINKER_SUFFIX_${TARCH}}) ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy OBJDUMP_${TARCH}:=${GCCPREFIX}objdump

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coreboot-gerrit August 2014