coreboot-gerrit August 2014

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Patch merged into coreboot/master: da36bcf qemu-armv7/media.c: fix coding style
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit da36bcf0d4334695b797166b865006842a1ae7e2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Sep 9 11:20:47 2013 -0700 qemu-armv7/media.c: fix coding style Change-Id: I01a11923fc1b250afeed36acc20793fd072421ba Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/168574 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 46b5f64096c55d0d9627cb9537fc4910e1bddcd9) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6520 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6520 for details. -gerrit

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Patch merged into coreboot/master: 9dd01eb falco: Add double function reset to ALC283 verb table
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 9dd01eb416f371d3101d63a212439a9003c101b4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 28 09:53:57 2013 -0700 falco: Add double function reset to ALC283 verb table The ALC283 needs a double function reset to ensure that all settings are reset and the firmware beep is functional. Original-Change-Id: Id9ddc6f4914957f39c5f9cdfaaac354808929146 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167291 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)google.com> (cherry picked from commit c59865ac464af308baedcd69aa662f46ff3a04d3) Change-Id: Ie6f3a8179376bc97a6d22712dd965f5e0e6ec5d6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167313 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit b31d7a31b838e67a4b7f33119a3baea049d30a36) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6518 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6518 for details. -gerrit

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New patch to review for coreboot: 2d8be6c exynos5420: Make USB A-A booting work with early data cache
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6530 -gerrit commit 2d8be6ce43689bb551cbdf19715413de9f1d7004 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Aug 21 17:33:31 2013 -0700 exynos5420: Make USB A-A booting work with early data cache Apparently the IROM doesn't like data caches... the recently added dcache-in-bootblock makes A-A booting fail, and flushes/invalidations alone don't seem to fix it. It's pretty fast anyway, so we just disable the cache again for the duration of the IROM call. Also removes a superfluous invalidation line from the bootblock code... dcache_mmu_enable/disable already take care of that. Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66602 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f) exynos5: Implement booting from SDMMC media This patch augments the alternative CBFS media source implementation for Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as an SD or uSD card reader, if available). It also moves MMC initialization for the Snow, Pit and Kirby boards from romstage to ramstage (mainboard_init) to prevent it from interfering with the IROM during SDMMC boot. Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66154 (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc) snow and pit: turn on FET4 (for SD card) at bootup Explictly enable FET4 on Snow and Pit. Historically we haven't needed to do this because: * On snow there's a bypass around FET4 which effectively eliminates it. Even if we don't turn on FET4 the SD card is still powered. Turning on FET4 doesn't hurt though and is technically correct. * On pit the EC turns on FET4 on cold bootup. On pit we run into a problem if the kernel turns off FET4 like in <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a software reset or warm reset. In this case the EC won't know to turn it back on. This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c Reviewed-on: https://gerrit.chromium.org/gerrit/66786 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646) Squashed three commits for alternate cbfs SD support. Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5250/alternate_cbfs.c | 72 ++++++++++++++++++++++++-- src/cpu/samsung/exynos5250/alternate_cbfs.h | 6 +++ src/cpu/samsung/exynos5250/power.h | 3 +- src/cpu/samsung/exynos5420/alternate_cbfs.c | 79 +++++++++++++++++++++++++++-- src/cpu/samsung/exynos5420/alternate_cbfs.h | 6 +++ src/cpu/samsung/exynos5420/bootblock.c | 1 - src/cpu/samsung/exynos5420/power.h | 3 +- src/mainboard/google/pit/mainboard.c | 22 ++++++++ src/mainboard/google/pit/romstage.c | 15 ------ src/mainboard/google/snow/mainboard.c | 30 +++++++++++ src/mainboard/google/snow/romstage.c | 19 ------- 11 files changed, 209 insertions(+), 47 deletions(-) diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c index 49c9d4c..59843fb 100644 --- a/src/cpu/samsung/exynos5250/alternate_cbfs.c +++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c @@ -24,6 +24,8 @@ #include <string.h> #include <console/console.h> #include "alternate_cbfs.h" +#include "cpu.h" +#include "power.h" #include "spi.h" /* This allows USB A-A firmware upload from a compatible host in four parts: @@ -53,7 +55,7 @@ static int usb_cbfs_open(struct cbfs_media *media) return 0; if (!irom_load_usb()) { - printk(BIOS_ERR, "Unable to load CBFS image via USB!\n"); + printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n"); return -1; } @@ -70,6 +72,45 @@ static int usb_cbfs_open(struct cbfs_media *media) return 0; } +/* + * SDMMC works very similar to USB A-A: we copy the CBFS image into memory + * and read it from there. While SDMMC would also allow direct block by block + * on-demand reading, we might run into problems if we call back into the IROM + * in very late boot stages (e.g. after initializing/changing MMC clocks)... so + * this seems like a safer approach. It also makes it easy to pass our image + * down to payloads. + */ +static int sdmmc_cbfs_open(struct cbfs_media *media) +{ +#ifdef __PRE_RAM__ + /* + * In the bootblock, we just copy the small part that fits in the buffer + * and hope that it's enough (since the romstage is currently always the + * first component in the image, this should work out). In the romstage, + * we copy until our buffer is full (currently 12M) to avoid the pain of + * figuring out the true image size from in here. Since this is mainly a + * developer/debug boot mode, those shortcomings should be bearable. + */ + const u32 count = alternate_cbfs_size / 512; + static int first_run = 1; + int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) = + *irom_sdmmc_read_blocks_ptr; + + if (!first_run) + return 0; + + if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) { + printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n"); + return -1; + } + + printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" + " at %p\n", alternate_cbfs_buffer); + first_run = 0; +#endif + return 0; +} + static int alternate_cbfs_close(struct cbfs_media *media) { return 0; } static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest, @@ -90,6 +131,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, static void *alternate_cbfs_unmap(struct cbfs_media *media, const void *buffer) { return 0; } +static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n"); + + media->open = sdmmc_cbfs_open; + media->close = alternate_cbfs_close; + media->read = alternate_cbfs_read; + media->map = alternate_cbfs_map; + media->unmap = alternate_cbfs_unmap; + + return 0; +} + static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) { printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); @@ -108,8 +162,16 @@ int init_default_cbfs_media(struct cbfs_media *media) if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) return initialize_exynos_usb_cbfs_media(media); - /* TODO: implement SDMMC (and possibly other) boot mode */ - - return initialize_exynos_spi_cbfs_media(media, - (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE); + switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) { + case OM_STAT_SDMMC: + return initialize_exynos_sdmmc_cbfs_media(media); + case OM_STAT_SPI: + return initialize_exynos_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, + CONFIG_CBFS_CACHE_SIZE); + default: + printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n", + samsung_get_base_power()->om_stat); + return 0; + } } diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.h b/src/cpu/samsung/exynos5250/alternate_cbfs.h index a26fe61..8a87279 100644 --- a/src/cpu/samsung/exynos5250/alternate_cbfs.h +++ b/src/cpu/samsung/exynos5250/alternate_cbfs.h @@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; #define SECONDARY_BASE_BOOT_USB 0xfeed0002 u32 * const iram_secondary_base = (u32 *)0x02020018; +/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ +#define OM_STAT_SDMMC 0x4 +#define OM_STAT_EMMC 0x8 +#define OM_STAT_SPI 0x14 +#define OM_STAT_MASK 0x7f + #if defined(__BOOT_BLOCK__) /* A small space in IRAM to hold the romstage-only image */ void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h index f349e53..5483d92 100644 --- a/src/cpu/samsung/exynos5250/power.h +++ b/src/cpu/samsung/exynos5250/power.h @@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void); /* Power Management Unit register map */ struct exynos5_power { /* Add registers as and when required */ - uint8_t reserved1[0x0400]; + uint32_t om_stat; /* 0x0000 */ + uint8_t reserved1[0x03fc]; uint32_t sw_reset; /* 0x0400 */ uint8_t reserved2[0x0304]; uint32_t usb_host_phy_ctrl; /* 0x0708 */ diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c index 49c9d4c..4161303 100644 --- a/src/cpu/samsung/exynos5420/alternate_cbfs.c +++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c @@ -22,8 +22,11 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ #include <stdlib.h> #include <string.h> +#include <arch/cache.h> #include <console/console.h> #include "alternate_cbfs.h" +#include "cpu.h" +#include "power.h" #include "spi.h" /* This allows USB A-A firmware upload from a compatible host in four parts: @@ -52,10 +55,13 @@ static int usb_cbfs_open(struct cbfs_media *media) if (!first_run) return 0; + dcache_mmu_disable(); if (!irom_load_usb()) { - printk(BIOS_ERR, "Unable to load CBFS image via USB!\n"); + dcache_mmu_enable(); + printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n"); return -1; } + dcache_mmu_enable(); /* * We need to trust the host/irom to copy the image to our @@ -70,6 +76,48 @@ static int usb_cbfs_open(struct cbfs_media *media) return 0; } +/* + * SDMMC works very similar to USB A-A: we copy the CBFS image into memory + * and read it from there. While SDMMC would also allow direct block by block + * on-demand reading, we might run into problems if we call back into the IROM + * in very late boot stages (e.g. after initializing/changing MMC clocks)... so + * this seems like a safer approach. It also makes it easy to pass our image + * down to payloads. + */ +static int sdmmc_cbfs_open(struct cbfs_media *media) +{ +#ifdef __PRE_RAM__ + /* + * In the bootblock, we just copy the small part that fits in the buffer + * and hope that it's enough (since the romstage is currently always the + * first component in the image, this should work out). In the romstage, + * we copy until our buffer is full (currently 12M) to avoid the pain of + * figuring out the true image size from in here. Since this is mainly a + * developer/debug boot mode, those shortcomings should be bearable. + */ + const u32 count = alternate_cbfs_size / 512; + static int first_run = 1; + int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) = + *irom_sdmmc_read_blocks_ptr; + + if (!first_run) + return 0; + + dcache_mmu_disable(); + if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) { + dcache_mmu_enable(); + printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n"); + return -1; + } + dcache_mmu_enable(); + + printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" + " at %p\n", alternate_cbfs_buffer); + first_run = 0; +#endif + return 0; +} + static int alternate_cbfs_close(struct cbfs_media *media) { return 0; } static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest, @@ -90,6 +138,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, static void *alternate_cbfs_unmap(struct cbfs_media *media, const void *buffer) { return 0; } +static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n"); + + media->open = sdmmc_cbfs_open; + media->close = alternate_cbfs_close; + media->read = alternate_cbfs_read; + media->map = alternate_cbfs_map; + media->unmap = alternate_cbfs_unmap; + + return 0; +} + static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) { printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); @@ -108,8 +169,16 @@ int init_default_cbfs_media(struct cbfs_media *media) if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) return initialize_exynos_usb_cbfs_media(media); - /* TODO: implement SDMMC (and possibly other) boot mode */ - - return initialize_exynos_spi_cbfs_media(media, - (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE); + switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) { + case OM_STAT_SDMMC: + return initialize_exynos_sdmmc_cbfs_media(media); + case OM_STAT_SPI: + return initialize_exynos_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, + CONFIG_CBFS_CACHE_SIZE); + default: + printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n", + samsung_get_base_power()->om_stat); + return 0; + } } diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h index 4e9dff9..3bb9c76 100644 --- a/src/cpu/samsung/exynos5420/alternate_cbfs.h +++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h @@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; #define SECONDARY_BASE_BOOT_USB 0xfeed0002 u32 * const iram_secondary_base = (u32 *)0x02020018; +/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ +#define OM_STAT_SDMMC 0x4 +#define OM_STAT_EMMC 0x8 +#define OM_STAT_SPI 0x14 +#define OM_STAT_MASK 0x7f + #if defined(__BOOT_BLOCK__) /* A small space in IRAM to hold the romstage-only image */ void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index 3df51a7..1ad75ef 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -63,7 +63,6 @@ void bootblock_cpu_init(void) mmu_config_range(0, SRAM_START, DCACHE_OFF); mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); - dcache_invalidate_all(); dcache_mmu_enable(); /* For most ARM systems, we have to initialize firmware media source diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h index 665e94c..4efc84e 100644 --- a/src/cpu/samsung/exynos5420/power.h +++ b/src/cpu/samsung/exynos5420/power.h @@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void); /* Power Management Unit register map */ struct exynos5_power { /* Add registers as and when required */ - uint8_t reserved1[0x0400]; + uint32_t om_stat; /* 0x0000 */ + uint8_t reserved1[0x03fc]; uint32_t sw_reset; /* 0x0400 */ uint8_t reserved2[0x0304]; uint32_t usb_host_phy_ctrl; /* 0x0708 */ diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 3ffb824..9aa8d5c 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -330,6 +330,19 @@ static void disable_usb30_pll(void) gpio_direction_output(usb3_pll_l, 0); } +static void setup_storage(void) +{ + /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ + if (clock_set_dwmci(PERIPH_ID_SDMMC0)) + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); + exynos_pinmux_sdmmc0(); + + /* MMC2: Removable, 4 bit mode, no GPIO. */ + /* (Must be after romstage to avoid breaking SDMMC boot.) */ + clock_set_dwmci(PERIPH_ID_SDMMC2); + exynos_pinmux_sdmmc2(); +} + static void gpio_init(void) { /* Set up the I2C busses. */ @@ -370,6 +383,12 @@ static void backlight_vdd(void) tps65090_thru_ec_fet_set(1); } +static void sdmmc_vdd(void) +{ + /* Enable FET4, P3.3V_SDCARD */ + tps65090_thru_ec_fet_set(4); +} + /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { @@ -380,6 +399,7 @@ static void mainboard_init(device_t dev) void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); + setup_storage(); tmu_init(&exynos5420_tmu_info); /* Clock Gating all the unused IP's to save power */ @@ -388,6 +408,8 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); + sdmmc_vdd(); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); /* diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 319ebf9..7967a55 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -40,8 +40,6 @@ #include <drivers/maxim/max77802/max77802.h> #include <device/i2c.h> -#define MMC0_GPIO_PIN (58) - #define PMIC_I2C_BUS 4 struct pmic_write @@ -109,18 +107,6 @@ static int setup_power(int is_resume) return error; } -static void setup_storage(void) -{ - /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ - if (clock_set_dwmci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); - exynos_pinmux_sdmmc0(); - - /* MMC2: Removable, 4 bit mode, no GPIO. */ - clock_set_dwmci(PERIPH_ID_SDMMC2); - exynos_pinmux_sdmmc2(); -} - static void setup_ec(void) { /* SPI2 (EC) is slower and needs to work in half-duplex mode with @@ -270,7 +256,6 @@ void main(void) wakeup(); } - setup_storage(); setup_gpio(); setup_ec(); diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 23b7072..9fc2fe6 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -38,6 +38,8 @@ #include "exynos5250.h" +#define MMC0_GPIO_PIN (58) + /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB @@ -132,6 +134,7 @@ static void backlight_en(void) #define TPS65090_BUS 4 /* Snow-specific */ #define FET1_CTRL 0x0f +#define FET4_CTRL 0x12 #define FET6_CTRL 0x14 static void lcd_vdd(void) @@ -147,6 +150,12 @@ static void backlight_vdd(void) udelay(LCD_T5_DELAY_MS * 1000); } +static void sdmmc_vdd(void) +{ + /* Enable FET4, P3.3V_SDCARD */ + tps65090_fet_enable(TPS65090_BUS, FET4_CTRL); +} + //static struct video_info smdk5250_dp_config = { static struct video_info dp_video_info = { /* FIXME: fix video_info struct to use const for name */ @@ -179,6 +188,24 @@ static void disable_usb30_pll(void) gpio_direction_output(usb3_pll_l, 0); } +static void setup_storage(void) +{ + /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ + if (clock_set_mshci(PERIPH_ID_SDMMC0)) + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); + if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { + printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); + } + gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE); + gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X); + exynos_pinmux_sdmmc0(); + + /* MMC2: Removable, 4 bit mode, no GPIO. */ + /* (Must be after romstage to avoid breaking SDMMC boot.) */ + clock_set_mshci(PERIPH_ID_SDMMC2); + exynos_pinmux_sdmmc2(); +} + static void gpio_init(void) { /* Set up the I2C busses. */ @@ -217,6 +244,7 @@ static void mainboard_init(device_t dev) void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); + setup_storage(); i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); i2c_init(7, I2C_0_SPEED, I2C_SLAVE); @@ -229,6 +257,8 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); + sdmmc_vdd(); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 3a8b5e8..44074c5 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -42,7 +42,6 @@ #include "exynos5250.h" #define PMIC_BUS 0 -#define MMC0_GPIO_PIN (58) static void setup_power(int is_resume) { @@ -96,23 +95,6 @@ static void setup_power(int is_resume) } } -static void setup_storage(void) -{ - /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ - if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); - if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); - } - gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE); - gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X); - exynos_pinmux_sdmmc0(); - - /* MMC2: Removable, 4 bit mode, no GPIO. */ - clock_set_mshci(PERIPH_ID_SDMMC2); - exynos_pinmux_sdmmc2(); -} - static void setup_graphics(void) { exynos_pinmux_dphpd(); @@ -176,7 +158,6 @@ void main(void) wakeup(); } - setup_storage(); setup_gpio(); setup_graphics();

1 0

Patch merged into coreboot/master: 3bb40b9 chromeec: Implement full battery workaround at 6%
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 3bb40b93f857256c8eafe9529de0e572522f71f0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 16 14:22:57 2013 -0700 chromeec: Implement full battery workaround at 6% Currently the workaround for indicating a "full" battery kicks in at 3%, but this turns out to be too high for some devices. So move the workaround start point to 6% from full, or 94%. Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169549 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6521 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6521 for details. -gerrit

1 0

Patch merged into coreboot/master: 5b10fc5 Pit: remove backlight delay
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 5b10fc5242191428ecec8b7c5b9068100d95f889 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Aug 21 14:37:36 2013 -0700 Pit: remove backlight delay Change-Id: Ia2e5427fec1bfff9babb9c59a3878323277f4f4c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66555 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 2b96235123d55db3ff5ae5c2454b65de831a1c18) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6524 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6524 for details. -gerrit

1 0

Patch merged into coreboot/master: 45d2ff3 exynos5420: Implement support to boot with USB A-A firmware upload
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 45d2ff317c0c077e6f83602a81bc915aa195d3f7 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 12 18:04:06 2013 -0700 exynos5420: Implement support to boot with USB A-A firmware upload This patch ports the USB A-A firmware upload functionality from exynos5250 over to exynos5420. Essentially just like a conflictless cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes the exact same bug with SPI initialization for Pit and Kirby. Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65751 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132) exynos5: Fix trivial style nits A few curly braces on the wrong line. Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66153 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb) Squashed two related commits. Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6500 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6500 for details. -gerrit

1 0

New patch to review for coreboot: 05c9cbf southbridge/ricoh, ti: Remove trailing whitespace in debug output
by Paul Menzel 08 Aug '14

08 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6529 -gerrit commit 05c9cbfdb7f9565a33af9f0df8a3deec885e7265 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Aug 8 15:24:31 2014 +0200 southbridge/ricoh,ti: Remove trailing whitespace in debug output Change-Id: If58854c35dce83bf6db7a84a8cb441cc3e60d6d4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/ti/pci7420/cardbus.c | 4 ++-- src/southbridge/ti/pcixx12/pcixx12.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 0efcafa..ab13957 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_read_resources(device_t dev) static void rl5c476_set_resources(device_t dev) { struct resource *resource; - printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 2ab383b..64878b3 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -90,11 +90,11 @@ static void pci7420_cardbus_read_resources(device_t dev) static void pci7420_cardbus_set_resources(device_t dev) { - printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev)); } static struct device_operations ti_pci7420_ops = { diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 5e62292..abddba1 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -38,11 +38,11 @@ static void pcixx12_read_resources(device_t dev) static void pcixx12_set_resources(device_t dev) { - printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev)); } static struct device_operations ti_pcixx12_ops = {

1 0

Patch set updated for coreboot: 1dd6c06 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
by HAOUAS Elyes 08 Aug '14

08 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6310 -gerrit commit 1dd6c069c91e2cccc50fbaf1a7a061677c3c61cb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 8 09:42:37 2014 +0200 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg) raminit: here is a Dumping MCHBAR Registers: 1 DIMM with RAM at 533: https://www.dropbox.com/s/w7kkk9b7zqieu0c/dump-1X533.txt 1 DIMM with RAM at 677: https://www.dropbox.com/s/h6u1ukzn92ult3r/dump-1X667.txt 2 DIMMs with RAM at 533: https://www.dropbox.com/s/t1wkyv5bbxf0uxq/dump-2X533.txt 2 DIMMs with RAM at 677: https://www.dropbox.com/s/yi042zitsd092hb/dump-2X667.txt Change-Id: I5e890bede569176c86cb3f6d6bd735c7736e852d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 ++++ src/mainboard/nec/945g-m4/acpi/ec.asl | 49 +++++ src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 ++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 +++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++++ src/mainboard/nec/945g-m4/acpi_tables.c | 230 ++++++++++++++++++++++ src/mainboard/nec/945g-m4/board_info.txt | 7 + src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 116 +++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 43 +++++ src/mainboard/nec/945g-m4/fadt.c | 155 +++++++++++++++ src/mainboard/nec/945g-m4/irq_tables.c | 61 ++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 +++++++++++ src/mainboard/nec/945g-m4/romstage.c | 233 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 +++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 ++++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/mainboard/nec/Kconfig | 4 + src/northbridge/intel/i945/raminit.c | 10 +- 23 files changed, 2079 insertions(+), 5 deletions(-) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..e6c30a0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..d1774d4 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..e6a517e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..8c6f8c8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,7 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..9978fcf --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 off end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..f30c12d --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c new file mode 100644 index 0000000..b55f628 --- /dev/null +++ b/src/mainboard/nec/945g-m4/fadt.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 2; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..4b050fe --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..d872d95 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..aaa3069 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..9021958 --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,233 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +//#include <cpu/intel/car.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ +/* values found unsing ./inteltool -g on nec bios */ + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + +/* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + /* Enable IOAPIC */ + RCBA8(0x31ff) |= 3 << 24; + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /*./inteltool -r on vendor bios*/ + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); +// RCBA32(0x3e0e) |= (1 << 7); +// RCBA32(0x3e4e) |= (1 << 7); + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + if (bist == 0) + enable_lapic(); + ich7_enable_lpc(); + /* Set up the console */ + winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE); + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + + i945_early_initialization(); + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(boot_mode, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + /* Chipset Errata! */ + fixup_i945_errata(); + +// u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); +// printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x100000, 0x0); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +sdram_dump_mchbar_registers(); +//dump_pci_devices(); +//ram_check_nodie(0<<20,0); +//ram_check_nodie(2<<20,0); +//ram_check_nodie(1<<20,0); +// quick_ram_check(); + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); +#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */ + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + } +#endif /* CONFIG_HAVE_ACPI_RESUME */ +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..e7a922b --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig index 525121f..b8bb2d6 100644 --- a/src/mainboard/nec/Kconfig +++ b/src/mainboard/nec/Kconfig @@ -24,9 +24,13 @@ choice config BOARD_NEC_POWERMATE_2000 bool "PowerMate 2000" +config BOARD_NEC_945G_M4 + bool "945g-m4" + endchoice source "src/mainboard/nec/powermate2000/Kconfig" +source "src/mainboard/nec/945g-m4/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..100052b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -92,7 +92,7 @@ static void ram_read32(u32 offset) read32(offset); } -#if CONFIG_DEBUG_RAM_SETUP +//#if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void) { int i; @@ -104,14 +104,14 @@ void sdram_dump_mchbar_registers(void) printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i)); } } -#endif +//#endif static int memclk(void) { int offset = 0; -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM +//#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM offset++; -#endif +//#endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; case 2: return 533; @@ -2264,7 +2264,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */

1 0

Patch merged into coreboot/master: 782ac36 lenovo/x230: Enable wake on LID and Fn key.
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 782ac36cfac8be208f0d1221f6586375e1b8c574 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:00:20 2014 +0200 lenovo/x230: Enable wake on LID and Fn key. Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6526 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6526 for details. -gerrit

1 0

Patch set updated for coreboot: 0071760 Intel: Add common header file for CAR setup
by Edward O'Callaghan 08 Aug '14

08 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5872 -gerrit commit 0071760a5e6d98b4373f852d3021a4cdbf9baf72 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 17:38:23 2014 +1000 Intel: Add common header file for CAR setup When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/intel/car.h | 7 +++++++ src/mainboard/a-trend/atc-6220/romstage.c | 1 + src/mainboard/a-trend/atc-6240/romstage.c | 1 + src/mainboard/aaeon/pfm-540i_revb/romstage.c | 1 + src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 + src/mainboard/advantech/pcm-5820/romstage.c | 1 + src/mainboard/amd/db800/romstage.c | 1 + src/mainboard/amd/norwich/romstage.c | 1 + src/mainboard/amd/rumba/romstage.c | 1 + src/mainboard/aopen/dxplplusu/romstage.c | 1 + src/mainboard/artecgroup/dbe61/romstage.c | 1 + src/mainboard/asi/mb_5blgp/romstage.c | 1 + src/mainboard/asi/mb_5blmp/romstage.c | 1 + src/mainboard/asus/dsbf/romstage.c | 1 + src/mainboard/asus/mew-am/romstage.c | 1 + src/mainboard/asus/mew-vm/romstage.c | 1 + src/mainboard/asus/p2b-d/romstage.c | 1 + src/mainboard/asus/p2b-ds/romstage.c | 1 + src/mainboard/asus/p2b-f/romstage.c | 1 + src/mainboard/asus/p2b-ls/romstage.c | 1 + src/mainboard/asus/p2b/romstage.c | 1 + src/mainboard/asus/p3b-f/romstage.c | 1 + src/mainboard/axus/tc320/romstage.c | 1 + src/mainboard/azza/pt-6ibd/romstage.c | 1 + src/mainboard/bachmann/ot200/romstage.c | 1 + src/mainboard/bcom/winnet100/romstage.c | 1 + src/mainboard/bcom/winnetp680/romstage.c | 1 + src/mainboard/biostar/m6tba/romstage.c | 1 + src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 1 + src/mainboard/digitallogic/adl855pc/romstage.c | 1 + src/mainboard/digitallogic/msm586seg/romstage.c | 1 + src/mainboard/digitallogic/msm800sev/romstage.c | 1 + src/mainboard/dmp/vortex86ex/romstage.c | 1 + src/mainboard/eaglelion/5bcm/romstage.c | 1 + src/mainboard/ecs/p6iwp-fe/romstage.c | 1 + src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 1 + src/mainboard/getac/p470/romstage.c | 1 + src/mainboard/gigabyte/ga-6bxc/romstage.c | 1 + src/mainboard/gigabyte/ga-6bxe/romstage.c | 1 + src/mainboard/google/butterfly/romstage.c | 1 + src/mainboard/google/link/romstage.c | 1 + src/mainboard/google/parrot/romstage.c | 1 + src/mainboard/google/stout/romstage.c | 1 + src/mainboard/hp/e_vectra_p2706t/romstage.c | 1 + src/mainboard/ibase/mb899/romstage.c | 1 + src/mainboard/iei/juki-511p/romstage.c | 1 + src/mainboard/iei/nova4899r/romstage.c | 1 + src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 1 + src/mainboard/iei/pm-lx-800-r11/romstage.c | 1 + src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 + src/mainboard/intel/d810e2cb/romstage.c | 1 + src/mainboard/intel/d945gclf/romstage.c | 1 + src/mainboard/intel/eagleheights/romstage.c | 1 + src/mainboard/intel/emeraldlake2/romstage.c | 1 + src/mainboard/intel/jarrell/romstage.c | 1 + src/mainboard/intel/mtarvon/romstage.c | 1 + src/mainboard/intel/truxton/romstage.c | 1 + src/mainboard/intel/xe7501devkit/romstage.c | 1 + src/mainboard/iwave/iWRainbowG6/romstage.c | 1 + src/mainboard/jetway/j7f2/romstage.c | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 1 + src/mainboard/kontron/ktqm77/romstage.c | 1 + src/mainboard/lanner/em8510/romstage.c | 1 + src/mainboard/lenovo/t520/romstage.c | 1 + src/mainboard/lenovo/t530/romstage.c | 1 + src/mainboard/lenovo/t60/romstage.c | 1 + src/mainboard/lenovo/x201/romstage.c | 1 + src/mainboard/lenovo/x230/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 1 + src/mainboard/lippert/frontrunner/romstage.c | 1 + src/mainboard/lippert/hurricane-lx/romstage.c | 1 + src/mainboard/lippert/literunner-lx/romstage.c | 1 + src/mainboard/lippert/roadrunner-lx/romstage.c | 1 + src/mainboard/lippert/spacerunner-lx/romstage.c | 1 + src/mainboard/mitac/6513wu/romstage.c | 1 + src/mainboard/msi/ms6119/romstage.c | 1 + src/mainboard/msi/ms6147/romstage.c | 1 + src/mainboard/msi/ms6156/romstage.c | 1 + src/mainboard/msi/ms6178/romstage.c | 1 + src/mainboard/nec/powermate2000/romstage.c | 1 + src/mainboard/nokia/ip530/romstage.c | 1 + src/mainboard/packardbell/ms2290/romstage.c | 1 + src/mainboard/pcengines/alix1c/romstage.c | 1 + src/mainboard/pcengines/alix2d/romstage.c | 1 + src/mainboard/rca/rm4100/romstage.c | 1 + src/mainboard/roda/rk886ex/romstage.c | 1 + src/mainboard/roda/rk9/romstage.c | 1 + src/mainboard/samsung/lumpy/romstage.c | 1 + src/mainboard/samsung/stumpy/romstage.c | 1 + src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 + src/mainboard/supermicro/x6dai_g/romstage.c | 1 + src/mainboard/supermicro/x6dhe_g/romstage.c | 1 + src/mainboard/supermicro/x6dhe_g2/romstage.c | 1 + src/mainboard/supermicro/x6dhr_ig/romstage.c | 1 + src/mainboard/supermicro/x6dhr_ig2/romstage.c | 1 + src/mainboard/supermicro/x7db8/romstage.c | 1 + src/mainboard/technologic/ts5300/romstage.c | 1 + src/mainboard/televideo/tc7020/romstage.c | 1 + src/mainboard/thomson/ip1000/romstage.c | 1 + src/mainboard/traverse/geos/romstage.c | 1 + src/mainboard/tyan/s1846/romstage.c | 1 + src/mainboard/tyan/s2735/romstage.c | 1 + src/mainboard/via/epia-cn/romstage.c | 1 + src/mainboard/via/epia-m/romstage.c | 1 + src/mainboard/via/epia-m700/romstage.c | 1 + src/mainboard/via/epia-m850/romstage.c | 1 + src/mainboard/via/epia-n/romstage.c | 1 + src/mainboard/via/epia/romstage.c | 1 + src/mainboard/via/pc2500e/romstage.c | 1 + src/mainboard/via/vt8454c/romstage.c | 1 + src/mainboard/winent/pl6064/romstage.c | 1 + src/mainboard/wyse/s50/romstage.c | 1 + 113 files changed, 119 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/intel/car.h b/src/include/cpu/intel/car.h new file mode 100644 index 0000000..dc89ffc --- /dev/null +++ b/src/include/cpu/intel/car.h @@ -0,0 +1,7 @@ +#ifndef _CPU_INTEL_CAR_H +#define _CPU_INTEL_CAR_H + +/* std signature of entry-point to romstage.c */ +void main(unsigned long bist); + +#endif /* _CPU_INTEL_CAR_H */ diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 22d3270..3c3f9eb 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -42,6 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 41d5d2a..a153730 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index f80ef95..7f78dce 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -54,6 +54,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 510c8ce..a17e68f 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -43,6 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index b710aad..51a713c 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -30,6 +30,7 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 564380e..f645812 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -49,6 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 9322508..2daef93 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -45,6 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index c5a3fc3..9158aad 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -31,6 +31,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = { diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 94546b1..7ef8a47 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -39,6 +39,7 @@ int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 7276b30..23e537f 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -57,6 +57,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index d661387..c7f3090 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -30,6 +30,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index e8befe4..6c18d8f 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -31,6 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index e013371..6db0866 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -110,6 +110,7 @@ int mainboard_set_fbd_clock(int speed) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 2392ac2..9ea6c04 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -34,6 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 5962aab..87f8d65 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -34,6 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index b03dfd5..4faae20 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index b4dbe32..070b002 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index b857754..64b4dae 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -43,6 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index d046c4b..8cf2b42 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -42,6 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 22d3270..3c3f9eb 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -42,6 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e7a7f43..825457e 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -74,6 +74,7 @@ static void disable_spd(void) outb(0x67, PM_IO_BASE + 0x37); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 053da17..e733003 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -31,6 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index b4252a6..7325618 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -43,6 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 39385c7..41a65dd 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -46,6 +46,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 053da17..e733003 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -31,6 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index a252e00..3676a6d 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -81,6 +81,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index dd7684a..43158bd 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 37b28df..8de8a83 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -42,6 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { /* FIXME: Should be PC97307! */ diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 5935af2..0ae7610 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -26,6 +26,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index e67ec68..b6412e8 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -154,6 +154,7 @@ static inline void irqinit(void){ #endif } +#include <cpu/intel/car.h> static void main(unsigned long bist) { volatile int i; diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 986e918..6075565 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -30,6 +30,7 @@ int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index 8889015..040b937 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -300,6 +300,7 @@ static void enable_l2_cache(void) pci_write_config8(NB1, 0xe8, reg_nb_f1_e8); } +#include <cpu/intel/car.h> static void main(unsigned long bist) { device_t dev; diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 2f803aa..cbfe04d 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -12,6 +12,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index c014c57..7deb730 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -37,6 +37,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#include <cpu/intel/car.h> void main(unsigned long bist) { ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index bf33dee..8dc61b2 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -33,7 +33,7 @@ #include "memory.c" -void main(unsigned long bist); +#include <cpu/intel/car.h> void main(unsigned long bist) { int cbmem_was_initted; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 190c775..635a44f 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -34,6 +34,7 @@ #include "../qemu-i440fx/memory.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { int cbmem_was_initted; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index b0dd2bc..5ebc451 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -265,6 +265,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 1b2e29b..d28ac34 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index c3926f0..cad3694 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_48mhz_clkin(); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d946ea3..1c7b8ba 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -112,6 +112,7 @@ static void rcba_config(void) RCBA32(FD) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 18c833a..25c6529 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -150,6 +150,7 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 45cf7fe..a4daae5 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -113,6 +113,7 @@ static void rcba_config(void) RCBA32(FD) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 0e29b33..008f1f8 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -154,6 +154,7 @@ static void early_ec_init(void) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 81e1ad2..85660c0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -37,6 +37,7 @@ /* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { /* TODO: It's a PC87364 actually! */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0e74418..eec574d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -223,6 +223,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 8b26b40..b8daac4 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -32,6 +32,7 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 174953d..9a89107 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -32,6 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index a75691c..2af0b2f 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -49,6 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index bf34e9a..d2e331e 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -53,6 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index b34bce4..947b52d 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -53,6 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 6c277d5..982060c 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -35,6 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index fbec052..94b6610 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -156,6 +156,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 249fda4..99445b8 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -120,6 +120,7 @@ static void early_config(void) pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } +#include <cpu/intel/car.h> void main(unsigned long bist) { /* int boot_mode = 0; */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 5597a2d..12abb54 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -162,6 +162,7 @@ static void setup_sio_gpios(void) outb(0xaa, port); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index bddb34a..a672afa 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -38,6 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "debug.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..2e99be5 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -51,6 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address) #include "arch/x86/lib/stages.c" #endif +#include <cpu/intel/car.h> void main(unsigned long bist) { msr_t msr; diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..c56b1df 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -51,6 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address) #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { msr_t msr; diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 342e6f1..f35f93b 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -33,6 +33,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 4da6fe7..5ede2f9 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -332,6 +332,7 @@ static void poulsbo_setup_Stage2Regs(void) printk(BIOS_DEBUG, " done.\n"); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 8455610..cc207b1 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -86,6 +86,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 9c76a42..842f7bc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -329,6 +329,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index d74f3a6..98f5f10 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -159,6 +159,7 @@ static void superio_gpio_config(void) pnp_exit_ext_func_mode(dev); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 4ae5c12..186e9fd 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -48,6 +48,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 548c040..df46092 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -108,6 +108,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d65031a..b2cd616 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -109,6 +109,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 1e2b72d..01e48e7 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -206,6 +206,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index aa2c367..5f8e291 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -215,6 +215,7 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 8c82e61..1705003 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -148,7 +148,7 @@ init_usb (void) outw (0x0000, DEFAULT_PMBASE | 0x003c); } - +#include <cpu/intel/car.h> void main(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index d1f8f64..68a9b48 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -213,6 +213,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 92a3a99..3192e5c 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -71,6 +71,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = { diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 063721b..b3b4498 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -110,6 +110,7 @@ static void mb_gpio_init(void) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 174620a..2f7bd85 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -152,6 +152,7 @@ static void mb_gpio_init(void) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { int err; diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 2642373..18f48f6 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -85,6 +85,7 @@ static void mb_gpio_init(void) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9d5539e..c3f1c8a 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -149,6 +149,7 @@ static void mb_gpio_init(void) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { int err; diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index b337fb2..59e1c6d 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -35,6 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 813e855..578de61 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index b7f99f5..a6767bc 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 09713d4..3811cc5 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -41,6 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index fa78a82..4005ac8 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -36,6 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) +#include <cpu/intel/car.h> void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 08a845d..97d0580 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -34,6 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index c04067c..39c75ca 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 2ca520d..93dd7c2 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -198,6 +198,7 @@ static inline u16 read_acpi16(u32 addr) return inw(DEFAULT_PMBASE | addr); } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 204f0bd..436edc0 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -107,6 +107,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 18453ac..9b272a4 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -130,6 +130,7 @@ static void mb_gpio_init(void) outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ } +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 4db8cbb..7dd4b48 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -94,6 +94,7 @@ static void mb_early_setup(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 1bea48c..a4f55a8 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -251,6 +251,7 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index d4bb56a..f8ff68d 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -120,6 +120,7 @@ static void default_superio_gpio_setup(void) outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ } +#include <cpu/intel/car.h> void main(unsigned long bist) { sysinfo_t sysinfo; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 001a1f8..f984af2 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -132,6 +132,7 @@ static void early_pch_init(void) pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 153ce5c..3abea10 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -172,6 +172,7 @@ static void setup_sio_gpios(void) it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 551c060..fccd29a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index c998466..6b10a68 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -42,6 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index b1c3cfa..9a637be 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -46,6 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index c6350e8..09f4c57 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -43,6 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 2dc96c1..3e51b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -45,6 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 0f2a644..868fbdc 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -45,6 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 791028e..a52193f 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -111,6 +111,7 @@ int mainboard_set_fbd_clock(int speed) } } +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 453cecc..64de0c0 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -136,6 +136,7 @@ static void hard_reset(void) while (1) ; } +#include <cpu/intel/car.h> static void main(unsigned long bist) { volatile int i; diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 053da17..e733003 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -31,6 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 77255e7..ed87462 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -92,6 +92,7 @@ static void mb_early_setup(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 36d55a7..115b402 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -46,6 +46,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index bbd63ee..78313fc 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -40,6 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include <cpu/intel/car.h> void main(unsigned long bist) { pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 600d806..1b03982 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -34,6 +34,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 2d780db..e7e65f2 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -79,6 +79,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index ebe6a50..b3b515d 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -66,6 +66,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } +#include <cpu/intel/car.h> static void main(unsigned long bist) { device_t dev; diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 6198cda..c33acbe 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -373,6 +373,7 @@ static void EmbedComInit(void) #endif /* cache_as_ram.inc jumps to here. */ +#include <cpu/intel/car.h> void main(unsigned long bist) { u16 boot_mode; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index ece64d8..969e2b6 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -42,6 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 tolm; diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 568dab5..5c1477d 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -101,6 +101,7 @@ static void enable_shadow_ram(void) pci_write_config8(ctrl.d0f3, 0x82, shadowreg); } +#include <cpu/intel/car.h> static void main(unsigned long bist) { unsigned long x; diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index b1e6c54..e839541 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -69,6 +69,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } +#include <cpu/intel/car.h> static void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index b270350..aa7e2de 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -55,6 +55,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index e1532be..d3ad0e2 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -83,6 +83,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6a38355..f9b4eec 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -51,6 +51,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 9e5dd53..07216d5 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -49,6 +49,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = {

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coreboot-gerrit August 2014