coreboot-gerrit August 2014

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Patch merged into coreboot/master: 91810dd device/oprom/realmode: Sanitize header inclusion
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 91810ddf798be6067dd4a42dd4c708573645987d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 13:53:04 2014 +1000 device/oprom/realmode: Sanitize header inclusion Alphabetise includes to avoid duplication. Change-Id: I7fa6998cd736bad2bab4a6b1a65d48a21d6220d9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6415 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen(a)se-eng.com> See http://review.coreboot.org/6415 for details. -gerrit

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Patch set updated for coreboot: e06f269 lenovo/x201: Enable wake on LID and Fn key.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6528 -gerrit commit e06f2697eb876c26aba0dc5ecb7538c2639ae203 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:10:28 2014 +0200 lenovo/x201: Enable wake on LID and Fn key. Change-Id: I485da5b8e9084c73f16b5df1c42879697fc0ac3d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/smihandler.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 0529818..ad3911c 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -200,3 +200,23 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +}

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Patch set updated for coreboot: d7a7361 lenovo/x230: Enable wake on LID and Fn key.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6526 -gerrit commit d7a73612be1632081a951ca9d05ead86d7e8c087 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:00:20 2014 +0200 lenovo/x230: Enable wake on LID and Fn key. Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/smihandler.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index bbe08e2..063209d 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -173,3 +173,23 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +}

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New patch to review for coreboot: 1b9390d lenovo/x201: Enable wake on LID.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6528 -gerrit commit 1b9390de4de34ba2eb5a8fbf1aebedcdba62a0b5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:10:28 2014 +0200 lenovo/x201: Enable wake on LID. Change-Id: I485da5b8e9084c73f16b5df1c42879697fc0ac3d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/smihandler.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 0529818..754c981 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -200,3 +200,23 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 4) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +}

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Patch merged into coreboot/master: 62997e0 ARMV7: threading support for cooperative multitasking
by gerrit＠coreboot.org 08 Aug '14

08 Aug '14

the following patch was just integrated into master: commit 62997e0981dddd1ef6b2841fbaee204ed88b9733 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Aug 23 11:22:42 2013 -0700 ARMV7: threading support for cooperative multitasking These functions add support for cooperative multitasking. Currently, since we only have one ARM SOC that uses or supports multitasking, arch_get_thread_stackbase returns CONFIG_STACK_BOTTOM for the thread stack. We may end up having to make a cpu-specific function that arch_get_thread_stackbase calls, but let's avoid adding complexity until we're sure we need to. We also wish to avoid creating Yet Another Config Variable but will do so if pressed. The switch code only saves r4-r11 and lr, which is consistent with the standard. Change-Id: I0338a9c11127351e1f3a190bc51a7a558420b141 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66845 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 22b62af3c26b6b504498b434d29a56a8932f3061) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6517 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6517 for details. -gerrit

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New patch to review for coreboot: 6a8d7b3 falco: Remove RTD2132 chip and setup from devicetree
by Isaac Christensen 08 Aug '14

08 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6527 -gerrit commit 6a8d7b3ce0d9a8604a367e3ba4f1c0c3d8151d00 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 22 10:19:25 2013 -0700 falco: Remove RTD2132 chip and setup from devicetree This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/falco/devicetree.cb | 29 +---------------------------- 2 files changed, 1 insertion(+), 29 deletions(-) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index c3b95a2..27fd3be 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select MONOTONIC_TIMER_MSR - select DRIVERS_I2C_RTD2132 config VBOOT_RAMSTAGE_INDEX hex diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index ab8beae..428a060 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -114,34 +114,7 @@ chip northbridge/intel/haswell end end # LPC bridge device pci 1f.2 on end # SATA Controller - device pci 1f.3 on # SMBus - chip drivers/i2c/rtd2132 - # Panel Power Timings (1 ms units) - # Note: the panel Tx timings are very - # different from the LVDS bridge - # Tx timing settings. Below is a mapping - # for RTD2132 -> Panel timings. - # T1 = T2 - # T2 = T8 + T10 + T12 - # T3 = T14 - # T4 = T15 - # T5 = T9 + T11 + T13 - # T6 = T3 - # T7 = T4 - register "t1" = "20" - register "t2" = "16" - register "t3" = "1" - register "t4" = "1" - register "t5" = "16" - register "t6" = "20" - register "t7" = "500" - # LVDS Swap settings are normal. - register "lvds_swap" = "0" - # Enable Spread Sprectrum at 1.0% - register "sscg_percent" = "0x10" - device i2c 35 on end - end - end + device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal end end

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Patch set updated for coreboot: cb5b149 lenovo/x230: Enable wake on LID.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6526 -gerrit commit cb5b1493e8d3c68fca60c61902ca772664ee8be8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:00:20 2014 +0200 lenovo/x230: Enable wake on LID. Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/smihandler.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index bbe08e2..4d793e0 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -173,3 +173,23 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 4) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +}

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Patch set updated for coreboot: 6e2d18a lenovo/x230: Enable wake on LID.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6526 -gerrit commit 6e2d18a4e48b8d544a80d860b32b0020a5f810cc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:00:20 2014 +0200 lenovo/x230: Enable wake on LID. Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/smihandler.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index bbe08e2..68b7dd5 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -173,3 +173,23 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 4) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout) + } + } +}

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New patch to review for coreboot: 5bc50c8 lenovo/x230: Enable wake on LID.
by Vladimir Serbinenko 08 Aug '14

08 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6526 -gerrit commit 5bc50c8eeb57cd062c573488a9bf02efe0073c59 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 8 00:00:20 2014 +0200 lenovo/x230: Enable wake on LID. Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/devicetree.cb | 1 + src/mainboard/lenovo/x230/smihandler.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1a93ad8..2043dd9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -60,6 +60,7 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) register "sata_port_map" = "0x7" diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index bbe08e2..497f77b 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -173,3 +173,14 @@ int mainboard_smi_apmc(u8 data) } return 0; } + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 4) + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + } +}

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Patch merged into coreboot/master: ad4afe9 armv7: Fix dcache writethrough policy handling
by gerrit＠coreboot.org 07 Aug '14

07 Aug '14

the following patch was just integrated into master: commit ad4afe9b043bd2ab9482c677f29c6d74e250d5e2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Aug 28 12:39:11 2013 -0700 armv7: Fix dcache writethrough policy handling The "bufferable" bit was erroneously set for the writethrough policy making it the same as writeback. (credit to jwerner for pointing this out) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I567d57f0e522cb4b82988894ba9b4638642bf8db Reviewed-on: https://chromium-review.googlesource.com/167323 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: ron minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 36cf13839604c349692865475f3011afd08965b4) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6515 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6515 for details. -gerrit

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coreboot-gerrit August 2014