coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: f9061cf util/sconfig/main.c: Free memory pointed to by `outputc`
by Paul Menzel 04 Aug '14

04 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6487 -gerrit commit f9061cf60cf79c156aa713d3325529688ae2f7b0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Aug 4 08:22:39 2014 +0200 util/sconfig/main.c: Free memory pointed to by `outputc` Cppcheck 1.65 reports the error below. [main.c:709]: (error) Memory leak: outputc So free the memory space pointed to by `outputc` to fix the memory leak. Change-Id: I1767cd15380832a93cc79fb515861982e3f1ee94 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/sconfig/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6295e01..90ceda2 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -629,9 +629,11 @@ int main(int argc, char** argv) { FILE *autogen = fopen(outputc, "w"); if (!autogen) { fprintf(stderr, "Could not open file '%s' for writing: ", outputc); + free(outputc); perror(NULL); exit(1); } + free(outputc); struct header *h; if (scan_mode == STATIC_MODE) {

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New patch to review for coreboot: 0162234 util/sconfig/main.c: Free memory pointed to by `devtree`
by Paul Menzel 04 Aug '14

04 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6486 -gerrit commit 0162234401f52cc13c5cf2edf501047b45977e83 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Aug 4 08:15:03 2014 +0200 util/sconfig/main.c: Free memory pointed to by `devtree` Cppcheck 1.65 reports the error below. [main.c:709]: (error) Memory leak: devtree So free the memory space pointed to by `devtree` to fix the memory leak. Change-Id: Ibcd93057e88544ea900d9b6261c907baa751b2f1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/sconfig/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 44d4911..6295e01 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -606,9 +606,11 @@ int main(int argc, char** argv) { FILE *filec = fopen(devtree, "r"); if (!filec) { fprintf(stderr, "Could not open file '%s' for reading: ", devtree); + free(devtree); perror(NULL); exit(1); } + free(devtree); yyrestart(filec);

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Patch set updated for coreboot: fe5451d Add missing header guards
by HAOUAS Elyes 04 Aug '14

04 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6455 -gerrit commit fe5451d01bccf7e5658f2241af18b2c0441f03fc Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Aug 4 08:22:10 2014 +0200 Add missing header guards Change-Id: I065297cdb20dc0f31c1eddc03f0382d5c59ec7e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/amdfam10.h | 6 +++--- src/northbridge/amd/amdfam10/nums.h | 7 +++---- src/northbridge/amd/amdk8/amdk8.h | 7 +++---- src/northbridge/amd/amdmct/amddefs.h | 5 +++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 5 +++++ src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/e7520/e7520.h | 5 +++++ src/northbridge/intel/e7525/e7525.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/via/cn400/cn400.h | 5 +++++ src/northbridge/via/cn700/cn700.h | 5 +++++ src/northbridge/via/cx700/registers.h | 5 +++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 5 +++++ src/southbridge/intel/i82870/82870.h | 5 +++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 5 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/early_setup_ss.h | 5 +++++ src/southbridge/ricoh/rl5c476/rl5c476.h | 7 +++++-- src/southbridge/sis/sis966/early_setup_ss.h | 5 +++++ src/southbridge/ti/pci7420/pci7420.h | 5 +++++ src/southbridge/via/common/via_early_smbus.h | 5 +++++ src/southbridge/via/vt82c686/vt82c686.h | 5 +++++ 25 files changed, 118 insertions(+), 13 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..da9792f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef AMDFAM10_H +#ifndef NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H +#define NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H -#define AMDFAM10_H /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -1200,4 +1200,4 @@ u8 get_sbbusn(u8 sblk); #include "northbridge/amd/amdht/porting.h" BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); -#endif /* AMDFAM10_H */ +#endif /* NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h index 12bac5d..a2856b2 100644 --- a/src/northbridge/amd/amdfam10/nums.h +++ b/src/northbridge/amd/amdfam10/nums.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef AMDFAM10_NUMS_H - -#define AMDFAM10_NUMS_H +#ifndef NORTHBRIDGE_AMD_AMDFAM10_NUMS_H +#define NORTHBRIDGE_AMD_AMDFAM10_NUMS_H #if CONFIG_MAX_PHYSICAL_CPUS > 8 #if CONFIG_MAX_PHYSICAL_CPUS > 32 @@ -37,4 +36,4 @@ //it could be more bigger #define HC_POSSIBLE_NUM 32 -#endif +#endif /* NORTHBRIDGE_AMD_AMDFAM10_NUMS_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2f7ee9c 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -1,6 +1,5 @@ -#ifndef AMDK8_H - -#define AMDK8_H +#ifndef NORTHBRIDGE_AMD_AMDK8_AMDK8_H +#define NORTHBRIDGE_AMD_AMDK8_AMDK8_H #if CONFIG_K8_REV_F_SUPPORT @@ -19,4 +18,4 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_ void cpus_ready_for_init(void); -#endif /* AMDK8_H */ +#endif /* NORTHBRIDGE_AMD_AMDK8_AMDK8_H */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..2798263 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H +#define NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ @@ -148,3 +151,5 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 + +#endif /* NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index e989ae3..5d487e6 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H +#define NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { @@ -376,3 +378,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index abe6e7b..1e4016b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H +#define NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H + static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( @@ -358,3 +361,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H */ diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index 1e431b1..23a135c 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_INTEL_E7501_E7501_H +#define NORTHBRIDGE_INTEL_E7501_E7501_H + /* * e7501.h: PCI configuration space for the Intel E7501 memory controller */ @@ -77,3 +80,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7501_E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 08b681a..09c287b 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H +#define NORTHBRIDGE_INTEL_E7505_E7505_H + /* * e7505.h: PCI configuration space for the Intel E7501 memory controller */ @@ -82,3 +85,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h index 61401e4..d3a71e6 100644 --- a/src/northbridge/intel/e7520/e7520.h +++ b/src/northbridge/intel/e7520/e7520.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_E7520_E7520_H +#define NORTHBRIDGE_INTEL_E7520_E7520_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* NORTHBRIDGE_INTEL_E7520_E7520_H */ diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h index 61401e4..d7c3574 100644 --- a/src/northbridge/intel/e7525/e7525.h +++ b/src/northbridge/intel/e7525/e7525.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_E7525_E7525_H +#define NORTHBRIDGE_INTEL_E7525_E7525_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* NORTHBRIDGE_INTEL_E7525_E7525_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index bdf7e51..8a86279 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H +#define NORTHBRIDGE_INTEL_I82830_I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -49,3 +52,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..b09dea6 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_INTEL_I855_I855_H +#define NORTHBRIDGE_INTEL_I855_I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -74,3 +77,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* NORTHBRIDGE_INTEL_I855_I855_H */ diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..74cdaa6 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_VIA_CN400_CN400_H +#define NORTHBRIDGE_VIA_CN400_CN400_H + #ifndef __PRE_RAM__ // HACK static inline void cn400_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +#endif /* NORTHBRIDGE_VIA_CN400_CN400_H */ diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index ff1d4b3..f3f1d24 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_VIA_CN700_CN700_H +#define NORTHBRIDGE_VIA_CN700_CN700_H + #if !defined (__PRE_RAM__) // HACK static inline void cn700_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn700_noop(device_t dev) #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif /* NORTHBRIDGE_VIA_CN700_CN700_H */ diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h index 67c3da4..730aa75 100644 --- a/src/northbridge/via/cx700/registers.h +++ b/src/northbridge/via/cx700/registers.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_VIA_CX700_REGISTERS_H +#define NORTHBRIDGE_VIA_CX700_REGISTERS_H + /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ #define SCRATCH_REG_BASE 0xd0 #define SCRATCH_RANK_0 0xd0 @@ -42,3 +45,5 @@ #define DDRII_333 0x2 #define DDRII_266 0x1 #define DDRII_200 0x0 + +#endif /* NORTHBRIDGE_VIA_CX700_REGISTERS_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..50d3bfc 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,3 +1,6 @@ +#ifndef SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H +#define SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H + #include <device/smbus_def.h> #define SMBGSTATUS 0xe0 @@ -323,3 +326,5 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne } return 0; } + +#endif /* SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H */ diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index b576cc1..f857c40 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,3 +1,6 @@ +#ifndef SOUTHBRIDGE_INTEL_I82870_82870_H +#define SOUTHBRIDGE_INTEL_I82870_82870_H + /* for io apic 1461 */ #define MBAR 0x10 #define ABAR 0x40 @@ -12,3 +15,5 @@ #define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero) #define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + +#endif /* SOUTHBRIDGE_INTEL_I82870_82870_H */ diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h index 9f89595..fb2be0b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index cf25403..62dc1db 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -1,5 +1,10 @@ +#ifndef SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H +#define SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H + int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); int smbus_write_byte(unsigned int, unsigned int, unsigned char); + +#endif /* SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h index 0aadc73..031ff72 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -219,3 +222,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 71966a1..2720808 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -18,12 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - /* rl5c476 routines and defines*/ +#ifndef SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H +#define SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H + /* rl5c476 routines and defines*/ #include <stdint.h> - /* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { u8 idrevs; @@ -92,3 +93,5 @@ typedef struct pc16reg { u8 resv9; u8 smpga0; } __attribute__ ((packed)) pc16reg_t; + +#endif /* SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H */ diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h index b6aa7d7..d8226d5 100644 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ b/src/southbridge/sis/sis966/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index f71fe17..58fe5e2 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SOUTHBRIDGE_TI_PCI7420_PCI7420_H +#define SOUTHBRIDGE_TI_PCI7420_PCI7420_H + // 0844d060 (old) #define SYSCTL 0x80 // 08405061 #define RIMUX (1 << 0) @@ -47,3 +50,5 @@ #define INTB 1 #define INTC 2 #define INTD 3 + +#endif /* SOUTHBRIDGE_TI_PCI7420_PCI7420_H */ diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h index aca920b..0f91548 100644 --- a/src/southbridge/via/common/via_early_smbus.h +++ b/src/southbridge/via/common/via_early_smbus.h @@ -17,6 +17,9 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H +#define SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H + /** * @file via_early_sambus.h * @@ -54,3 +57,5 @@ #include <device/early_smbus.h> #include <arch/io.h> + +#endif /* SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H */ diff --git a/src/southbridge/via/vt82c686/vt82c686.h b/src/southbridge/via/vt82c686/vt82c686.h index 7d2ac52..c2440d6 100644 --- a/src/southbridge/via/vt82c686/vt82c686.h +++ b/src/southbridge/via/vt82c686/vt82c686.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SOUTHBRIDGE_VIA_VT82C686_VT82C686_H +#define SOUTHBRIDGE_VIA_VT82C686_VT82C686_H + /* Datasheets: * Name: VT82C686A "Super South" South Bridge * Link: http://www.datasheets.org.uk/datasheet.php?article=3510260 @@ -53,3 +56,5 @@ PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ + +#endif /* SOUTHBRIDGE_VIA_VT82C686_VT82C686_H */

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Patch merged into coreboot/master: 1f68880 sconfig: more careful string resource handling
by gerrit＠coreboot.org 04 Aug '14

04 Aug '14

the following patch was just integrated into master: commit 1f68880e50a2b847838bbdc6916484f9fd86a681 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 15:51:19 2014 +0200 sconfig: more careful string resource handling When parsing a string to numbers, we don't need to copy it. And when creating strings, we should eventually free them. Change-Id: I9023fef6e97a1830bc68502be32e79879c1617d4 Found-By: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6484 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6484 for details. -gerrit

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New patch to review for coreboot: 9c30a0d northbridge/via/vx800: Fix out-of-bounds read due to off-by-one
by Edward O'Callaghan 04 Aug '14

04 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6485 -gerrit commit 9c30a0d4342899453781560a3afe6b72e3e4a375 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Aug 4 09:58:30 2014 +1000 northbridge/via/vx800: Fix out-of-bounds read due to off-by-one Change-Id: Ia7fda59b60b2148dd4d246686bd94d2334b23eb5 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/vx800/driving_setting.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index 695fcab..0c8865a 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -370,7 +370,7 @@ void DrivingDCLK(DRAM_SYS_ATTR * DramAttr) else if (DIMMFREQ_667 == DramAttr->DramFreq) FreqId = 2; else if (DIMMFREQ_800 == DramAttr->DramFreq) - FreqId = 4; + FreqId = 3; else FreqId = 0;

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Patch set updated for coreboot: a5560ea cpu/intel: Fix out-of-bounds read due to off-by-one in condition
by Edward O'Callaghan 03 Aug '14

03 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6478 -gerrit commit a5560ea8ad27cc8a8f2631ec9766ddbd402e54cb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 20:00:47 2014 +1000 cpu/intel: Fix out-of-bounds read due to off-by-one in condition If power_limit_1_time > 129 is false then power_limit_1_time can have a value of up to 129 leading to an out-of-bounds illegal read indexing the power_limit_time_sec_to_msr[] array. Thankfully all call sites have been doing the right thing up until now so the issue has not been visible. Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 2 +- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index c2f9f19..ac1880a 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -156,7 +156,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned tdp, min_power, max_power, max_time; u8 power_limit_1_val; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) return; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 043ba3a..68c7643 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -463,8 +463,8 @@ void set_power_limits(u8 power_limit_1_time) unsigned tdp, min_power, max_power, max_time; u8 power_limit_1_val; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = 28; + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4e56414..dbde512 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -247,7 +247,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned tdp, min_power, max_power, max_time; u8 power_limit_1_val; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) return; if (!(msr.lo & PLATFORM_INFO_SET_TDP))

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New patch to review for coreboot: 927a150 sconfig: more careful string resource handling
by Patrick Georgi 03 Aug '14

03 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6484 -gerrit commit 927a150faf917b5b9da5406d9b9356702a5a001f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 15:51:19 2014 +0200 sconfig: more careful string resource handling When parsing a string to numbers, we don't need to copy it. And when creating strings, we should eventually free them. Change-Id: I9023fef6e97a1830bc68502be32e79879c1617d4 Found-By: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 20471de..ce39a11 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -195,6 +195,7 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { parent->latestchild = new_chip; if (!parent->children) parent->children = new_chip; + free(chip_h); return new_chip; } @@ -225,7 +226,7 @@ struct device *new_device(struct device *parent, struct device *busdev, const in new_d->bustype = bus; char *tmp; - new_d->path_a = strtol(strdup(devnum), &tmp, 16); + new_d->path_a = strtol(devnum, &tmp, 16); if (*tmp == '.') { tmp++; new_d->path_b = strtol(tmp, NULL, 16);

1 0

Patch merged into coreboot/master: 55391c4 nehalem: Make UMA size configurable in CMOS.
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 55391c422f8c45e40bb014d238769501aed65d56 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 14:51:00 2014 +0200 nehalem: Make UMA size configurable in CMOS. All modes tested on X201. Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6481 for details. -gerrit

1 0

Patch set updated for coreboot: 5bad85a northbridge/intel: Out of bounds write to array in gma.h
by Edward O'Callaghan 03 Aug '14

03 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6473 -gerrit commit 5bad85ac4bcdab72ad8aee2ae31ecc4f1924df0a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 23:38:17 2014 +1000 northbridge/intel: Out of bounds write to array in gma.h The signature[] array in the mailbox struct opregion_header_t has IGD_OPREGION_SIGNATURE written to it with a sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This resulted in a silent off-by-one out of bounds illegal write. Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +- src/northbridge/intel/haswell/acpi.c | 2 +- src/northbridge/intel/nehalem/acpi.c | 2 +- src/northbridge/intel/sandybridge/acpi.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 3e47ed4..faef4d7 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -142,7 +142,7 @@ int init_igd_opregion(igd_opregion_t *opregion) // FIXME if IGD is disabled, we should exit here. memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(opregion->header.signature)); /* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024; diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 964a9d3..b2fab11 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -140,7 +140,7 @@ int init_igd_opregion(igd_opregion_t *opregion) // FIXME if IGD is disabled, we should exit here. memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(opregion->header.signature)); /* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024; diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 077ceda..0ede237 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -139,7 +139,7 @@ int init_igd_opregion(igd_opregion_t * opregion) // FIXME if IGD is disabled, we should exit here. memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(opregion->header.signature)); /* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024; diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 398cb30..58e3b54 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -142,7 +142,7 @@ int init_igd_opregion(igd_opregion_t *opregion) // FIXME if IGD is disabled, we should exit here. memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(opregion->header.signature)); /* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024;

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New patch to review for coreboot: 2b2169f sconfig: improve argument parsing
by Patrick Georgi 03 Aug '14

03 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6483 -gerrit commit 2b2169fdb7784ea92020a486d32003afdef463d3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 3 15:27:35 2014 +0200 sconfig: improve argument parsing Running sconfig with four arguments where the third does not match /-./ made sconfig use uninitialized memory to build the output filename. Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0 Found-By: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index f6ec0e2..20471de 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -570,7 +570,10 @@ int main(int argc, char** argv) { scan_mode = STATIC_MODE; outputc=malloc(strlen(outputdir)+20); sprintf(outputc, "%s/static.c", outputdir); - } else if ((argc == 5) && (argv[3][0] == '-') && (argv[3][2] == 0)) { + } else if (argc == 5) { + if ((argv[3][0] != '-') || (argv[3][2] == 0)) { + usage(); + } switch (argv[3][1]) { case 's':

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coreboot-gerrit August 2014