New patch to review for coreboot: ec33d6b superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463
-gerrit
commit ec33d6bf94556268ba04fb736155d77343b53e12 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Aug 2 20:08:35 2014 +1000
superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/amd/dinar/romstage.c | 4 ++-- src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 4 ++++ src/superio/smsc/sio1036/sio1036_early_init.c | 13 ++++++------- 4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..6e217f1 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,7 +33,7 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> @@ -53,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); + sio1036_early_init(0x4E, CONFIG_TTYS0_BASE); }
post_code(0x31); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
+romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..d6b7978 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,8 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6)
+#include <stdint.h> + +void sio1036_early_init(unsigned port, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..be91669 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,20 +20,19 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
#include <arch/io.h> +#include <stdint.h> + #include "sio1036.h"
-#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); }
static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); }
@@ -55,7 +54,7 @@ static u8 detect_sio1036_chip(unsigned port) }; }
-static inline void sio1036_early_init(unsigned port) +void sio1036_early_init(unsigned port, u16 iobase) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port)
/* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
/* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);
-
Edward O'Callaghan