coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c13d7be amd/dinar: Fix agesawrapper header
by Kyösti Mälkki 04 Jul '14

04 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6179 -gerrit commit c13d7be92ef5935e9fccfaadd6fb47bd8c0af856 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 4 17:32:22 2014 +0300 amd/dinar: Fix agesawrapper header Change-Id: I246cfb38aa47e67d62bcfcc37539e9593b8026ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/romstage.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 0b52ea9..8851e8c 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -22,33 +22,23 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/cpu.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" +#include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#include "Platform.h" -#include <arch/cpu.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -u32 agesawrapper_amdinitmmio (void); -u32 agesawrapper_amdinitreset (void); -u32 agesawrapper_amdinitearly (void); -u32 agesawrapper_amdinitenv (void); -u32 agesawrapper_amdinitlate (void); -u32 agesawrapper_amdinitpost (void); -u32 agesawrapper_amdinitmid (void); - - - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val;

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Patch merged into coreboot/master: bda9a82 Documentation: Use correct file name for the build guide in the Makefile
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit bda9a821142c0a105bc8892aef610ea43ce3400c Author: Vladimir Berezniker <vmpn(a)vmpn.net> Date: Tue Jul 1 20:40:18 2014 -0400 Documentation: Use correct file name for the build guide in the Makefile Change-Id: I19c456e8bcd2de19c5f9d963ea17dad84d300ab8 Signed-off-by: Vladimir Berezniker <vmpn(a)vmpn.net> Reviewed-on: http://review.coreboot.org/6170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6170 for details. -gerrit

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Patch merged into coreboot/master: e05cba2 intel/lynxpoint: Add SATA DEVSLP disable option
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit e05cba2c7225d43913fea3b0066f2e24990cee6f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Oct 30 23:56:26 2013 -0600 intel/lynxpoint: Add SATA DEVSLP disable option Add the chip option to disable SATA DEVSLP. This disables the SDS bit in the SATA CAP2 register. BUG=chrome-os-partner:23186 BRANCH=leon TEST=Manual: System runs without SATA failure for more than 10 hours Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/174648 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4) Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/176352 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/6013 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6013 for details. -gerrit

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Patch merged into coreboot/master: 5a45b04 intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit 5a45b04ac0e4a296f1df1984200766151c66c42c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 22 09:56:42 2013 -0700 intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig This was missing from lynxpoint. BUG=chrome-os-partner:21796 BRANCH=falco,peppy TEST=emerge-falco chromeos-coreboot-falco Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66669 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/6012 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6012 for details. -gerrit

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Patch merged into coreboot/master: 78145a5 intel/lynxpoint: Use separate SMI callback for USB XHCI routing
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit 78145a56b4f0332804d3b843f0ca855821308d83 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 21 13:16:21 2013 -0700 intel/lynxpoint: Use separate SMI callback for USB XHCI routing This will allow the legacy mode boot path to leave USB ports routed to EHCI so they can be used by SeaBIOS. BUG=chrome-os-partner:22085 BRANCH=falco,peppy TEST=manual: Build and boot from USB and SeaBIOS on falco Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66547 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/6011 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6011 for details. -gerrit

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Patch merged into coreboot/master: 7034b9e intel/haswell: Allow overriding PRE_GRAPHICS_DELAY in config
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit 7034b9ef77c8e3782eb920f602ef962a38f221a3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Feb 11 16:18:07 2014 -0800 intel/haswell: Allow overriding PRE_GRAPHICS_DELAY in config Without a prompt the config option will always stay 0 due to the way Kconfig works. BUG=chrome-os-partner:25387 BRANCH=panther TEST=Boot into dev mode with Mohammed's TV screen, see the dev mode screen appear. Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185970 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/6010 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6010 for details. -gerrit

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Patch merged into coreboot/master: f1aabec intel/haswell: Allow pre-graphics delay
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit f1aabecaaccbac8ed575312f3801ec9de7e912a9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 22 15:16:30 2014 -0800 intel/haswell: Allow pre-graphics delay Some slow monitors/TVs can't wake up quickly enough for coreboot, so when the VBIOS is run it won't detect them. Hence, add an option to wait for a while before running the VBIOS. BUG=none BRANCH=panther TEST=Boot to dev mode on one of the systems that exposed the problem and see it go away. Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183545 Reviewed-by: Mohammed Habibulla <moch(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/6009 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6009 for details. -gerrit

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Patch merged into coreboot/master: 0089c24 intel/lynxpoint: Make inclusion of Intel ME optional
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit 0089c2418b252483120f72a47955f771b3993a28 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jun 16 14:59:44 2014 +0200 intel/lynxpoint: Make inclusion of Intel ME optional Current build configuration always wants to include an Intel Management Engine (ME) firmware (`me.bin`) on Intel Lynx Point systems. However, we can have a working coreboot without it, as long as the factory delivered ME firmware is kept untouched in the flash ROM. So let the user decide if a ME firmware will be included in the build by introducing the Kconfig option `HAVE_ME_BIN`. The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin optional) [1] for Intel Sandy Bridge (BD82x6x). [1] http://review.coreboot.org/3522 Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6047 for details. -gerrit

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Patch merged into coreboot/master: 5218e61 intel/lynxpoint: Allow building without IFD (descripter.bin)
by gerrit＠coreboot.org 04 Jul '14

04 Jul '14

the following patch was just integrated into master: commit 5218e616517ff5118080b01ce2f4305699f8b319 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jun 16 09:28:36 2014 +0200 intel/lynxpoint: Allow building without IFD (descripter.bin) On newer Intel systems, like Intel Lynx Point, the flash ROM is shared between the host processor (BIOS), its Management Engine (ME) and an integrated Ethernet controller (GbE). The layout of the flash ROM (and other information) is kept in the so called Intel Firmware Descriptor (IFD). If we only want to build coreboot to update the BIOS section, all we need is the flash layout. So add the option to specify the flash layout in the mainboard’s Kconfig, and thus, to build without the real IFD. However, with such a build, one has to make sure that the IFD section on the flash ROM will not be written over (nor any other section that has not been included by coreboot). A patch to write selected sections of a flash ROM with IFD has been sent to the flashrom mailing list [2]. The same was done in commit a15cd66b [1] (sandybridge: Make build possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x). [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [PATCH] Add option to read ROM layout from IFD [2] http://review.coreboot.org/3524 Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6046 for details. -gerrit

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New patch to review for coreboot: 231b0c4 YABEL: Drop IO stubs that are (by own admission) never used
by Patrick Georgi 04 Jul '14

04 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6178 -gerrit commit 231b0c41097e99f2a29cce52adc381c36afcd9ea Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jun 27 12:16:17 2014 +0200 YABEL: Drop IO stubs that are (by own admission) never used Change-Id: I90a120e64a5062493f64e3e8b48a75dae9342ec4 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/device/oprom/yabel/io.c | 47 --------------------------------------------- 1 file changed, 47 deletions(-) diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 37beccb..08189a9 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -26,53 +26,6 @@ #include <arch/io.h> -// these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs -// with the functions and struct below -void -outb(u8 val, u16 port) -{ - printf("WARNING: outb not implemented!\n"); - HALT_SYS(); -} - -void -outw(u16 val, u16 port) -{ - printf("WARNING: outw not implemented!\n"); - HALT_SYS(); -} - -void -outl(u32 val, u16 port) -{ - printf("WARNING: outl not implemented!\n"); - HALT_SYS(); -} - -u8 -inb(u16 port) -{ - printf("WARNING: inb not implemented!\n"); - HALT_SYS(); - return 0; -} - -u16 -inw(u16 port) -{ - printf("WARNING: inw not implemented!\n"); - HALT_SYS(); - return 0; -} - -u32 -inl(u16 port) -{ - printf("WARNING: inl not implemented!\n"); - HALT_SYS(); - return 0; -} - #if CONFIG_YABEL_DIRECTHW u8 my_inb(X86EMU_pioAddr addr) {

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coreboot-gerrit July 2014