coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 501093d Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 501093d4fe993cfcca915c0d1fe2ab3a596d27b7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jun 16 17:40:11 2014 +0200 Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN` Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6049 for details. -gerrit

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Patch merged into coreboot/master: cc53d51 Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit cc53d5122505e3528a1f3d38004649bca8ff975e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jun 16 17:30:56 2014 +0200 Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN` Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6048 for details. -gerrit

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Patch set updated for coreboot: 1919d32 mainboard/lippert: Forward port MPTable use mainboard IRQ routing
by Edward O'Callaghan 05 Jul '14

05 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6056 -gerrit commit 1919d327a9ac5c3b200300221be4a99b22cbfa22 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jun 17 17:28:44 2014 +1000 mainboard/lippert: Forward port MPTable use mainboard IRQ routing Forward port the following updates to the reference board from which these lippert boards were derived: cbc783f Persimmon: Change MPTable to use mainboard IRQ routing Sanitize headers while here. Change-Id: Id4fca6c8ddc6ff72f4a3cc6568631c6186476ec2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../lippert/frontrunner-af/get_bus_conf.c | 25 +++- src/mainboard/lippert/frontrunner-af/mainboard.c | 124 +++++++++++++++-- src/mainboard/lippert/frontrunner-af/mptable.c | 155 ++++++++++----------- src/mainboard/lippert/toucan-af/get_bus_conf.c | 25 +++- src/mainboard/lippert/toucan-af/mainboard.c | 124 +++++++++++++++-- src/mainboard/lippert/toucan-af/mptable.c | 155 ++++++++++----------- 6 files changed, 412 insertions(+), 196 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index bddcee1..aba121e 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,17 +19,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + +#include <arch/ioapic.h> #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h> /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -36,6 +39,7 @@ u8 bus_isa; u8 bus_sb800[6]; u32 apicid_sb800; +u32 apicver_sb800; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -98,7 +102,14 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); + apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index f813358..175fec6 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,20 +19,119 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ +#include <stdlib.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg:06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + /* Init SIO GPIOs. */ #define SIO_RUNTIME_BASE 0x0E00 @@ -184,6 +285,9 @@ static void mainboard_enable(device_t dev) */ pm_iowrite(0x29, 0x80); pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 498ae58..f1e83ee 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,131 +19,122 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> +#include <drivers/generic/ioapic/chip.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> -extern u8 bus_sb800[6]; +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx/cimx_util.h> +extern u8 bus_sb800[6]; extern u32 apicid_sb800; +extern u32 apicver_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800; -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + /* Intialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - mptable_write_buses(mc, NULL, &bus_isa); + /* Get Bus Configuration */ + get_bus_conf(); - /* I/O APICs: APIC ID Version State Address */ - - u32 dword; - u8 byte; - - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) -#else -#define PCI_INT(bus, dev, fn, pin) -#endif - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - /* on board NIC & Slot PCIE. */ + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ @@ -153,6 +146,6 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; - v = smp_write_floating_table(addr, 0); + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index f0de0e5..230a12d 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,17 +19,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + +#include <arch/ioapic.h> #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h> /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -36,6 +39,7 @@ u8 bus_isa; u8 bus_sb800[6]; u32 apicid_sb800; +u32 apicver_sb800; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -97,7 +101,14 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); + apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 6608930..447c672 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,20 +19,119 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ +#include <stdlib.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg:06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /* Write data block to slave on SMBUS0. */ #define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0) @@ -151,6 +252,9 @@ static void mainboard_enable(device_t dev) */ pm_iowrite(0x29, 0x80); pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 498ae58..f1e83ee 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,131 +19,122 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> +#include <drivers/generic/ioapic/chip.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> -extern u8 bus_sb800[6]; +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx/cimx_util.h> +extern u8 bus_sb800[6]; extern u32 apicid_sb800; +extern u32 apicver_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800; -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + /* Intialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - mptable_write_buses(mc, NULL, &bus_isa); + /* Get Bus Configuration */ + get_bus_conf(); - /* I/O APICs: APIC ID Version State Address */ - - u32 dword; - u8 byte; - - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) -#else -#define PCI_INT(bus, dev, fn, pin) -#endif - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - /* on board NIC & Slot PCIE. */ + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ @@ -153,6 +146,6 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; - v = smp_write_floating_table(addr, 0); + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); }

1 0

Patch set updated for coreboot: be57ac0 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
by Edward O'Callaghan 05 Jul '14

05 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6155 -gerrit commit be57ac0a2f1e46a84c7978c721d125ac927ae039 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 22:47:22 2014 +1000 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 41 ++++++++++++++++++----------------------- src/southbridge/amd/rs780/cmn.c | 40 ++++++++++++++++++---------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..05a47b3 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -47,7 +47,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -60,7 +60,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -191,12 +191,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -245,11 +245,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -278,17 +278,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -309,9 +305,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs690_set_tom(device_t nb_dev) { /* set TOM */ @@ -324,4 +320,3 @@ void rs690_set_tom(device_t nb_dev) nbmc_write_index(nb_dev, 0x1e, 0x38000000); #endif } - diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..497d1af 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -46,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -59,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -190,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -249,11 +249,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -319,17 +319,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -350,9 +346,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs780_set_tom(device_t nb_dev) { /* set TOM */

1 0

Patch merged into coreboot/master: 32d2298 amd/dinar: Fix agesawrapper header
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 32d22988282c0696dd89312e41b4a9ef57886443 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 4 17:32:22 2014 +0300 amd/dinar: Fix agesawrapper header Change-Id: I246cfb38aa47e67d62bcfcc37539e9593b8026ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6179 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6179 for details. -gerrit

1 0

Patch merged into coreboot/master: 36abdc4 gizmosphere/gizmo: Move support of SPD data in CBFS
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 36abdc4017d93484577fe08fdb61d8ff22c6259c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 16:40:15 2014 +0300 gizmosphere/gizmo: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5690 for details. -gerrit

1 0

New patch to review for coreboot: c95a06c AGESA: No need to shout VOID in agesawrapper
by Edward O'Callaghan 05 Jul '14

05 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6183 -gerrit commit c95a06c94a9e6b2f91c7f0b0f282a53f2fba1ed2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jul 5 19:35:17 2014 +1000 AGESA: No need to shout VOID in agesawrapper Change-Id: I9a8a310d5f0df7a514c370fec3cbf23f9675bd63 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/agesawrapper.c | 4 ++-- src/mainboard/amd/olivehill/agesawrapper.c | 10 +++++----- src/mainboard/amd/olivehill/agesawrapper.h | 10 +++++----- src/mainboard/amd/parmer/agesawrapper.c | 10 +++++----- src/mainboard/amd/parmer/agesawrapper.h | 10 +++++----- src/mainboard/amd/thatcher/agesawrapper.c | 10 +++++----- src/mainboard/amd/thatcher/agesawrapper.h | 10 +++++----- src/mainboard/asrock/imb-a180/agesawrapper.c | 10 +++++----- src/mainboard/asrock/imb-a180/agesawrapper.h | 10 +++++----- src/mainboard/asus/f2a85-m/agesawrapper.c | 10 +++++----- src/mainboard/asus/f2a85-m/agesawrapper.h | 10 +++++----- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 10 +++++----- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h | 10 +++++----- src/mainboard/supermicro/h8qgi/agesawrapper.c | 16 ++++++++-------- src/mainboard/supermicro/h8scm/agesawrapper.c | 16 ++++++++-------- src/mainboard/tyan/s8226/agesawrapper.c | 14 +++++++------- 16 files changed, 85 insertions(+), 85 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 782512d..e561293 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -78,7 +78,7 @@ GetEndBusNum ( return Index; } -static UINT32 amdinitcpuio(VOID) +static UINT32 amdinitcpuio(void) { AGESA_STATUS Status; UINT64 MsrReg; @@ -471,7 +471,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( return status; } -AGESA_STATUS agesawrapper_amdinitlate(VOID) +AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index f4ea628..4009838 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -417,7 +417,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -455,7 +455,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -478,7 +478,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -521,7 +521,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -557,7 +557,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/amd/olivehill/agesawrapper.h b/src/mainboard/amd/olivehill/agesawrapper.h index f826d80..038895a 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.h +++ b/src/mainboard/amd/olivehill/agesawrapper.h @@ -51,11 +51,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); AGESA_STATUS agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c011242..a56d267 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -418,7 +418,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -456,7 +456,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -480,7 +480,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -523,7 +523,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -560,7 +560,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/amd/parmer/agesawrapper.h b/src/mainboard/amd/parmer/agesawrapper.h index f826d80..038895a 100644 --- a/src/mainboard/amd/parmer/agesawrapper.h +++ b/src/mainboard/amd/parmer/agesawrapper.h @@ -51,11 +51,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); AGESA_STATUS agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 74a2321..ab5e775 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -415,7 +415,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -455,7 +455,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -478,7 +478,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -523,7 +523,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -559,7 +559,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h index f826d80..038895a 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.h +++ b/src/mainboard/amd/thatcher/agesawrapper.h @@ -51,11 +51,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); AGESA_STATUS agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index fcb9827..167440a 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -446,7 +446,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -484,7 +484,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -507,7 +507,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -550,7 +550,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -586,7 +586,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.h b/src/mainboard/asrock/imb-a180/agesawrapper.h index 60ec551..97cb8c5 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.h +++ b/src/mainboard/asrock/imb-a180/agesawrapper.h @@ -80,11 +80,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); AGESA_STATUS agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 46d24ad..33bb5fd 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -430,7 +430,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -470,7 +470,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -493,7 +493,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -538,7 +538,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -574,7 +574,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h index 5294562..3db75e8 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -79,11 +79,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); AGESA_STATUS agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 1e010d2..1b5cc39 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -429,7 +429,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( } -AGESA_STATUS agesawrapper_amdinitresume(VOID) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -467,7 +467,7 @@ AGESA_STATUS agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -491,7 +491,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID) } #endif -AGESA_STATUS agesawrapper_amds3laterestore (VOID) +AGESA_STATUS agesawrapper_amds3laterestore (void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdInterfaceParams; @@ -534,7 +534,7 @@ AGESA_STATUS agesawrapper_amds3laterestore (VOID) extern UINT8 picr_data[0x54], intr_data[0x54]; -AGESA_STATUS agesawrapper_fchs3laterestore (VOID) +AGESA_STATUS agesawrapper_fchs3laterestore (void) { AGESA_STATUS status = AGESA_SUCCESS; @@ -571,7 +571,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (VOID) #ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) +AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h index 96ed141..3c07e58 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h @@ -79,11 +79,11 @@ AGESA_STATUS agesawrapper_amdinitmmio (void); uint32_t agesawrapper_amdinitcpuio (void); void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(VOID); -AGESA_STATUS agesawrapper_amdinitresume (VOID); -AGESA_STATUS agesawrapper_amds3laterestore (VOID); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitresume (void); +AGESA_STATUS agesawrapper_amds3laterestore (void); -AGESA_STATUS agesawrapper_fchs3earlyrestore (VOID); -AGESA_STATUS agesawrapper_fchs3laterestore (VOID); +AGESA_STATUS agesawrapper_fchs3earlyrestore (void); +AGESA_STATUS agesawrapper_fchs3laterestore (void); #endif diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 24e3ee7..9002858 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(VOID) +static AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; @@ -172,7 +172,7 @@ static AGESA_STATUS agesawrapper_amdinitcpuio(VOID) return Status; } -AGESA_STATUS agesawrapper_amdinitmmio(VOID) +AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; @@ -202,7 +202,7 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) return Status; } -UINT32 agesawrapper_amdinitreset(VOID) +UINT32 agesawrapper_amdinitreset(void) { AGESA_STATUS status = AGESA_SUCCESS; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -244,7 +244,7 @@ UINT32 agesawrapper_amdinitreset(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitearly(VOID) +AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -283,7 +283,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitpost(VOID) +AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -324,7 +324,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitenv(VOID) +AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -382,7 +382,7 @@ VOID * agesawrapper_getlateinitptr(int pick) return NULL; } -AGESA_STATUS agesawrapper_amdinitmid(VOID) +AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -414,7 +414,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitlate(VOID) +AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 9679fd9..369cc93 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(VOID) +static AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; @@ -172,7 +172,7 @@ static AGESA_STATUS agesawrapper_amdinitcpuio(VOID) return Status; } -AGESA_STATUS agesawrapper_amdinitmmio(VOID) +AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; @@ -202,7 +202,7 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) return Status; } -UINT32 agesawrapper_amdinitreset(VOID) +UINT32 agesawrapper_amdinitreset(void) { AGESA_STATUS status = AGESA_SUCCESS; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -244,7 +244,7 @@ UINT32 agesawrapper_amdinitreset(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitearly(VOID) +AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -283,7 +283,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitpost(VOID) +AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -324,7 +324,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitenv(VOID) +AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -382,7 +382,7 @@ VOID * agesawrapper_getlateinitptr(int pick) return NULL; } -AGESA_STATUS agesawrapper_amdinitmid(VOID) +AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -414,7 +414,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitlate(VOID) +AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 9f622be..8869b0b 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(VOID) +static AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; @@ -211,7 +211,7 @@ AGESA_STATUS agesawrapper_amdinitmmio ( return Status; } -UINT32 agesawrapper_amdinitreset(VOID) +UINT32 agesawrapper_amdinitreset(void) { AGESA_STATUS status = AGESA_SUCCESS; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -253,7 +253,7 @@ UINT32 agesawrapper_amdinitreset(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitearly(VOID) +AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -292,7 +292,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitpost(VOID) +AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -333,7 +333,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitenv(VOID) +AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -391,7 +391,7 @@ VOID * agesawrapper_getlateinitptr(int pick) return NULL; } -AGESA_STATUS agesawrapper_amdinitmid(VOID) +AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -423,7 +423,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitlate(VOID) +AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct;

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Patch merged into coreboot/master: 93d9f92 spi: Change spi_xfer to work in units of bytes instead of bits.
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 93d9f92cfbb214718e211aee71ac869c77f725ee Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 27 21:52:43 2014 -0700 spi: Change spi_xfer to work in units of bytes instead of bits. Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6175 for details. -gerrit

1 0

Patch merged into coreboot/master: 1e18735 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 1e187356e831583830a22cf051c792470d0440f5 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 27 20:37:03 2014 -0700 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6174 for details. -gerrit

1 0

Patch merged into coreboot/master: ab60510 spi flash: Organise options list
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit ab605108184e53964e6f6a2300a1983aa7166422 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 07:49:55 2014 +0300 spi flash: Organise options list Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6173 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6173 for details. -gerrit

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coreboot-gerrit July 2014