coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 01d40c6 google/panther: Force enable ASPM on PCIe Root Port 4
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6007 -gerrit commit 01d40c6b6a5d4ce006183255df2ed0b7e3356212 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Feb 19 15:05:15 2014 -0800 google/panther: Force enable ASPM on PCIe Root Port 4 BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 9fbe8e6..7cc3672 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/haswell register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + # Enable port coalescing register "pcie_port_coalesce" = "1"

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Patch set updated for coreboot: dec164f google/panther: acpi: Fix unstable fan behavior on boot + resume
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006 -gerrit commit dec164f9946a05fe52fa25dff45e8c6d19db86ef Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Feb 14 13:41:39 2014 -0800 google/panther: acpi: Fix unstable fan behavior on boot + resume FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone. Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF. BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase. Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/acpi/platform.asl | 3 + src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++-------- 2 files changed, 71 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl index e6aaf75..1c70d49 100644 --- a/src/mainboard/google/panther/acpi/platform.asl +++ b/src/mainboard/google/panther/acpi/platform.asl @@ -68,5 +68,8 @@ Method(_PTS,1) Method(_WAK,1) { + /* Initialize thermal defaults */ + \_TZ.THRM._INI () + Return(Package(){0,0}) } diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index e0ea2f5..ddf4473 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -61,6 +61,14 @@ Scope (\_TZ) Return (\PPKG ()) } + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 @@ -170,14 +178,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (\F0PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (1, \FLVL) + Store (\F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -191,14 +205,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (\F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (2, \FLVL) + Store (\F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -212,14 +232,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (\F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (3, \FLVL) + Store (\F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -233,14 +259,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (\F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -254,14 +286,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } }

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Patch set updated for coreboot: 5035de2 google/panther: Fix RW ramstage index
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6005 -gerrit commit 5035de2bd545303325124b88f7863b55e4e41c11 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Feb 14 13:22:30 2014 -0800 google/panther: Fix RW ramstage index Without this patch coreboot will always use the read-only version of ramstage, even if there is a read-write version available. BRANCH=panther BUG=chrome-os-partner:25870 TEST=Install different RO and RW version, check in cbmem log that coreboot's romstage and ramstage have different timestamps in their banners. Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186664 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/panther/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 4c507c7..db44396 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config VBOOT_RAMSTAGE_INDEX hex - default 0x2 + default 0x1 config MAINBOARD_DIR string

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Patch set updated for coreboot: 3d6bd14 google/panther: Add new thermal values
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6004 -gerrit commit 3d6bd1446920f4b67f1ca72f876d655717b52141 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Wed Feb 12 10:07:34 2014 -0800 google/panther: Add new thermal values Based on latest thermal report BUG=chrome-os-partner:24532 TEST=boot tested on panther BRANCH=panther Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d Signed-off-by: Mohammed Habibulla <moch(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186113 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/thermal.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h index 075e304..2d345c0 100644 --- a/src/mainboard/google/panther/thermal.h +++ b/src/mainboard/google/panther/thermal.h @@ -28,21 +28,21 @@ /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 40 #define FAN3_THRESHOLD_ON 50 -#define FAN3_PWM 0x6b +#define FAN3_PWM 0x5a /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 75 -#define FAN2_THRESHOLD_ON 83 -#define FAN2_PWM 0xcc +#define FAN2_THRESHOLD_OFF 58 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0xa6 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 86 -#define FAN1_THRESHOLD_ON 90 -#define FAN1_PWM 0xe5 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xc0 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 93 -#define FAN0_THRESHOLD_ON 96 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 #define FAN0_PWM 0xff /* Temperature which OS will shutdown at */

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Patch set updated for coreboot: 611a22b google/panther: Avoid shutdown when thermal sensor is unavailable
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6002 -gerrit commit 611a22b637195955ab86d6632e69e552a3578674 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 13 17:40:37 2014 -0800 google/panther: Avoid shutdown when thermal sensor is unavailable When the thermal sensor on Panther is unavailable (early on resume) it will return 0x80 which causes our AML thermal code to overflow, which causes the system to shut down. Instead, return a reasonable value in those cases so that the system will continue running until the sensor gets back on its feet. BUG=chrome-os-partner:24918 BRANCH=panther TEST=suspend_resume_test survived more than 100 iterations on Panther Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182369 Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/acpi/thermal.asl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index a6ea851..e0ea2f5 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -66,6 +66,11 @@ Scope (\_TZ) // Get CPU Temperature from PECI via SuperIO TMPIN3 Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + // Check for "no reading available" + If (LEqual (Local0, 0x80)) { + Return (CTOK (\F2ON)) + } + // Check for invalid readings If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { Return (CTOK (\F2ON))

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Patch set updated for coreboot: 47f4b50 google/panther: Re-read temperature if current reading would cause power-off
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6001 -gerrit commit 47f4b50a55a86137c8b98a5834de98f41d31ab04 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jan 10 16:06:03 2014 -0800 google/panther: Re-read temperature if current reading would cause power-off Sometimes the SuperIO seems to provide wrong readings, especially early on after a resume from suspend. This will cause the system to power off. If that happens, wait for 1s and read again, to make sure the high temperature value was not just a flaky read. BUG=chrome-os-partner:24918 BRANCH=panther TEST=Boot tested on Panther. Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182188 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/acpi/thermal.asl | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index d5b1290..a6ea851 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -61,7 +61,7 @@ Scope (\_TZ) Return (\PPKG ()) } - Method (_TMP, 0, Serialized) + Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) @@ -84,6 +84,31 @@ Scope (\_TZ) Return (CTOK (Local0)) } + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + Method (_AC0) { If (LLessEqual (\FLVL, 0)) { Return (CTOK (\F0OF))

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Patch set updated for coreboot: 7508282 google/panther: Disconnect speaker and mic in verb table
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6000 -gerrit commit 7508282e8d2209e0d71dcbc79b9b339c7574e0da Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jan 9 14:15:36 2014 -0800 google/panther: Disconnect speaker and mic in verb table There is no speaker and no builtin microphone in this system, hence disable them in the verb table. BRANCH=panther BUG=chrome-os-partner:24230 TEST=Boot Panther, see Microphone and Speaker disappear in Audio Settings Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182006 Reviewed-by: Dylan Reid <dgreid(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/hda_verb.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/panther/hda_verb.h b/src/mainboard/google/panther/hda_verb.h index ba0da1c..cec56eb 100644 --- a/src/mainboard/google/panther/hda_verb.h +++ b/src/mainboard/google/panther/hda_verb.h @@ -31,17 +31,17 @@ static const u32 mainboard_cim_verb_data[] = { /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ - 0x01271c10, - 0x01271d10, - 0x01271ea6, - 0x01271fb7, + /* Pin Complex (NID 0x12) DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471c10, // group 1, front left/right - 0x01471d01, // no connector, no jack detect - 0x01471e17, // speaker out, analog - 0x01471f90, // fixed function, internal + 0x01471cf0, + 0x01471d11, + 0x01471e11, + 0x01471f40, /* Pin Complex (NID 0x17) */ 0x01771cf0,

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Patch merged into coreboot/master: 577573f YABEL: Drop IO stubs that are (by own admission) never used
by gerrit＠coreboot.org 05 Jul '14

05 Jul '14

the following patch was just integrated into master: commit 577573fd5ec7df094da09c92ae454b261173ecbe Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jun 27 12:16:17 2014 +0200 YABEL: Drop IO stubs that are (by own admission) never used Change-Id: I90a120e64a5062493f64e3e8b48a75dae9342ec4 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/6178 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6178 for details. -gerrit

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Patch set updated for coreboot: 206861f Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 05 Jul '14

05 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5834 -gerrit commit 206861f4ad0537da863378c4725982ddbe2f85f4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: I129cf8349e9ee2ebd4a4d0f69a6d830bdbc4ebf0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 15 +++++++++++++++ src/northbridge/intel/haswell/mrccache.c | 8 ++------ src/northbridge/intel/sandybridge/mrccache.c | 8 ++------ src/soc/intel/baytrail/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 25 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 61c931e..3608a65 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -84,4 +84,19 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +#ifndef CONFIG_VIRTUAL_ROM_SIZE +#error "CONFIG_VIRTUAL_ROM_SIZE must be set." +#endif + +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { +#if defined(CONFIG_VIRTUAL_ROM_SIZE) + return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); +#else + return ((u32)p + flash->size); +#endif /* defined(CONFIG_VIRTUAL_ROM_SIZE) */ +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index f411db6..c6912e9 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -124,6 +119,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -228,7 +224,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 915f9d3..6fc266a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -123,6 +118,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -227,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index 0cc64f5..a880984 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -79,6 +73,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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Patch set updated for coreboot: b22b6cf southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
by Edward O'Callaghan 05 Jul '14

05 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6155 -gerrit commit b22b6cf3a5867e6a2cdd3fdb953eba55bc5b4d69 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 22:47:22 2014 +1000 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 41 ++++++++++++++++++----------------------- src/southbridge/amd/rs780/cmn.c | 40 ++++++++++++++++++---------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..05a47b3 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -47,7 +47,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -60,7 +60,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -191,12 +191,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -245,11 +245,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -278,17 +278,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -309,9 +305,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs690_set_tom(device_t nb_dev) { /* set TOM */ @@ -324,4 +320,3 @@ void rs690_set_tom(device_t nb_dev) nbmc_write_index(nb_dev, 0x1e, 0x38000000); #endif } - diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..497d1af 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -46,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -59,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -190,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -249,11 +249,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -319,17 +319,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -350,9 +346,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs780_set_tom(device_t nb_dev) { /* set TOM */

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coreboot-gerrit July 2014