coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: b5d3ded intel/lynxpoint: xhci: Revert suspend/resume changes
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6016 -gerrit commit b5d3ded813313f93dad92a79c10fb6e97b9350cd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Sep 25 14:08:16 2013 -0700 intel/lynxpoint: xhci: Revert suspend/resume changes I have been attempting to work around USB3 issues that appear in the kernel with hacks in the firmware, but this is resulting in more headaches in the kernel. Instead remove all the work that was being done at resume time and undo the change that was issuing a warm reset to all ports at suspend time. The bad device behavior will be dealt with at the kernel level to handle devices that get stuck in polling state after enable/disable sequence. BUG=chrome-os-partner:22754 BRANCH=falco,peppy,wolf,leon TEST=manual: suspend/resume with several misbehaving devices: Kingston USB3 Media Reader Transcend USB3 Media Reader Various ADATA USB3 drives Various Kingston USB3 sticks Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170107 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7) Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170578 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/usb_xhci.c | 94 +++--------------------------- 1 file changed, 9 insertions(+), 85 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index f6409b4..e091340 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -37,6 +37,8 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } +#ifdef __SMM__ + static int usb_xhci_port_count_usb3(device_t dev) { if (pch_is_lp()) { @@ -78,8 +80,6 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) #define XHCI_RESET_DELAY_US 1000 /* 1ms */ #define XHCI_RESET_TIMEOUT 100 /* 100ms */ -#ifdef __SMM__ - /* * 1) Wait until port is done polling * 2) If port is disconnected @@ -87,7 +87,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev) +static void usb_xhci_reset_usb3(device_t dev, int all) { u32 status, port_disabled; int timeout, port; @@ -127,7 +127,10 @@ static void usb_xhci_reset_usb3(device_t dev) continue; status = read32(portsc) & XHCI_USB3_PORTSC_PLS; /* Reset all or only disconnected ports */ - usb_xhci_reset_port_usb3(mem_base, port); + if (all || status == XHCI_PLSR_RXDETECT) + usb_xhci_reset_port_usb3(mem_base, port); + else + port_disabled |= 1 << port; } /* Wait for warm reset complete on all reset ports */ @@ -181,7 +184,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) write32(mem_base + 0x816c, reg32); /* Reset disconnected USB3 ports */ - usb_xhci_reset_usb3(dev); + usb_xhci_reset_usb3(dev, 0); /* Set MMIO 0x80e0[15] */ reg32 = read32(mem_base + 0x80e0); @@ -233,7 +236,7 @@ void usb_xhci_route_all(void) usb_ehci_disable(PCH_EHCI2_DEV); /* Reset and clear port change status */ - usb_xhci_reset_usb3(PCH_XHCI_DEV); + usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); } #else /* !__SMM__ */ @@ -285,81 +288,6 @@ static void usb_xhci_clock_gating(device_t dev) pci_write_config32(dev, 0xa4, reg32); } -/* Re-enable ports that are disabled */ -static void usb_xhci_enable_ports_usb3(device_t dev) -{ -#if CONFIG_FINALIZE_USB_ROUTE_XHCI - int port; - u32 portsc, status, disabled; - u32 mem_base = usb_xhci_mem_base(dev); - int port_count = usb_xhci_port_count_usb3(dev); - u8 port_reset = 0; - int timeout; - - if (!mem_base || !port_count) - return; - - /* Get port disable override map */ - disabled = pci_read_config32(dev, XHCI_USB3PDO); - - for (port = 0; port < port_count; port++) { - /* Skip overridden ports */ - if (disabled & (1 << port)) - continue; - portsc = mem_base + XHCI_USB3_PORTSC(port); - status = read32(portsc) & XHCI_USB3_PORTSC_PLS; - switch (status) { - case XHCI_PLSR_RXDETECT: - /* Clear change status */ - printk(BIOS_DEBUG, "usb_xhci reset status %d\n", port); - usb_xhci_reset_status_usb3(mem_base, port); - break; - case XHCI_PLSR_DISABLED: - default: - /* Reset port */ - printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port); - usb_xhci_reset_port_usb3(mem_base, port); - port_reset |= 1 << port; - break; - } - } - - if (!port_reset) - return; - - /* Wait for warm reset complete on all reset ports */ - for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { - int complete = 1; - for (port = 0; port < port_count; port++) { - /* Only check ports that were reset */ - if (!(port_reset & (1 << port))) - continue; - /* Check if warm reset is complete */ - status = read32(mem_base + XHCI_USB3_PORTSC(port)); - if (!(status & XHCI_USB3_PORTSC_WRC)) - complete = 0; - } - /* Check for warm reset complete in any port */ - if (complete) - break; - udelay(XHCI_RESET_DELAY_US); - } - - /* Enable ports that were reset */ - for (port = 0; port < port_count; port++) { - /* Only check ports that were reset */ - if (!(port_reset & (1 << port))) - continue; - /* Transition to enabled */ - portsc = mem_base + XHCI_USB3_PORTSC(port); - status = read32(portsc); - status &= ~(XHCI_USB3_PORTSC_PLS | XHCI_USB3_PORTSC_PED); - status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS; - write32(portsc, status); - } -#endif -} - static void usb_xhci_init(device_t dev) { u32 reg32; @@ -422,10 +350,6 @@ static void usb_xhci_init(device_t dev) reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); - - /* Enable ports that are disabled before returning to OS */ - if (acpi_is_wakeup_s3()) - usb_xhci_enable_ports_usb3(dev); } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,

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Patch set updated for coreboot: c0116ba google/panther: Disable DEVSLP for SATA
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999 -gerrit commit c0116ba192ad2276752ed02b9293301c2a58cde0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 8 15:20:59 2014 -0800 google/panther: Disable DEVSLP for SATA Some SSD modules don't support DEVSLP correctly due to their firmware. Since the power savings are minimal, don't use DEVSLP to prevent potential problems. Some of the symptoms are that sometimes this causes USB devices to not work properly. BUG=chrome-os-partner:23186, BRANCH=panther TEST=Boot tested on Panther Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181957 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index f461c58..9fbe8e6 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -55,6 +55,7 @@ chip northbridge/intel/haswell register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" register "sio_acpi_mode" = "0" register "sio_i2c0_voltage" = "0" # 3.3V

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Patch set updated for coreboot: 58b3121 google/panther: Disable power-failure gating for the PSON# signal
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996 -gerrit commit 58b3121e05c25330d45219c8c668a677152e9542 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Dec 11 11:09:45 2013 -0800 google/panther: Disable power-failure gating for the PSON# signal When the system loses AC power, the system will power back on automatically as soon as the AC power is reapplied. BUG=chrome-os-partner:24066 BRANCH=firmware-panther-4920.24.B TEST=boot tested on panther Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179537 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 1966a30..f461c58 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -111,6 +111,7 @@ chip northbridge/intel/haswell io 0x60 = 0x700 io 0x62 = 0x710 irq 0x70 = 0x09 + irq 0xf4 = 0x20 irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO

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Patch set updated for coreboot: 89ddd1f google/panther: Update Fan Policy
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5997 -gerrit commit 89ddd1f050ac6fba0ed9208d93652aebfadcbcaf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 6 14:48:35 2014 -0800 google/panther: Update Fan Policy Update fan policy according to Panther thermal report. CPU Temp. Readings | PWM -------------------+------ 40C | 42% 50C | 42% 83C | 80% 90C | 90% 96C | 100% BUG=chrome-os-partner:24532 BRANCH=panther TEST=boot tested on Panther Change-Id: I60f04d8b038c561b87dad505bbf058100119cc23 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181666 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/thermal.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h index 794065e..075e304 100644 --- a/src/mainboard/google/panther/thermal.h +++ b/src/mainboard/google/panther/thermal.h @@ -26,23 +26,23 @@ #define FAN4_PWM 0x00 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x6b /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 +#define FAN2_THRESHOLD_OFF 75 +#define FAN2_THRESHOLD_ON 83 +#define FAN2_PWM 0xcc /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 +#define FAN1_THRESHOLD_OFF 86 +#define FAN1_THRESHOLD_ON 90 +#define FAN1_PWM 0xe5 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 +#define FAN0_THRESHOLD_OFF 93 +#define FAN0_THRESHOLD_ON 96 #define FAN0_PWM 0xff /* Temperature which OS will shutdown at */

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Patch set updated for coreboot: 4996493 intel/lynxpoint: Allow to always route USB3 ports to XHCI
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6018 -gerrit commit 4996493decbd97a69eebcb3932f65c3f1747d19b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 17 17:00:26 2013 -0700 intel/lynxpoint: Allow to always route USB3 ports to XHCI This will make USB keyboards connected to USB3 ports work in libpayload on Beltino. BUG=chrome-os-partner:23396 BRANCH=none TEST=Use USB keyboard on Beltino in dev mode screen Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/173640 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/chip.h | 3 +++ src/southbridge/intel/lynxpoint/usb_xhci.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e47a031..cc2cda0 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config { * [24] = CLKOUT_ITPXDP */ uint32_t icc_clock_disable; + + /* Route USB ports to XHCI per default */ + uint8_t xhci_default; }; extern struct chip_operations southbridge_intel_lynxpoint_ops; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 997ef61..6c7bf04 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -26,6 +26,8 @@ #include <arch/io.h> #include "pch.h" +typedef struct southbridge_intel_lynxpoint_config config_t; + static u32 usb_xhci_mem_base(device_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev) u32 reg32; u16 reg16; u32 mem_base = usb_xhci_mem_base(dev); + config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); @@ -356,6 +359,9 @@ static void usb_xhci_init(device_t dev) /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); + } else if (config->xhci_default) { + /* Route all ports to XHCI */ + outb(0xca, 0xb2); } }

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Patch set updated for coreboot: 7ad8e31 google/panther: Set default interrupt value for Environmental Controller
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994 -gerrit commit 7ad8e3176e18702b81875a58fa5df07625d803fe Author: Mohammed Habibulla <moch(a)chromium.org> Date: Wed Nov 20 16:24:58 2013 -0800 google/panther: Set default interrupt value for Environmental Controller This writes the default value to the register, but it gets rid of the error that disturbs some of our tests: ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned (panther port of Ieab1c776b553c996a7d06e4059110943aaf41338) BRANCH=none BUG=chrome-os-partner:23945 TEST=boot test on Panther Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/177468 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)google.com> Tested-by: Mohammed Habibulla <moch(a)google.com> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 8bce691..1966a30 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/haswell device pnp 2e.4 on # Environment Controller io 0x60 = 0x700 io 0x62 = 0x710 + irq 0x70 = 0x09 irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO

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Patch set updated for coreboot: fb582b7 google/panther: Configure USB_ILIM_SEL to low
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5995 -gerrit commit fb582b783f2d2743c4635ba5536f96ab6cbfd704 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Wed Nov 20 16:30:09 2013 -0800 google/panther: Configure USB_ILIM_SEL to low (panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e) BUG=none BRANCH=none TEST=boot tested on Panther Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/177474 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)google.com> Tested-by: Mohammed Habibulla <moch(a)google.com> --- src/mainboard/google/panther/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h index 620acef..9951984 100644 --- a/src/mainboard/google/panther/gpio.h +++ b/src/mainboard/google/panther/gpio.h @@ -51,7 +51,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 25: UNUSED */ LP_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_OUT_HIGH, /* 28: USB_ILIM_SEL */ + LP_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ LP_GPIO_UNUSED, /* 29: UNUSED */ LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ LP_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */

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Patch set updated for coreboot: 568e753 google/panther: Disable LPSS I2C controllers
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992 -gerrit commit 568e7538a7f1b5746b02785677cfd05d7b3fca13 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Tue Oct 29 11:13:14 2013 -0700 google/panther: Disable LPSS I2C controllers There is nothing attached to these devices so we can disable them as well as the function 0 DMA controller. Also remove the EC SMI/SCI mappings since there is no EC. (panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87) BUG=chrome-os-partner:23563 TEST=none BRANCH=panther Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174944 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 95f1084..39d4f06 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -46,11 +46,9 @@ chip northbridge/intel/haswell # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" + register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" + register "gpe0_en_2" = "0x00000000" register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" @@ -73,9 +71,9 @@ chip northbridge/intel/haswell device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 device pci 15.3 off end # GSPI0 device pci 15.4 off end # GSPI1 device pci 15.5 off end # UART0

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Patch set updated for coreboot: 65df5a5 google/panther: Make sure the S5 power status is on track
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5993 -gerrit commit 65df5a53f1ba624dc7a6e8cb420d373f452e8eaa Author: Mohammed Habibulla <moch(a)chromium.org> Date: Tue Nov 12 13:29:43 2013 -0800 google/panther: Make sure the S5 power status is on track (panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6) BUG=none BRANCH=none TEST=boot test on panther Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/176563 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 39d4f06..8bce691 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/haswell device pnp 2e.4 on # Environment Controller io 0x60 = 0x700 io 0x62 = 0x710 + irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO io 0x60 = 0x720

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Patch set updated for coreboot: f7f0273 google/panther: acpi: Fix unstable fan behavior on boot + resume
by Paul Menzel 06 Jul '14

06 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006 -gerrit commit f7f02733cdbccc4c07b635f5b494060621fc908f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Feb 14 13:41:39 2014 -0800 google/panther: acpi: Fix unstable fan behavior on boot + resume FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone. Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF. BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase. Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/panther/acpi/platform.asl | 3 + src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++-------- 2 files changed, 71 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl index e6aaf75..1c70d49 100644 --- a/src/mainboard/google/panther/acpi/platform.asl +++ b/src/mainboard/google/panther/acpi/platform.asl @@ -68,5 +68,8 @@ Method(_PTS,1) Method(_WAK,1) { + /* Initialize thermal defaults */ + \_TZ.THRM._INI () + Return(Package(){0,0}) } diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index e0ea2f5..ddf4473 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -61,6 +61,14 @@ Scope (\_TZ) Return (\PPKG ()) } + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 @@ -170,14 +178,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (\F0PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (1, \FLVL) + Store (\F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -191,14 +205,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (\F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (2, \FLVL) + Store (\F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -212,14 +232,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (\F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (3, \FLVL) + Store (\F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -233,14 +259,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (\F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } } @@ -254,14 +286,20 @@ Scope (\_TZ) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) + If (_STA ()) { + Store (4, \FLVL) + Store (\F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } } }

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coreboot-gerrit July 2014