coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: c80fb8e drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5973 -gerrit commit c80fb8e25ac85d3ff2662e151af448997fddc1cd Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

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Patch set updated for coreboot: ff45d61 intel: Make monotonic timer a first class citizen
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6135 -gerrit commit ff45d613dacecb395658e92d3a58061e2687b39a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_206ax/Kconfig | 1 + src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/bayleybay_fsp/Kconfig | 1 + src/northbridge/intel/nehalem/Kconfig | 1 + 7 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..043320c 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..8185d3a 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..afd155a 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..7272cbc 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..18aa0e3 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

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Patch set updated for coreboot: eb57887 intel: Make monotonic timer a first class citizen
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6176 -gerrit commit eb578876656e4608309084469261f6aacb693df1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I900d9d7de710403e37b6bac10582bb42aba7d733 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_206ax/Kconfig | 1 + src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/bayleybay_fsp/Kconfig | 1 + src/northbridge/intel/nehalem/Kconfig | 1 + 7 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..043320c 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..8185d3a 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..afd155a 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..7272cbc 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..18aa0e3 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

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Patch set updated for coreboot: 69ee5ec drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6177 -gerrit commit 69ee5ecd2a5e6f0e99a64b24b74a1096323160a7 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Icddb9953d7065d9ef789f941ea1a93ce9305a33a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

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New patch to review for coreboot: 8de2843 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6177 -gerrit commit 8de284388fb3eeb7e5c743b33183148dcf6781aa Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Icddb9953d7065d9ef789f941ea1a93ce9305a33a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

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New patch to review for coreboot: b087550 intel: Make monotonic timer a first class citizen
by David Hendricks 04 Jul '14

04 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6176 -gerrit commit b0875503473c95cfc10e20b381f5f0ea5aef51d2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I900d9d7de710403e37b6bac10582bb42aba7d733 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_206ax/Kconfig | 1 + src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/intel/bayleybay_fsp/Kconfig | 1 + src/northbridge/intel/nehalem/Kconfig | 1 + 7 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..043320c 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..8185d3a 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..afd155a 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..0482dfe 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..7272cbc 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..18aa0e3 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

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New patch to review for coreboot: 1e79ef7 spi: Change spi_xfer to work in units of bytes instead of bits.
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6175 -gerrit commit 1e79ef75dcd108156fb5a646eb8781482a1780de Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 27 21:52:43 2014 -0700 spi: Change spi_xfer to work in units of bytes instead of bits. Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/samsung/exynos5420/spi.c | 6 ++---- src/drivers/spi/spi_flash.c | 6 +++--- src/ec/google/chromeec/ec_spi.c | 4 ++-- src/include/spi-generic.h | 24 +++++++----------------- src/soc/intel/baytrail/spi.c | 15 +++++---------- src/soc/intel/fsp_baytrail/spi.c | 15 +++++---------- src/southbridge/amd/agesa/hudson/spi.c | 19 ++++++------------- src/southbridge/amd/cimx/sb800/spi.c | 7 ++----- src/southbridge/intel/common/spi.c | 15 +++++---------- 9 files changed, 37 insertions(+), 74 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 5c546cc..46b9ced 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -258,15 +258,13 @@ int spi_claim_bus(struct spi_slave *slave) return 0; } -int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, - void *din, unsigned int bitsin) +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int out_bytes, + void *din, unsigned int in_bytes) { - unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; uint8_t *out_ptr = (uint8_t *)dout, *in_ptr = (uint8_t *)din; int offset, todo, len; int ret = 0; - ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); len = MAX(out_bytes, in_bytes); /* diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 8232220..ed1164c 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -27,7 +27,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd) int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) { - int ret = spi_xfer(spi, &cmd, 8, response, len * 8); + int ret = spi_xfer(spi, &cmd, sizeof(cmd), response, len); if (ret) printk(BIOS_WARNING, "SF: Failed to send command %02x: %d\n", cmd, ret); @@ -37,7 +37,7 @@ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, void *data, size_t data_len) { - int ret = spi_xfer(spi, cmd, cmd_len * 8, data, data_len * 8); + int ret = spi_xfer(spi, cmd, cmd_len, data, data_len); if (ret) { printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n", data_len, ret); @@ -54,7 +54,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, memcpy(buff, cmd, cmd_len); memcpy(buff + cmd_len, data, data_len); - ret = spi_xfer(spi, buff, (cmd_len + data_len) * 8, NULL, 0); + ret = spi_xfer(spi, buff, cmd_len + data_len, NULL, 0); if (ret) { printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n", data_len, ret); diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 012a4ca..d6b7b0c 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -31,8 +31,8 @@ static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, int rv; spi_claim_bus(slave); - rv = spi_xfer(slave, write_bytes, write_size * 8, read_bytes, - read_size * 8); + rv = spi_xfer(slave, write_bytes, write_size, read_bytes, + read_size); spi_release_bus(slave); if (rv != 0) { diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index b7a14f9..6c62de6 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -120,27 +120,17 @@ void spi_release_bus(struct spi_slave *slave); /*----------------------------------------------------------------------- * SPI transfer * - * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks - * "bitlen" bits in the SPI MISO port. That's just the way SPI works. - * - * The source of the outgoing bits is the "dout" parameter and the - * destination of the input bits is the "din" parameter. Note that "dout" - * and "din" can point to the same memory location, in which case the - * input data overwrites the output data (since both are buffered by - * temporary variables, this is OK). - * * spi_xfer() interface: * slave: The SPI slave which will be sending/receiving the data. - * dout: Pointer to a string of bits to send out. The bits are - * held in a byte array and are sent MSB first. - * bitsout: How many bits to write. - * din: Pointer to a string of bits that will be filled in. - * bitsin: How many bits to read. + * dout: Pointer to a string of bytes to send out. + * bytesout: How many bytes to write. + * din: Pointer to a string of bytes that will be filled in. + * bytesin: How many bytes to read. * * Returns: 0 on success, not 0 on failure */ -int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, - void *din, unsigned int bitsin); +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, + void *din, unsigned int bytesin); /*----------------------------------------------------------------------- * Determine if a SPI chipselect is valid. @@ -196,7 +186,7 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) dout[0] = byte; dout[1] = 0; - ret = spi_xfer(slave, dout, 16, din, 16); + ret = spi_xfer(slave, dout, 2, din, 2); return ret < 0 ? ret : din[1]; } diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index d75caca..b649f53 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -500,7 +500,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) } int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int bytesout, void *din, unsigned int bytesin) { uint16_t control; int16_t opcode_index; @@ -508,26 +508,21 @@ int spi_xfer(struct spi_slave *slave, const void *dout, int status; spi_transaction trans = { - dout, bitsout / 8, - din, bitsin / 8, + dout, bytesout, + din, bytesin, 0xff, 0xff, 0 }; /* There has to always at least be an opcode. */ - if (!bitsout || !dout) { + if (!bytesout || !dout) { printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); return -1; } /* Make sure if we read something we have a place to put it. */ - if (bitsin != 0 && !din) { + if (bytesin != 0 && !din) { printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); return -1; } - /* Right now we don't support writing partial bytes. */ - if (bitsout % 8 || bitsin % 8) { - printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); - return -1; - } if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 5e8da95..50f1123 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -498,7 +498,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) } int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int bytesout, void *din, unsigned int bytesin) { uint16_t control; int16_t opcode_index; @@ -506,26 +506,21 @@ int spi_xfer(struct spi_slave *slave, const void *dout, int status; spi_transaction trans = { - dout, bitsout / 8, - din, bitsin / 8, + dout, bytesout, + din, bytesin, 0xff, 0xff, 0 }; /* There has to always at least be an opcode. */ - if (!bitsout || !dout) { + if (!bytesout || !dout) { printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); return -1; } /* Make sure if we read something we have a place to put it. */ - if (bitsin != 0 && !din) { + if (bytesin != 0 && !din) { printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); return -1; } - /* Right now we don't support writing partial bytes. */ - if (bitsout % 8 || bitsin % 8) { - printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); - return -1; - } if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index c19d1a0..720b26f 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -87,21 +87,14 @@ void spi_init(void) } int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int bytesout, void *din, unsigned int bytesin) { /* First byte is cmd which can not being sent through FIFO. */ - uint8_t cmd = *(uint8_t *)dout++; - uint8_t readoffby1; -#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - uint8_t readwrite; -#endif - uint8_t bytesout, bytesin; - uint8_t count; - - bitsout -= 8; - bytesout = bitsout / 8; - bytesin = bitsin / 8; + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 count; + bytesout--; readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE @@ -110,7 +103,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, spi_write(0x1E, 6); spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ #else - readwrite = (bytesin + readoffby1) << 4 | bytesout; + u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; spi_write(SPI_REG_CNTRL01, readwrite); #endif spi_write(SPI_REG_OPCODE, cmd); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d059f5e..a46349e 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -57,18 +57,15 @@ void spi_init() } int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int bytesout, void *din, unsigned int bytesin) { /* First byte is cmd which can not being sent through FIFO. */ u8 cmd = *(u8 *)dout++; u8 readoffby1; u8 readwrite; - u8 bytesout, bytesin; u8 count; - bitsout -= 8; - bytesout = bitsout / 8; - bytesin = bitsin / 8; + bytesout--; readoffby1 = bytesout ? 0 : 1; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 14d2f54..76fd226 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -551,7 +551,7 @@ static int spi_is_multichip (void) } int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int bytesout, void *din, unsigned int bytesin) { uint16_t control; int16_t opcode_index; @@ -559,26 +559,21 @@ int spi_xfer(struct spi_slave *slave, const void *dout, int status; spi_transaction trans = { - dout, bitsout / 8, - din, bitsin / 8, + dout, bytesout, + din, bytesin, 0xff, 0xff, 0 }; /* There has to always at least be an opcode. */ - if (!bitsout || !dout) { + if (!bytesout || !dout) { printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); return -1; } /* Make sure if we read something we have a place to put it. */ - if (bitsin != 0 && !din) { + if (bytesin != 0 && !din) { printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); return -1; } - /* Right now we don't support writing partial bytes. */ - if (bitsout % 8 || bitsin % 8) { - printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); - return -1; - } if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1;

1 0

New patch to review for coreboot: 9cd4276 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6174 -gerrit commit 9cd4276852a24a320e9875fdec57c5975a885182 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 27 20:37:03 2014 -0700 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/spi.c | 2 +- src/cpu/samsung/exynos5420/spi.c | 3 +-- src/drivers/elog/elog.c | 2 +- src/drivers/intel/fsp/fastboot_cache.c | 2 +- src/drivers/spi/spi_flash.c | 5 ++--- src/ec/google/chromeec/ec_spi.c | 9 ++------- src/include/spi-generic.h | 5 +---- src/include/spi_flash.h | 3 +-- src/northbridge/intel/haswell/mrccache.c | 2 +- src/northbridge/intel/sandybridge/mrccache.c | 2 +- src/soc/intel/baytrail/nvm.c | 2 +- src/soc/intel/baytrail/spi.c | 3 +-- src/soc/intel/fsp_baytrail/nvm.c | 2 +- src/soc/intel/fsp_baytrail/spi.c | 3 +-- src/southbridge/amd/agesa/hudson/spi.c | 3 +-- src/southbridge/amd/cimx/sb800/spi.c | 3 +-- src/southbridge/intel/common/spi.c | 3 +-- 17 files changed, 19 insertions(+), 35 deletions(-) diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c index f4ffa62..5631053 100644 --- a/src/cpu/amd/agesa/spi.c +++ b/src/cpu/amd/agesa/spi.c @@ -28,7 +28,7 @@ void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) struct spi_flash *flash; spi_init(); - flash = spi_flash_probe(0, 0, 0, 0); + flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); /* Dont make flow stop. */ diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 1c60378..5c546cc 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -79,8 +79,7 @@ void spi_init(void) printk(BIOS_INFO, "Exynos SPI driver initiated.\n"); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ASSERT(bus >= 0 && bus < 3); return &(exynos_spi_slaves[bus].slave); diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 8816974..227bd82 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -548,7 +548,7 @@ int elog_init(void) /* Prepare SPI */ spi_init(); - elog_spi = spi_flash_probe(0, 0, 0, 0); + elog_spi = spi_flash_probe(0, 0); if (!elog_spi) { printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); return -1; diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index b9a6e33..64982d8 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -185,7 +185,7 @@ void update_mrc_cache(void *unused) /* 1. use spi_flash_probe() to find the flash, then... */ spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + struct spi_flash *flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..8232220 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -252,15 +252,14 @@ static struct { }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) -struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode) +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) { struct spi_slave *spi; struct spi_flash *flash = NULL; int ret, i, shift; u8 idcode[IDCODE_LEN], *idp; - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + spi = spi_setup_slave(bus, cs); if (!spi) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); return NULL; diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index cc2c9ba..012a4ca 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -23,8 +23,6 @@ #include "ec.h" #include "ec_commands.h" -#define CROSEC_SPI_SPEED (500000) - static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, uint8_t *read_bytes, size_t read_size, void *context) @@ -48,12 +46,9 @@ static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, int google_chromeec_command(struct chromeec_command *cec_command) { static struct spi_slave *slave = NULL; - if (!slave) { + if (!slave) slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, - CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP, - CROSEC_SPI_SPEED, - SPI_READ_FLAG | SPI_WRITE_FLAG); - } + CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP); return crosec_command_proto(cec_command, crosec_spi_io, slave); } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 6cdb87a..b7a14f9 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -84,14 +84,11 @@ void spi_init(void); * * bus: Bus ID of the slave chip. * cs: Chip select ID of the slave chip on the specified bus. - * max_hz: Maximum SCK rate in Hz. - * mode: Clock polarity, clock phase and other parameters. * * Returns: A spi_slave reference that can be used in subsequent SPI * calls, or NULL if one or more of the parameters are not supported. */ -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs); /*----------------------------------------------------------------------- * Claim the bus and prepare it for communication with a given slave. diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 8e51471..61c931e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -64,8 +64,7 @@ struct spi_flash { size_t len); }; -struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode); +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs); static inline int spi_flash_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 88dbf7f..f411db6 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -192,7 +192,7 @@ static void update_mrc_cache(void *unused) // 1. use spi_flash_probe() to find the flash, then spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + struct spi_flash *flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return; diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5d7c49b..915f9d3 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -191,7 +191,7 @@ static void update_mrc_cache(void *unused) // 1. use spi_flash_probe() to find the flash, then spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + struct spi_flash *flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return; diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index 843bc5a..0cc64f5 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -37,7 +37,7 @@ static int nvm_init(void) return 0; spi_init(); - flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 5ac42c2..d75caca 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -272,8 +272,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave)); diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index dab87ae..0224463 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -38,7 +38,7 @@ static int nvm_init(void) return 0; spi_init(); - flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + flash = spi_flash_probe(0, 0); if (!flash) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index ddec2e0..5e8da95 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -270,8 +270,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave)); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 573dd3d..c19d1a0 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -172,8 +172,7 @@ void spi_cs_deactivate(struct spi_slave *slave) { } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct spi_slave *slave = malloc(sizeof(*slave)); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index a1cdf55..d059f5e 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -164,8 +164,7 @@ void spi_cs_deactivate(struct spi_slave *slave) { } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct spi_slave *slave = malloc(sizeof(*slave)); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 51586cc..14d2f54 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -299,8 +299,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave));

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New patch to review for coreboot: 2e71248 spi flash: Organise options list
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6173 -gerrit commit 2e71248f3e3cac34986321108725b400d4183051 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 07:49:55 2014 +0300 spi flash: Organise options list Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/spi/Kconfig | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 5135dfb..6b31053 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -33,6 +33,20 @@ config SPI_FLASH_SMM help Select this option if you want SPI flash support in SMM. +config SPI_FLASH_NO_FAST_READ + bool "Disable Fast Read command" + default n + help + Select this option if your setup requires to avoid "fast read"s + from the SPI flash parts. + +config SPI_FLASH_ADESTO + bool + default y + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Adesto Technologies. + config SPI_FLASH_AMIC bool default y @@ -47,6 +61,13 @@ config SPI_FLASH_EON Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON. +config SPI_FLASH_GIGADEVICE + bool + default y + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Gigadevice. + config SPI_FLASH_MACRONIX bool default y @@ -82,25 +103,4 @@ config SPI_FLASH_WINBOND Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. -config SPI_FLASH_NO_FAST_READ - bool "Disable Fast Read command" - default n - help - Select this option if your setup requires to avoid "fast read"s - from the SPI flash parts. - -config SPI_FLASH_GIGADEVICE - bool - default y - help - Select this option if your chipset driver needs to store certain - data in the SPI flash and your SPI flash is made by Gigadevice. - -config SPI_FLASH_ADESTO - bool - default y - help - Select this option if your chipset driver needs to store certain - data in the SPI flash and your SPI flash is made by Adesto Technologies. - endif # SPI_FLASH

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Patch set updated for coreboot: e2294c2 gizmosphere/gizmo: Move support of SPD data in CBFS
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5690 -gerrit commit e2294c268e27fa4e69176ef31ae6ec737e04652e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 16:40:15 2014 +0300 gizmosphere/gizmo: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 4 ++ src/device/Makefile.inc | 2 +- src/device/dram/Makefile.inc | 1 + src/device/dram/spd_cache.c | 68 ++++++++++++++++++++++ src/include/spd_cache.h | 30 ++++++++++ src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 60 +------------------ src/mainboard/gizmosphere/gizmo/Kconfig | 1 + src/mainboard/gizmosphere/gizmo/Makefile.inc | 1 - src/northbridge/amd/agesa/def_callouts.c | 27 ++++++++- src/northbridge/amd/agesa/def_callouts.h | 2 + .../amd/agesa/family14/fam14_callouts.h | 2 - 11 files changed, 133 insertions(+), 65 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index ab7a577..52d12c7 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -191,6 +191,10 @@ config MULTIPLE_VGA_ADAPTERS bool default n +config SPD_CACHE + bool + default n + config PCI bool default n diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 7ef7d2f..813ce7e 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -17,7 +17,7 @@ ramstage-y += smbus_ops.c romstage-y += device_romstage.c romstage-$(CONFIG_PCI) += pci_early.c -subdirs-y += oprom +subdirs-y += oprom dram ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc new file mode 100644 index 0000000..05f440b --- /dev/null +++ b/src/device/dram/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c new file mode 100644 index 0000000..0032f32 --- /dev/null +++ b/src/device/dram/spd_cache.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <device/dram/ddr3.h> +#include <spd_cache.h> +#include <stdint.h> +#include <string.h> + +#define SPD_SIZE 128 +#define SPD_CRC_HI 127 +#define SPD_CRC_LO 126 + +int read_spd_from_cbfs(u8 *buf, int idx) +{ + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx + 1) * SPD_SIZE; + + printk(BIOS_DEBUG, "read SPD\n"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ", i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h new file mode 100644 index 0000000..64e3aab --- /dev/null +++ b/src/include/spd_cache.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SPD_CACHE_H_ +#define _SPD_CACHE_H_ + +#include <stdint.h> + +#if IS_ENABLED(CONFIG_SPD_CACHE) +int read_spd_from_cbfs(u8 *buf, int idx); +#else +static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; } +#endif + +#endif diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 2efc459..da21f57 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,13 +23,6 @@ #include "heapManager.h" #include "SB800.h" #include <stdlib.h> -#include <cbfs.h> -#include <string.h> -#include <device/dram/ddr3.h> - -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -40,7 +32,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd_from_cbfs }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -51,56 +43,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; -#ifdef __PRE_RAM__ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, - &spd_file_len); - if (!spd_file) - die("file [spd.bin] not found in CBFS"); - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - memcpy((char*)info->Buffer, spd_file, SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); - - if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0)) - || (info->Buffer[SPD_CRC_LO] != (crc & 0xff)) - || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); - info->Buffer[SPD_CRC_LO] = crc & 0xff; - info->Buffer[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ",i); - printk(BIOS_WARNING, "%02x ", info->Buffer[i]); - } - printk(BIOS_WARNING, "\n"); - } - Status = AGESA_SUCCESS; -#else - Status = AGESA_UNSUPPORTED; -#endif - - return Status; -} - /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 6f57f4b..fc34f12 100755 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA + select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 3f4224b..d18c372 100755 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c -romstage-y += ../../../device/dram/ddr3.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index f813c49..1184050 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,14 +18,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> +#include <spd_cache.h> + #include "AGESA.h" #include "amdlib.h" #include "Ids.h" #include "agesawrapper.h" -#include <cbfs.h> #include "def_callouts.h" - AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINTN i; @@ -113,3 +115,24 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } #endif + +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h index 033abc3..b679bae 100644 --- a/src/northbridge/amd/agesa/def_callouts.h +++ b/src/northbridge/amd/agesa/def_callouts.h @@ -65,6 +65,8 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index c885761..f58441a 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -26,7 +26,5 @@ /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); - #endif /* CALLOUTS_AMD_AGESA_FAM14_H */

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coreboot-gerrit July 2014