coreboot-gerrit July 2014

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Patch set updated for coreboot: 338f18f gizmosphere/gizmo: Move support of SPD data in CBFS
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5690 -gerrit commit 338f18f14c9184ba0e34287c64790c8f64fd67ee Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 16:40:15 2014 +0300 gizmosphere/gizmo: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 4 ++ src/device/Makefile.inc | 2 +- src/device/dram/Makefile.inc | 1 + src/device/dram/spd_cache.c | 68 ++++++++++++++++++++++ src/include/spd.h | 6 ++ src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 60 +------------------ src/mainboard/gizmosphere/gizmo/Kconfig | 1 + src/mainboard/gizmosphere/gizmo/Makefile.inc | 1 - src/northbridge/amd/agesa/def_callouts.c | 27 ++++++++- src/northbridge/amd/agesa/def_callouts.h | 2 + .../amd/agesa/family14/fam14_callouts.h | 2 - 11 files changed, 109 insertions(+), 65 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index ab7a577..52d12c7 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -191,6 +191,10 @@ config MULTIPLE_VGA_ADAPTERS bool default n +config SPD_CACHE + bool + default n + config PCI bool default n diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 7ef7d2f..813ce7e 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -17,7 +17,7 @@ ramstage-y += smbus_ops.c romstage-y += device_romstage.c romstage-$(CONFIG_PCI) += pci_early.c -subdirs-y += oprom +subdirs-y += oprom dram ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc new file mode 100644 index 0000000..05f440b --- /dev/null +++ b/src/device/dram/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c new file mode 100644 index 0000000..1d6fc98 --- /dev/null +++ b/src/device/dram/spd_cache.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <device/dram/ddr3.h> +#include <spd.h> +#include <stdint.h> +#include <string.h> + +#define SPD_SIZE 128 +#define SPD_CRC_HI 127 +#define SPD_CRC_LO 126 + +int read_spd_from_cbfs(u8 *buf, int idx) +{ + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx + 1) * SPD_SIZE; + + printk(BIOS_DEBUG, "read SPD\n"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ", i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/include/spd.h b/src/include/spd.h index 2b07fb1..d84bbd0 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -237,4 +237,10 @@ enum spd_memory_type { #define RC62 62 #define RC63 63 +#if IS_ENABLED(CONFIG_SPD_CACHE) +int read_spd_from_cbfs(u8 *buf, int idx); +#else +static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; } +#endif + #endif diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 2efc459..da21f57 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,13 +23,6 @@ #include "heapManager.h" #include "SB800.h" #include <stdlib.h> -#include <cbfs.h> -#include <string.h> -#include <device/dram/ddr3.h> - -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -40,7 +32,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd_from_cbfs }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -51,56 +43,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; -#ifdef __PRE_RAM__ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, - &spd_file_len); - if (!spd_file) - die("file [spd.bin] not found in CBFS"); - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - memcpy((char*)info->Buffer, spd_file, SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); - - if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0)) - || (info->Buffer[SPD_CRC_LO] != (crc & 0xff)) - || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); - info->Buffer[SPD_CRC_LO] = crc & 0xff; - info->Buffer[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ",i); - printk(BIOS_WARNING, "%02x ", info->Buffer[i]); - } - printk(BIOS_WARNING, "\n"); - } - Status = AGESA_SUCCESS; -#else - Status = AGESA_UNSUPPORTED; -#endif - - return Status; -} - /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 6f57f4b..fc34f12 100755 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA + select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 3f4224b..d18c372 100755 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c -romstage-y += ../../../device/dram/ddr3.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index f813c49..7ae2afd 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,14 +18,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> +#include <spd.h> + #include "AGESA.h" #include "amdlib.h" #include "Ids.h" #include "agesawrapper.h" -#include <cbfs.h> #include "def_callouts.h" - AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINTN i; @@ -113,3 +115,24 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } #endif + +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h index 033abc3..b679bae 100644 --- a/src/northbridge/amd/agesa/def_callouts.h +++ b/src/northbridge/amd/agesa/def_callouts.h @@ -65,6 +65,8 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index c885761..f58441a 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -26,7 +26,5 @@ /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); - #endif /* CALLOUTS_AMD_AGESA_FAM14_H */

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New patch to review for coreboot: 8372bf7 Drop redundant select CACHE_AS_RAM
by Kyösti Mälkki 03 Jul '14

03 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6172 -gerrit commit 8372bf78369b67bc53d27106d9793cc093c57b9f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 3 12:11:05 2014 +0300 Drop redundant select CACHE_AS_RAM The few remaining boards without CAR override this with select ROMCC. Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/geode_gx2/Kconfig | 1 - src/cpu/amd/geode_lx/Kconfig | 1 - src/cpu/amd/socket_754/Kconfig | 1 - src/cpu/amd/socket_939/Kconfig | 1 - src/cpu/amd/socket_940/Kconfig | 1 - src/cpu/amd/socket_AM2/Kconfig | 1 - src/cpu/amd/socket_AM2r2/Kconfig | 1 - src/cpu/amd/socket_AM3/Kconfig | 1 - src/cpu/amd/socket_ASB2/Kconfig | 1 - src/cpu/amd/socket_C32/Kconfig | 1 - src/cpu/amd/socket_F/Kconfig | 1 - src/cpu/amd/socket_F_1207/Kconfig | 1 - src/cpu/amd/socket_S1G1/Kconfig | 1 - src/cpu/intel/slot_1/Kconfig | 1 - src/cpu/intel/socket_441/Kconfig | 1 - src/cpu/intel/socket_BGA956/Kconfig | 1 - src/cpu/intel/socket_FC_PGA370/Kconfig | 1 - src/cpu/intel/socket_PGA370/Kconfig | 1 - src/cpu/intel/socket_mFCBGA479/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 1 - src/cpu/intel/socket_mPGA479M/Kconfig | 1 - src/cpu/intel/socket_rPGA988B/Kconfig | 1 - src/cpu/intel/socket_rPGA989/Kconfig | 1 - src/cpu/via/c7/Kconfig | 1 - src/cpu/via/nano/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/tyan/s2735/Kconfig | 1 - 28 files changed, 28 deletions(-) diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index baa1a7c..88fdc8f 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -27,7 +27,6 @@ if CPU_AMD_GEODE_GX2 config CPU_SPECIFIC_OPTIONS def_bool y - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 39890c4..b700e0c 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -8,7 +8,6 @@ if CPU_AMD_GEODE_LX config CPU_SPECIFIC_OPTIONS def_bool y - select CACHE_AS_RAM select TSC_MONOTONIC_TIMER config DCACHE_RAM_BASE diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index e77ac42..3ddaea0 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -6,7 +6,6 @@ if CPU_AMD_SOCKET_754 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig index 4c6cc2b..6217072 100644 --- a/src/cpu/amd/socket_939/Kconfig +++ b/src/cpu/amd/socket_939/Kconfig @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_939 bool select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 051eadc..1ca23e7 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS config CPU_ADDR_BITS diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig index c8c79bb..7da5a4d 100644 --- a/src/cpu/amd/socket_AM2/Kconfig +++ b/src/cpu/amd/socket_AM2/Kconfig @@ -4,7 +4,6 @@ config CPU_AMD_SOCKET_AM2 # Opteron K8 1G HT support select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index 8379063..8c260ea 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM2R2 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS if CPU_AMD_SOCKET_AM2R2 diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index 4069bfd..3c7433f 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM3 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS if CPU_AMD_SOCKET_AM3 diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index a73a29b..167cf2f 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_ASB2 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS if CPU_AMD_SOCKET_ASB2 diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 97b37ee..615387c 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_C32_NON_AGESA select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS if CPU_AMD_SOCKET_C32_NON_AGESA diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig index 6d94f55..6c2fafa 100644 --- a/src/cpu/amd/socket_F/Kconfig +++ b/src/cpu/amd/socket_F/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_F select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index c36c33c..a69a65a 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207 bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS if CPU_AMD_SOCKET_F_1207 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 2943b91..e714200 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM select X86_AMD_FIXED_MTRRS config CPU_SOCKET_TYPE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index e3e6fb2..57076d7 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,6 @@ if CPU_INTEL_SLOT_1 config SLOT_SPECIFIC_OPTIONS # dummy def_bool y - select CACHE_AS_RAM select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X select CPU_INTEL_MODEL_68X diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index f73c8a9..2269190 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_106CX select MMX select SSE - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 40f82af..4dd5a60 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X - select CACHE_AS_RAM select MMX select SSE diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig index a0c2df6..f8ea0f9 100644 --- a/src/cpu/intel/socket_FC_PGA370/Kconfig +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -23,7 +23,6 @@ config CPU_INTEL_SOCKET_FC_PGA370 select CPU_INTEL_MODEL_68X select MMX select SSE - select CACHE_AS_RAM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index c8a4b59..ea2de87 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -22,7 +22,6 @@ config CPU_INTEL_SOCKET_PGA370 select CPU_INTEL_MODEL_6XX select MMX select UDELAY_TSC - select CACHE_AS_RAM if CPU_INTEL_SOCKET_PGA370 diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig index d2ceabe..5576623 100644 --- a/src/cpu/intel/socket_mFCBGA479/Kconfig +++ b/src/cpu/intel/socket_mFCBGA479/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_MFCBGA479 select CPU_INTEL_MODEL_6BX select MMX select SSE - select CACHE_AS_RAM diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 2d241cf..b67f5e6 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6FX select MMX select SSE - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig index 4be39b5..8598eaf 100644 --- a/src/cpu/intel/socket_mPGA479M/Kconfig +++ b/src/cpu/intel/socket_mPGA479M/Kconfig @@ -6,4 +6,3 @@ config CPU_INTEL_SOCKET_MPGA479M select CPU_INTEL_MODEL_F2X select MMX select SSE - select CACHE_AS_RAM diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig index 7e74f89..471e522 100644 --- a/src/cpu/intel/socket_rPGA988B/Kconfig +++ b/src/cpu/intel/socket_rPGA988B/Kconfig @@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select MMX select SSE - select CACHE_AS_RAM config CACHE_MRC_BIN bool diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig index 11ac25f..83d29e7 100644 --- a/src/cpu/intel/socket_rPGA989/Kconfig +++ b/src/cpu/intel/socket_rPGA989/Kconfig @@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select MMX select SSE - select CACHE_AS_RAM config CACHE_MRC_BIN bool diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index 01fd408..10b52bb 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select MMX select SSE2 - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index e819585..4242dd6 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select MMX select SSE2 - select CACHE_AS_RAM select SUPPORT_CPU_UCODE_IN_CBFS config DCACHE_RAM_BASE diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 4681bc2..727176b 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82371EB - select CACHE_AS_RAM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 39a84ed..69f596d 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select CACHE_AS_RAM # select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index a13db8b..a64c0e3 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select UDELAY_TSC select HAVE_OPTION_TABLE - select CACHE_AS_RAM select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_512

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Patch merged into coreboot/master: 6a089e3 AGESA boards: Use acpi_is_wakeup_s3()
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit 6a089e3b18ebb5561ae7233d28ff53fff9fbe676 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 27 13:32:59 2014 +0300 AGESA boards: Use acpi_is_wakeup_s3() Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6143 for details. -gerrit

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Patch merged into coreboot/master: db8693b ACPI: Recover type of wakeup in acpi_is_wakeup()
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit db8693bde7ad2cc2f6b32bb9654685c1ddb502b2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 23:29:07 2014 +0300 ACPI: Recover type of wakeup in acpi_is_wakeup() Update acpi_slp_type early in ramstage. Change-Id: I30ec2680d28b880171217e896f48606f8691b099 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6142 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6142 for details. -gerrit

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Patch merged into coreboot/master: ef40ca5 AGESA: Call get_bus_conf() just once
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit ef40ca57ebd4de746eafaa1e5a1cae035337f285 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 22:19:20 2014 +0300 AGESA: Call get_bus_conf() just once Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6133 for details. -gerrit

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Patch merged into coreboot/master: 005028e AGESA: Add agesawrapper_post_device()
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit 005028e0a952b00b6184cdddf5905a1637029585 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 23:12:15 2014 +0300 AGESA: Add agesawrapper_post_device() NOTE: The procedure is moved across a collected timestamp TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted for in an earlier entry in cbmem -t output. Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6132 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6132 for details. -gerrit

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Patch merged into coreboot/master: e1b468e AGESA boards: Use acpi_s3_resume_allowed()
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit e1b468e1a7cbea55108fb106105612e1f50c9487 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 18 09:10:53 2014 +0300 AGESA boards: Use acpi_s3_resume_allowed() This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the build of romstage also for boards without HAVE_ACPI_RESUME. These symbols got exposed as the use of preprocessor directives was reduced. We expect the linker to do a fair job and optimize away function bodies that are on unreachable execution paths. Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6067 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6067 for details. -gerrit

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Patch merged into coreboot/master: adf3d6f AGESA: Clean separation of SPI flash
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit adf3d6ff52eb674267eacbf37f811c7144e857b3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 16:51:54 2014 +0300 AGESA: Clean separation of SPI flash To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6085 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/6085 for details. -gerrit

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Patch merged into coreboot/master: 23b4f0c AGESA boards: Add prepare_for_resume()
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit 23b4f0c7344c199d5adb0aece8d3ca9a624f4a34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 18 09:55:26 2014 +0300 AGESA boards: Add prepare_for_resume() Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6084 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6084 for details. -gerrit

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Patch merged into coreboot/master: 31eff28 AGESA S3: Refactor S3 backup store locations in SPI
by gerrit＠coreboot.org 03 Jul '14

03 Jul '14

the following patch was just integrated into master: commit 31eff28f4f47a38f6e25c93d76f52fe19a092545 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 20 12:52:06 2014 +0300 AGESA S3: Refactor S3 backup store locations in SPI Prepare code to locate S3 backup from CBFS as a file. Follow-up will replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content(). Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6083 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/6083 for details. -gerrit

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coreboot-gerrit July 2014