coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 2093c4f AMD/agesa: Add functions for AMD PCI IRQ routing
by gerrit＠coreboot.org 02 Jul '14

02 Jul '14

the following patch was just integrated into master: commit 2093c4f7c220068e630b756dd19b89ab1ddec88e Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jun 13 08:12:48 2014 -0600 AMD/agesa: Add functions for AMD PCI IRQ routing Port the changes that were made in amd/cimx to amd/agesa as were done in: commit c93a75a5ab067f86104028b74d92fc54cb939cd5 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Jun 6 15:16:29 2014 -0600 AMD/CIMx: Add functions for AMD PCI IRQ routing This change also moves the PCI INT functions to southbridge/amd so that they can be used by CIMX and AGESA. The amd/persimmon board is updated for this change. Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637 Reviewed-on: http://review.coreboot.org/6065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/6065 for details. -gerrit

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Patch set updated for coreboot: 863ee30 Remove unnecessary mappings in cbfs_media
by Naman Govil 02 Jul '14

02 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6169 -gerrit commit 863ee30a5b2feb0f4c04db7aab4cb061ad9725e7 Author: Naman Govil <namangov(a)gmail.com> Date: Mon Jun 30 22:57:11 2014 +0530 Remove unnecessary mappings in cbfs_media Reducing the sram usage while booting by removing unwanted map()s by creating a structure to replace it with appropriate read()s Change-Id: If503368553308a2fdd3ecc1a312a11f14c7a707f Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/cbfs_core.h | 26 ++++++-- src/lib/cbfs.c | 71 ++++++++++++++------ src/lib/cbfs_core.c | 171 +++++++++++++++++++++++++++--------------------- 3 files changed, 167 insertions(+), 101 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index a1d8127..773f04e 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -4,6 +4,7 @@ * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2012 Google, Inc. * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This file is dual-licensed. You can choose between: * - The GNU GPL, version 2, as published by the Free Software Foundation @@ -189,6 +190,12 @@ struct cbfs_optionrom { #define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) +struct cbfs_file_handler { + uint32_t data_offset; + uint32_t data_len; + struct cbfs_file file; +}; + /* Media for CBFS to load files. */ struct cbfs_media { @@ -220,16 +227,23 @@ struct cbfs_media { /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +/* stores a pointer to CBFS master header,return 0 on success and + <0 if header not found*/ +int cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header); + +/*Returns success (0) on finding the file requested by verifying name/type; + -1 if file not found + The absolute data_offset to the file is stored*/ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, + const char *name, int type); + + +/* returns pointer to file content inside CBFS after verifying if type is correct */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz); #endif /* __ROMCC__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dc08937..97cc6e4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * + * Copyright (C) 2014, Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -119,39 +119,70 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, void * cbfs_load_stage(struct cbfs_media *media, const char *name) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + struct cbfs_file_handler f; + struct cbfs_stage stage; + int c; + ssize_t value_read; + void * data; + ssize_t v_read; + struct cbfs_media default_media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return (void *)-1; + } + } + + c = cbfs_find_file(media, &f, name, CBFS_TYPE_STAGE); + if (c == 0) { + value_read = media->read(media, &stage, f.data_offset, sizeof(stage)); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; uint32_t final_size; - if (stage == NULL) + DEBUG("Read Complete @offset = 0x%x and length = %d\n", f.data_offset, value_read); + if (value_read != sizeof(stage)) return (void *) -1; LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (uint32_t) stage->load, stage->memlen, - stage->entry); - - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); - if (!final_size) - return (void *) -1; + (uint32_t) stage.load, stage.memlen, + stage.entry); - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); - DEBUG("stage loaded.\n"); + if(stage.compression == CBFS_COMPRESS_NONE) { + //No compression; hence we can directly read + DEBUG("Read Done\n"); + v_read = media->read(media, (void *) (uintptr_t) stage.load, + f.data_offset + sizeof(stage), f.data_len); + final_size = f.data_len; + } + else { + data = media->map(media, f.data_offset + sizeof(stage), f.data_len); + DEBUG("Map Done\n"); + final_size = cbfs_decompress(stage.compression, data, + (void *) (uint32_t) stage.load, + stage.len); + + if (!final_size) + return (void *) -1; + } - entry = stage->entry; - // entry = ntohll(stage->entry); + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *)((uintptr_t)stage.load + final_size), 0, + stage.memlen - final_size); + DEBUG("stage loaded.\n"); + entry = stage.entry; return (void *) entry; + } + else { + ERROR("Stage not loaded\n"); + return (void *)-1; + } } /* Simple buffer */ diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 50c037e..7c7f9ca 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 secunet Security Networks AG * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -52,150 +53,170 @@ #include <cbfs.h> #include <string.h> -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +/* stores a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS + * on failure. returns 0 on success and <0 if header not found */ +int cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header) { - const struct cbfs_header *header; struct cbfs_media default_media; + ssize_t header_size; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } } media->open(media); DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, CONFIG_ROM_SIZE); - header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); + header_size = media->read(media, (void *)header , CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (header_size == sizeof(*header)) { ERROR("Failed to load CBFS header from 0x%x\n", CBFS_HEADER_ROM_ADDRESS); - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + else if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { ERROR("Could not find valid CBFS master header at %x: " "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, ntohl(header->magic)); if (header->magic == 0xffffffff) { ERROR("Maybe ROM is not mapped properly?\n"); } - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } - return header; + return 0; } /* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +/* This functions finds the absolute data_offset of a file searched for by name/type + Returns 0 on success and -1 on failure + */ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, const char *name, int type) { - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; + uint32_t offset, align, romsize,name_len; struct cbfs_media default_media; + ssize_t value_read; + const char *file_name; + struct cbfs_header header; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return NULL; + return -1; } } - - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; + int flag; + flag = cbfs_get_header(media, &header); + if (flag != 0) + return -1; // error // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); + // Now we know where the file lives + offset = ntohl(header.offset); + align = ntohl(header.align); + romsize = ntohl(header.romsize); - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. #if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - romsize -= htonl(header->bootblocksize); + romsize -= htonl(header.bootblocksize); #endif + int catch; DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); - while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { + while (offset < romsize) + { + value_read = media->read(media, &f->file, offset, sizeof(f->file)); + if(value_read != sizeof(f->file)){ + return -1; //error: since read not successful + } + //make all ntohl() at once place to avoid any gibberish later + f->file.len = ntohl(f->file.len); + f->file.offset = ntohl(f->file.offset); + f->file.type = ntohl(f->file.type); + + if (memcmp(CBFS_FILE_MAGIC, f->file.magic, + sizeof(f->file.magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); + ERROR("ERROR: No file header found at 0x%x - try next aligned address: 0x%x.\n", offset,offset+new_align); offset += new_align; continue; } - name_len = ntohl(file.offset) - sizeof(file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); - media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - return file_ptr; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } + if (f->file.type == type) { + + name_len = f->file.offset - sizeof(f->file); + DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,name_len); + // load file name (arbitrary length). + file_name = (const char *)media->map(media, offset + sizeof(f->file), name_len); + //this mapping done to verify name of file + if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); + } else if (strcmp(file_name, name) == 0) { + f->data_offset = offset + f->file.offset; + f->data_len = f->file.len; + media->unmap(media, file_name); + DEBUG("Found file:offset = 0x%x, len=%d\n", f->data_offset, f->data_len); + catch = 0; + return catch; + } else { + DEBUG("unmatched file offset = 0x%x : %s\n", offset, file_name); + media->unmap(media,file_name); + } + } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); + offset += f->file.len + f->file.offset; if (offset % align) offset += align - (offset % align); + DEBUG("Going for next offset\n"); } media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return NULL; + LOG("Warning: '%s' not found\n",name); + return -1; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) + +/*Returns pointer to file content inside CBFS after verifying type + */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz) { - struct cbfs_file *file = cbfs_get_file(media, name); + struct cbfs_file_handler f; + int c; + struct cbfs_media default_media; + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return NULL; + } + } + c = cbfs_find_file(media, &f, name, type); + if (c == 0){ + DEBUG("Found file. Will be mapping it now!\n"); if (sz) *sz = 0; - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); + if (f.file.type != type) { + ERROR("File '%s' is of type %x, but we requested %x.\n", name, f.file.type, type); return NULL; } - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); + if (sz) + *sz = f.data_len; + return media->map(media, f.data_offset, f.data_len + f.file.offset); + } + else { + DEBUG("condition not successful\n"); + ERROR("File Not Found\n"); return NULL; } - - if (sz) - *sz = ntohl(file->len); - - return (void *)CBFS_SUBHEADER(file); } int cbfs_decompress(int algo, void *src, void *dst, int len)

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New patch to review for coreboot: e3deeff drivers/spi: Excessive use of preprocessor checking Kconfig vars
by Edward O'Callaghan 02 Jul '14

02 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6171 -gerrit commit e3deefff20ac079eab8b4e922b659a608c70e4e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 2 15:14:56 2014 +1000 drivers/spi: Excessive use of preprocessor checking Kconfig vars printk(DEBUG, ..) will only show when DEBUG is selected, no need to wrap them again in another debug Kconfig variable. Change-Id: Id70dd55bf41c17931745996f5bad3d222f99ae6c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/spi/adesto.c | 4 ---- src/drivers/spi/amic.c | 4 ---- src/drivers/spi/eon.c | 4 ---- src/drivers/spi/gigadevice.c | 4 ---- src/drivers/spi/macronix.c | 4 ---- src/drivers/spi/spansion.c | 4 ---- src/drivers/spi/spi_flash.c | 4 ---- src/drivers/spi/sst.c | 6 ------ src/drivers/spi/stmicro.c | 4 ---- src/drivers/spi/winbond.c | 4 ---- 10 files changed, 42 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 83be8b8..79a267d 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -105,11 +105,9 @@ static int adesto_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); if (ret < 0) { @@ -132,10 +130,8 @@ static int adesto_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); -#endif ret = 0; out: diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index fa17036..f675a30 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -87,11 +87,9 @@ static int amic_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_A25_WREN, NULL, 0); if (ret < 0) { @@ -114,10 +112,8 @@ static int amic_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: AMIC: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); -#endif ret = 0; out: diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 5a74b84..7cd92b8 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -95,11 +95,9 @@ static int eon_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); if (ret < 0) { @@ -122,10 +120,8 @@ static int eon_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n", len, offset); -#endif spi_release_bus(flash->spi); return ret; diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 5a8f82f..1f3ef69 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -153,12 +153,10 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd_write(flash->spi, cmd, 4, buf + actual, chunk_len); @@ -176,11 +174,9 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n", len, (unsigned int)(offset - len)); -#endif ret = 0; diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index bbc3704..104096e 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -150,11 +150,9 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { @@ -177,10 +175,8 @@ static int macronix_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: Macronix: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); -#endif spi_release_bus(flash->spi); return ret; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 6dd6df9..f0ee4c3 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -163,11 +163,9 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { @@ -190,10 +188,8 @@ static int spansion_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n", len, offset); -#endif spi_release_bus(flash->spi); return ret; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..38a1949 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -164,10 +164,8 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, spi_flash_addr(offset, cmd); offset += erase_size; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); -#endif ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); if (ret) goto out; @@ -285,9 +283,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, if (ret) goto err_read_id; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: Got idcodes\n"); -#endif /* count the number of continuation bytes */ for (shift = 0, idp = idcode; diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 3cf6c50..3be6f05 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -125,10 +125,8 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) offset, }; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); -#endif ret = sst_enable_writing(flash); if (ret) @@ -175,11 +173,9 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) cmd[3] = offset; for (; actual < len - 1; actual += 2) { -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); -#endif ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf + actual, 2); @@ -204,10 +200,8 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) ret = sst_byte_write(flash, offset, buf + actual); done: -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", ret ? "failure" : "success", len, (unsigned long)offset - actual); -#endif spi_release_bus(flash->spi); return ret; } diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index af23853..9bca343 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -160,11 +160,9 @@ static int stmicro_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { @@ -187,10 +185,8 @@ static int stmicro_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: STMicro: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); -#endif ret = 0; out: diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 52c7b61..9df7cfd 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -139,11 +139,9 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -#endif ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) { @@ -166,10 +164,8 @@ static int winbond_write(struct spi_flash *flash, byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: Winbond: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); -#endif ret = 0; out:

1 0

New patch to review for coreboot: 6cf6e4f Documentation: Use correct file name for the build guide in the Makefile
by Vl Be 02 Jul '14

02 Jul '14

Vl Be (vmpn(a)vmpn.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6170 -gerrit commit 6cf6e4fa4b3dacff8e6c752a3a29a966da808933 Author: Vladimir Berezniker <vmpn(a)vmpn.net> Date: Tue Jul 1 20:40:18 2014 -0400 Documentation: Use correct file name for the build guide in the Makefile Change-Id: I19c456e8bcd2de19c5f9d963ea17dad84d300ab8 Signed-off-by: Vladimir Berezniker <vmpn(a)vmpn.net> --- documentation/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/documentation/Makefile b/documentation/Makefile index 6aa4385..1e00444 100644 --- a/documentation/Makefile +++ b/documentation/Makefile @@ -31,13 +31,13 @@ else ifneq ($(strip $(CONVERT)),) convert $< $@ endif -CorebootPortingGuide.toc: $(FIGS) CorebootPortingGuide.tex +CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex # 2 times to make sure we have a current toc. - $(PDFLATEX) CorebootPortingGuide.tex - $(PDFLATEX) CorebootPortingGuide.tex + $(PDFLATEX) CorebootBuildingGuide.tex + $(PDFLATEX) CorebootBuildingGuide.tex -CorebootPortingGuide.pdf: $(FIGS) CorebootPortingGuide.tex CorebootPortingGuide.toc - $(PDFLATEX) CorebootPortingGuide.tex +CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc + $(PDFLATEX) CorebootBuildingGuide.tex Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex $(PDFLATEX) $<

1 0

Patch set updated for coreboot: 5738781 AMD/agesa: Add functions for AMD PCI IRQ routing
by Dave Frodin 01 Jul '14

01 Jul '14

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6065 -gerrit commit 5738781f7cd23827d3ed6e04858f5e26cb5e8f39 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jun 13 08:12:48 2014 -0600 AMD/agesa: Add functions for AMD PCI IRQ routing Port the changes that were made in amd/cimx to amd/agesa as were done in: commit c93a75a5ab067f86104028b74d92fc54cb939cd5 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Jun 6 15:16:29 2014 -0600 AMD/CIMx: Add functions for AMD PCI IRQ routing This change also moves the PCI INT functions to southbridge/amd so that they can be used by CIMX and AGESA. The amd/persimmon board is updated for this change. Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637 --- src/mainboard/amd/persimmon/mainboard.c | 1 + src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 1 + src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/northbridge/amd/agesa/family15tn/pci_devs.h | 54 ++++++ src/northbridge/amd/agesa/family16kb/pci_devs.h | 44 +++++ src/southbridge/amd/Makefile.inc | 6 + .../amd/agesa/hudson/amd_pci_int_defs.h | 84 +++++++++ .../amd/agesa/hudson/amd_pci_int_types.h | 44 +++++ src/southbridge/amd/agesa/hudson/pci.c | 25 +++ src/southbridge/amd/agesa/hudson/pci_devs.h | 121 ++++++++++++ src/southbridge/amd/amd_pci_util.c | 204 +++++++++++++++++++++ src/southbridge/amd/amd_pci_util.h | 48 +++++ src/southbridge/amd/cimx/cimx_util.c | 197 -------------------- src/southbridge/amd/cimx/cimx_util.h | 85 --------- src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h | 42 +++++ src/southbridge/amd/cimx/sb700/amd_pci_int_types.h | 29 +++ src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h | 74 ++++++++ src/southbridge/amd/cimx/sb800/amd_pci_int_types.h | 33 ++++ src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h | 74 ++++++++ src/southbridge/amd/cimx/sb900/amd_pci_int_types.h | 33 ++++ 22 files changed, 920 insertions(+), 285 deletions(-) diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index fda503d..db0dbe0 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> +#include <southbridge/amd/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include "BiosCallOuts.h" diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 8639617..2c2ec06 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/cimx/cimx_util.h> +#include <southbridge/amd/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 6053550..56f6c43 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -30,6 +30,7 @@ #include <device/pci.h> #include <device/pci_def.h> +#include <southbridge/amd/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <southbridge/amd/cimx/cimx_util.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index a97810c..12cb9d1 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -30,8 +30,8 @@ #include <stdint.h> #include <string.h> +#include <southbridge/amd/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/cimx/cimx_util.h> extern u8 bus_sb800[6]; extern u32 apicid_sb800; diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h new file mode 100644 index 0000000..d0acb5c --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_FAM15TN_PCI_DEVS_H_ +#define _AMD_FAM15TN_PCI_DEVS_H_ + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT1_DEV 0x2 +#define NB_PCIE_PORT2_DEV 0x3 +#define NB_PCIE_PORT3_DEV 0x4 +#define NB_PCIE_PORT4_DEV 0x5 +#define NB_PCIE_PORT5_DEV 0x6 +#define NB_PCIE_PORT6_DEV 0x7 +#define NB_PCIE_PORT7_DEV 0x8 +#define NB_PCIE_FUNC 0 +#define NB_PCIE_PORT1_DEVID 0x1412 +#define NB_PCIE_PORT2_DEVID 0x1413 +#define NB_PCIE_PORT3_DEVID 0x1414 +#define NB_PCIE_PORT4_DEVID 0x1415 +#define NB_PCIE_PORT5_DEVID 0x1416 +#define NB_PCIE_PORT6_DEVID 0x1417 +#define NB_PCIE_PORT7_DEVID 0x1418 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_PCIE_PORT6_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_PCIE_PORT7_DEV,NB_PCIE_FUNC) + +#endif /* _AMD_FAM15TN_PCI_DEVS_H_ */ diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h new file mode 100644 index 0000000..be0f524 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_FAM16KB_PCI_DEVS_H_ +#define _AMD_FAM16KB_PCI_DEVS_H_ + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT1_DEV 0x1 +#define NB_PCIE_PORT2_DEV 0x2 +#define NB_PCIE_PORT3_DEV 0x3 +#define NB_PCIE_PORT4_DEV 0x4 +#define NB_PCIE_PORT5_DEV 0x5 +#define NB_PCIE_FUNC 2 +#define NB_PCIE_PORT_DEVID 0x1439 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC) + +#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index e2f3f9c..57128d9 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -16,3 +16,9 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa + +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h new file mode 100644 index 0000000..01f769c --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define FCH_INT_TABLE_SIZE 0x54 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define FCH_INT_TABLE_SIZE 0x42 +#endif + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ +#endif +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h new file mode 100644 index 0000000..75efd67 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", + [0x40] = "RSVD\t", "SATA\t", +}; +#endif + +#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 58498f4..e8836e4 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,11 +24,35 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" +#include <southbridge/amd/amd_pci_util.h> +#include <bootstate.h> static void pci_init(struct device *dev) { } +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { + BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, + set_pci_irqs, NULL), +}; + static struct pci_operations lops_pci = { .set_subsystem = 0, }; diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h new file mode 100644 index 0000000..b66a232 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AGESA_HUDSON_PCI_DEVS_H_ +#define _AGESA_HUDSON_PCI_DEVS_H_ + +#define BUS0 0 + +/* XHCI */ +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7814 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) + +/* SATA */ +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7800 +#define AHCI_DEVID_MS 0x7801 +#define AHCI_DEVID_AMD 0x7804 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) + +/* OHCI */ +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x7807 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) + +/* EHCI */ +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x22 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x7808 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x780B +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) + +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + +/* HD Audio */ +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x780D +#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVID 0x780E +#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) + +/* PCI Ports */ +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +# define SB_PCI_PORT_DEVID 0x780F +# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) + +/* SD Controller */ +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7806 +#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) + +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + +#endif /* _AGESA_HUDSON_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/amd_pci_util.c new file mode 100644 index 0000000..9f2cc5c --- /dev/null +++ b/src/southbridge/amd/amd_pci_util.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include "amd_pci_util.h" +#include <pc80/i8259.h> +#include "amd_pci_int_defs.h" +#include "amd_pci_int_types.h" + +#ifndef __PRE_RAM__ + +const struct pirq_struct * pirq_data_ptr = NULL; +u32 pirq_data_size = 0; +const u8 * intr_data_ptr = NULL; +const u8 * picr_data_ptr = NULL; + +/* + * Read the FCH PCI_INTR registers 0xC00/0xC01 at a + * given index and a given PIC (0) or IOAPIC (1) mode + */ +u8 read_pci_int_idx(u8 index, int mode) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + return inb(PCI_INTR_DATA); +} + +/* + * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 + * at a given index and PIC (0) or IOAPIC (1) mode + */ +void write_pci_int_idx(u8 index, int mode, u8 data) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + outb(data, PCI_INTR_DATA); +} + +/* + * Write the FCH PCI_INTR registers 0xC00/0xC01 with values + * given in global variables intr_data and picr_data. + * These variables are defined in mainboard.c + */ +void write_pci_int_table (void) +{ + u8 byte; + + if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" + "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); + return; + } + + /* PIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 0)); + } + } + + /* APIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 1)); + } + } +} + +/* + * Function to write the PCI config space Interrupt + * registers based on the values given in PCI_INTR + * table at I/O port 0xC00/0xC01 + */ +void write_pci_cfg_irqs(void) +{ + device_t dev = NULL; /* Our current device to route IRQs to */ + device_t target_dev = NULL; /* The bridge that a device may be connected to */ + u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ + u16 target_pin = 0; /* Pin we will search our tables for */ + u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ + u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ + u8 bus = 0; /* A PCI Device Bus number */ + u16 devfn = 0; /* A PCI Device and Function number */ + u8 bridged_device = 0; /* This device is on a PCI bridge */ + u32 i = 0; + + if (pirq_data_ptr == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'mainboard_pirq_data' structure does not exist\n"); + return; + } + + /* Populate the PCI cfg space header with the IRQ assignment */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + + for (dev = all_devices; dev; dev = dev->next) { + /* + * Step 1: Get the INT_PIN and device structure to look for in the + * PCI_INTR table pirq_data + */ + target_dev = NULL; + target_pin = get_pci_irq_pins(dev, &target_dev); + if (target_dev == NULL) + continue; + + if (target_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + continue; /* Device has invalid INT_PIN so skip it */ + + bus = target_dev->bus->secondary; + devfn = target_dev->path.pci.devfn; + + /* + * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR + * register (0xC00) index for this device + */ + pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ + for (i = 0; i < pirq_data_size; i++) { + if (pirq_data_ptr[i].devfn != devfn) + continue; + + /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ + pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; + printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); + break; + } + + /* + * Step 3: Make sure we got a valid index and use it to get + * the IRQ number from the PCI_INTR register table + */ + if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ + printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); + continue; + } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ + printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); + continue; + } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ + printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", + __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); + continue; + } + + /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ + int_line = read_pci_int_idx(pci_intr_idx, 0); + if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ + printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); + continue; + } + + /* + * Step 4: Program the INT_LINE register in this device's + * PCI config space with the IRQ number we found in step 3 + * and make it Level Triggered + */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); + + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + + /* + * Step 5: Print out debug info and move on to next device + */ + printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", + int_pin, pin_to_str(int_pin)); + if (bridged_device) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + target_pin, pin_to_str(target_pin)); + printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); + } /* for (dev = all_devices) */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} +#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/amd_pci_util.h new file mode 100644 index 0000000..1d1e52b --- /dev/null +++ b/src/southbridge/amd/amd_pci_util.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_UTIL_H +#define AMD_PCI_UTIL_H + +#include <stdint.h> +#include "amd_pci_int_defs.h" + +/* FCH index/data registers */ +#define PCI_INTR_INDEX 0xc00 +#define PCI_INTR_DATA 0xc01 + +#ifndef __PRE_RAM__ + +struct pirq_struct { + u8 devfn; + u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ +}; + +extern const struct pirq_struct * pirq_data_ptr; +extern u32 pirq_data_size; +extern const u8 * intr_data_ptr; +extern const u8 * picr_data_ptr; + +u8 read_pci_int_idx(u8 index, int mode); +void write_pci_int_idx(u8 index, int mode, u8 data); +void write_pci_cfg_irqs(void); +void write_pci_int_table (void); +#endif /* __PRE_RAM */ + +#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c index 5d9276f..7909b68 100644 --- a/src/southbridge/amd/cimx/cimx_util.c +++ b/src/southbridge/amd/cimx/cimx_util.c @@ -21,204 +21,7 @@ #include <console/console.h> #include <device/pci.h> #include <arch/io.h> -#include <string.h> #include "cimx_util.h" -#include <pc80/i8259.h> - -#ifndef __PRE_RAM__ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) -const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" -}; -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) -const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", - [0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t", - [0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", -}; -#endif - -const struct pirq_struct * pirq_data_ptr = NULL; -u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; - -/* - * Read the FCH PCI_INTR registers 0xC00/0xC01 at a - * given index and a given PIC (0) or IOAPIC (1) mode - */ -u8 read_pci_int_idx(u8 index, int mode) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - return inb(PCI_INTR_DATA); -} - -/* - * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 - * at a given index and PIC (0) or IOAPIC (1) mode - */ -void write_pci_int_idx(u8 index, int mode, u8 data) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - outb(data, PCI_INTR_DATA); -} - -/* - * Write the FCH PCI_INTR registers 0xC00/0xC01 with values - * given in global variables intr_data and picr_data. - * These variables are defined in mainboard.c - */ -void write_pci_int_table (void) -{ - u8 byte; - - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ - printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); - return; - } - - /* PIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 0)); - } - } - - /* APIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 1)); - } - } -} - -/* - * Function to write the PCI config space Interrupt - * registers based on the values given in PCI_INTR - * table at I/O port 0xC00/0xC01 - */ -void write_pci_cfg_irqs(void) -{ - device_t dev = NULL; /* Our current device to route IRQs to */ - device_t target_dev = NULL; /* The bridge that a device may be connected to */ - u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ - u16 target_pin = 0; /* Pin we will search our tables for */ - u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ - u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ - u16 devfn = 0; /* A PCI Device and Function number */ - u8 bridged_device = 0; /* This device is on a PCI bridge */ - u32 i = 0; - - if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'mainboard_pirq_data' structure does not exist\n"); - return; - } - - /* Populate the PCI cfg space header with the IRQ assignment */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - - for (dev = all_devices; dev; dev = dev->next) { - /* - * Step 1: Get the INT_PIN and device structure to look for in the - * PCI_INTR table pirq_data - */ - target_dev = NULL; - target_pin = get_pci_irq_pins(dev, &target_dev); - if (target_dev == NULL) - continue; - - if (target_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (int_pin < 1 || int_pin > 4) - continue; /* Device has invalid INT_PIN so skip it */ - - bus = target_dev->bus->secondary; - devfn = target_dev->path.pci.devfn; - - /* - * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR - * register (0xC00) index for this device - */ - pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ - for (i = 0; i < pirq_data_size; i++) { - if (pirq_data_ptr[i].devfn != devfn) - continue; - - /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ - pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; - printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); - break; - } - - /* - * Step 3: Make sure we got a valid index and use it to get - * the IRQ number from the PCI_INTR register table - */ - if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ - printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); - continue; - } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ - printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); - continue; - } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", - __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); - continue; - } - - /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ - int_line = read_pci_int_idx(pci_intr_idx, 0); - if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ - printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); - continue; - } - - /* - * Step 4: Program the INT_LINE register in this device's - * PCI config space with the IRQ number we found in step 3 - * and make it Level Triggered - */ - pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); - - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - - /* - * Step 5: Print out debug info and move on to next device - */ - printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", - int_pin, pin_to_str(int_pin)); - if (bridged_device) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); - printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); - } /* for (dev = all_devices) */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} -#endif /* __PRE_RAM__ */ static void pmio_write_index(u16 port_base, u8 reg, u8 value) { diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h index 8413251..a16091a 100644 --- a/src/southbridge/amd/cimx/cimx_util.h +++ b/src/southbridge/amd/cimx/cimx_util.h @@ -23,73 +23,6 @@ #include <stdint.h> -/* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table - */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) -#define FCH_INT_TABLE_SIZE 0x54 -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_E 0x04 /* INT E */ -#define PIRQ_F 0x05 /* INT F */ -#define PIRQ_G 0x06 /* INT G */ -#define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ -#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ -#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ -#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ -#define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ -#define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ -#define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_IMC0 0x20 /* IMC INT0 */ -#define PIRQ_IMC1 0x21 /* IMC INT1 */ -#define PIRQ_IMC2 0x22 /* IMC INT2 */ -#define PIRQ_IMC3 0x23 /* IMC INT3 */ -#define PIRQ_IMC4 0x24 /* IMC INT4 */ -#define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#define PIRQ_GPP0 0x50 /* GPP INT 0 */ -#define PIRQ_GPP1 0x51 /* GPP INT 1 */ -#define PIRQ_GPP2 0x52 /* GPP INT 2 */ -#define PIRQ_GPP3 0x53 /* GPP INT 3 */ -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) -#define FCH_INT_TABLE_SIZE 0xD -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_ACPI 0x04 /* ACPI */ -#define PIRQ_SMBUS 0x05 /* SMBUS */ -/* Index 6, 7, 8 are all reserved */ -#define PIRQ_E 0x09 /* INT E */ -#define PIRQ_F 0x0A /* INT F */ -#define PIRQ_G 0x0B /* INT G */ -#define PIRQ_H 0x0C /* INT H */ -#endif - /* FCH index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 @@ -105,22 +38,4 @@ u8 pm_ioread(u8 reg); void pm2_iowrite(u8 reg, u8 value); u8 pm2_ioread(u8 reg); -#ifndef __PRE_RAM__ - -struct pirq_struct { -u8 devfn; -u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ -}; - -extern const struct pirq_struct * pirq_data_ptr; -extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; - -u8 read_pci_int_idx(u8 index, int mode); -void write_pci_int_idx(u8 index, int mode, u8 data); -void write_pci_cfg_irqs(void); -void write_pci_int_table (void); -#endif /* __PRE_RAM */ - #endif /* CIMX_UTIL_H */ diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h new file mode 100644 index 0000000..fb1cb9d --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#define FCH_INT_TABLE_SIZE 0xD +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_ACPI 0x04 /* ACPI */ +#define PIRQ_SMBUS 0x05 /* SMBUS */ +/* Index 6, 7, 8 are all reserved */ +#define PIRQ_E 0x09 /* INT E */ +#define PIRQ_F 0x0A /* INT F */ +#define PIRQ_G 0x0B /* INT G */ +#define PIRQ_H 0x0C /* INT H */ + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h new file mode 100644 index 0000000..6c28e31 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", + [0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t", + [0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", +}; + +#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h new file mode 100644 index 0000000..6f1ae8f --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#define FCH_INT_TABLE_SIZE 0x54 + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h new file mode 100644 index 0000000..173059c --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; + +#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8000601..b132bf1 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -38,7 +38,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" -#include <southbridge/amd/cimx/cimx_util.h> +#include <southbridge/amd/amd_pci_util.h> /*implement in mainboard.c*/ void set_pcie_reset(void); diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h new file mode 100644 index 0000000..6f1ae8f --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#define FCH_INT_TABLE_SIZE 0x54 + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h new file mode 100644 index 0000000..173059c --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; + +#endif /* AMD_PCI_INT_TYPES_H */

1 0

Patch set updated for coreboot: 01768dd Remove unnecessary mappings in cbfs_media
by Naman Govil 01 Jul '14

01 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6169 -gerrit commit 01768dd0596679d9b51e3e2cbb09b6330fee1362 Author: Naman Govil <namangov(a)gmail.com> Date: Mon Jun 30 22:57:11 2014 +0530 Remove unnecessary mappings in cbfs_media Reducing the sram usage while booting by removing unwanted map()s by creating a structure to replace it with appropriate read()s Change-Id: If503368553308a2fdd3ecc1a312a11f14c7a707f Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/cbfs_core.h | 22 ++++-- src/lib/cbfs.c | 71 ++++++++++++++------ src/lib/cbfs_core.c | 173 +++++++++++++++++++++++++++--------------------- 3 files changed, 168 insertions(+), 98 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index a1d8127..884f054 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -4,6 +4,7 @@ * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2012 Google, Inc. * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This file is dual-licensed. You can choose between: * - The GNU GPL, version 2, as published by the Free Software Foundation @@ -189,6 +190,12 @@ struct cbfs_optionrom { #define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) +struct cbfs_file_handler { + uint32_t data_offset; + uint32_t data_len; + struct cbfs_file file; +}; + /* Media for CBFS to load files. */ struct cbfs_media { @@ -220,16 +227,23 @@ struct cbfs_media { /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +void cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header); + +/*Returns success (0) on finding the file requested by verifying name/type; + -1 if file not found + The absolute data_offset to the file is stored*/ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, + const char *name, int type); + + +/* returns pointer to file content inside CBFS after verifying if type is correct */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz); #endif /* __ROMCC__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dc08937..97cc6e4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * + * Copyright (C) 2014, Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -119,39 +119,70 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, void * cbfs_load_stage(struct cbfs_media *media, const char *name) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + struct cbfs_file_handler f; + struct cbfs_stage stage; + int c; + ssize_t value_read; + void * data; + ssize_t v_read; + struct cbfs_media default_media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return (void *)-1; + } + } + + c = cbfs_find_file(media, &f, name, CBFS_TYPE_STAGE); + if (c == 0) { + value_read = media->read(media, &stage, f.data_offset, sizeof(stage)); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; uint32_t final_size; - if (stage == NULL) + DEBUG("Read Complete @offset = 0x%x and length = %d\n", f.data_offset, value_read); + if (value_read != sizeof(stage)) return (void *) -1; LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (uint32_t) stage->load, stage->memlen, - stage->entry); - - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); - if (!final_size) - return (void *) -1; + (uint32_t) stage.load, stage.memlen, + stage.entry); - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); - DEBUG("stage loaded.\n"); + if(stage.compression == CBFS_COMPRESS_NONE) { + //No compression; hence we can directly read + DEBUG("Read Done\n"); + v_read = media->read(media, (void *) (uintptr_t) stage.load, + f.data_offset + sizeof(stage), f.data_len); + final_size = f.data_len; + } + else { + data = media->map(media, f.data_offset + sizeof(stage), f.data_len); + DEBUG("Map Done\n"); + final_size = cbfs_decompress(stage.compression, data, + (void *) (uint32_t) stage.load, + stage.len); + + if (!final_size) + return (void *) -1; + } - entry = stage->entry; - // entry = ntohll(stage->entry); + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *)((uintptr_t)stage.load + final_size), 0, + stage.memlen - final_size); + DEBUG("stage loaded.\n"); + entry = stage.entry; return (void *) entry; + } + else { + ERROR("Stage not loaded\n"); + return (void *)-1; + } } /* Simple buffer */ diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 50c037e..0c6948c 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 secunet Security Networks AG * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,148 +55,172 @@ /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +void cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header) { - const struct cbfs_header *header; + struct cbfs_header h; struct cbfs_media default_media; + ssize_t header_size; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; } } media->open(media); DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, CONFIG_ROM_SIZE); - header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); + header_size = media->read(media, &h, CBFS_HEADER_ROM_ADDRESS, sizeof(h)); media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (header_size == sizeof(h)) { ERROR("Failed to load CBFS header from 0x%x\n", CBFS_HEADER_ROM_ADDRESS); - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + else if (CBFS_HEADER_MAGIC != ntohl(h.magic)) { ERROR("Could not find valid CBFS master header at %x: " "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, - ntohl(header->magic)); - if (header->magic == 0xffffffff) { + ntohl(h.magic)); + if (h.magic == 0xffffffff) { ERROR("Maybe ROM is not mapped properly?\n"); } - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; + } + else { + header = &h; } - return header; } /* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +/* This functions finds the absolute data_offset of a file searched for by name/type + Returns 0 on success and -1 on failure + */ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, const char *name, int type) { - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; + uint32_t offset, align, romsize,name_len; struct cbfs_media default_media; + ssize_t value_read; + const char *file_name; + struct cbfs_header header, *h; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return NULL; + return -1; } } - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; + cbfs_get_header(media, &header); + h = &header; + if (h == CBFS_HEADER_INVALID_ADDRESS) + return -1; // error // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); + // Now we know where the file lives + offset = ntohl(header.offset); + align = ntohl(header.align); + romsize = ntohl(header.romsize); - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. #if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - romsize -= htonl(header->bootblocksize); + romsize -= htonl(header.bootblocksize); #endif + int catch; DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); - while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { + while (offset < romsize) + { + value_read = media->read(media, &f->file, offset, sizeof(f->file)); + if(value_read != sizeof(f->file)){ + return -1; //error: since read not successful + } + //make all ntohl() at once place to avoid any gibberish later + f->file.len = ntohl(f->file.len); + f->file.offset = ntohl(f->file.offset); + f->file.type = ntohl(f->file.type); + + if (memcmp(CBFS_FILE_MAGIC, f->file.magic, + sizeof(f->file.magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); + ERROR("ERROR: No file header found at 0x%x - try next aligned address: 0x%x.\n", offset,offset+new_align); offset += new_align; continue; } - name_len = ntohl(file.offset) - sizeof(file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); - media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - return file_ptr; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } + if (f->file.type == type) { + + name_len = f->file.offset - sizeof(f->file); + DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,name_len); + // load file name (arbitrary length). + file_name = (const char *)media->map(media, offset + sizeof(f->file), name_len); + //this mapping done to verify name of file + if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); + } else if (strcmp(file_name, name) == 0) { + f->data_offset = offset + f->file.offset; + f->data_len = f->file.len; + media->unmap(media, file_name); + DEBUG("Found file:offset = 0x%x, len=%d\n", f->data_offset, f->data_len); + catch = 0; + return catch; + } else { + DEBUG("unmatched file offset = 0x%x : %s\n", offset, file_name); + media->unmap(media,file_name); + } + } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); + offset += f->file.len + f->file.offset; if (offset % align) offset += align - (offset % align); + DEBUG("Going for next offset\n"); } media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return NULL; + LOG("Warning: '%s' not found\n",name); + return -1; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) + +/*Returns pointer to file content inside CBFS after verifying type + */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz) { - struct cbfs_file *file = cbfs_get_file(media, name); + struct cbfs_file_handler f; + int c; + struct cbfs_media default_media; + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return NULL; + } + } + c = cbfs_find_file(media, &f, name, type); + if (c == 0){ + DEBUG("Found file. Will be mapping it now!\n"); if (sz) *sz = 0; - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); + if (f.file.type != type) { + ERROR("File '%s' is of type %x, but we requested %x.\n", name, f.file.type, type); return NULL; } - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); + if (sz) + *sz = f.data_len; + return media->map(media, f.data_offset, f.data_len + f.file.offset); + } + else { + DEBUG("condition not successful\n"); + ERROR("File Not Found\n"); return NULL; } - - if (sz) - *sz = ntohl(file->len); - - return (void *)CBFS_SUBHEADER(file); } int cbfs_decompress(int algo, void *src, void *dst, int len)

1 0

Patch set updated for coreboot: 3ed0d62 Remove unnecessary mappings in cbfs_media
by Naman Govil 01 Jul '14

01 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6169 -gerrit commit 3ed0d627f49aabaa2a1e7731791e800880663f87 Author: Naman Govil <namangov(a)gmail.com> Date: Mon Jun 30 22:57:11 2014 +0530 Remove unnecessary mappings in cbfs_media Reducing the sram usage while booting by removing unwanted map()s by creating a structure to replace it with appropriate read()s Change-Id: If503368553308a2fdd3ecc1a312a11f14c7a707f Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/cbfs_core.h | 22 +++++-- src/lib/cbfs.c | 71 ++++++++++++++------ src/lib/cbfs_core.c | 172 +++++++++++++++++++++++++++--------------------- 3 files changed, 167 insertions(+), 98 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index a1d8127..884f054 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -4,6 +4,7 @@ * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2012 Google, Inc. * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This file is dual-licensed. You can choose between: * - The GNU GPL, version 2, as published by the Free Software Foundation @@ -189,6 +190,12 @@ struct cbfs_optionrom { #define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) +struct cbfs_file_handler { + uint32_t data_offset; + uint32_t data_len; + struct cbfs_file file; +}; + /* Media for CBFS to load files. */ struct cbfs_media { @@ -220,16 +227,23 @@ struct cbfs_media { /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +void cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header); + +/*Returns success (0) on finding the file requested by verifying name/type; + -1 if file not found + The absolute data_offset to the file is stored*/ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, + const char *name, int type); + + +/* returns pointer to file content inside CBFS after verifying if type is correct */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz); #endif /* __ROMCC__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dc08937..97cc6e4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * + * Copyright (C) 2014, Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -119,39 +119,70 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, void * cbfs_load_stage(struct cbfs_media *media, const char *name) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + struct cbfs_file_handler f; + struct cbfs_stage stage; + int c; + ssize_t value_read; + void * data; + ssize_t v_read; + struct cbfs_media default_media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return (void *)-1; + } + } + + c = cbfs_find_file(media, &f, name, CBFS_TYPE_STAGE); + if (c == 0) { + value_read = media->read(media, &stage, f.data_offset, sizeof(stage)); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; uint32_t final_size; - if (stage == NULL) + DEBUG("Read Complete @offset = 0x%x and length = %d\n", f.data_offset, value_read); + if (value_read != sizeof(stage)) return (void *) -1; LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (uint32_t) stage->load, stage->memlen, - stage->entry); - - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); - if (!final_size) - return (void *) -1; + (uint32_t) stage.load, stage.memlen, + stage.entry); - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); - DEBUG("stage loaded.\n"); + if(stage.compression == CBFS_COMPRESS_NONE) { + //No compression; hence we can directly read + DEBUG("Read Done\n"); + v_read = media->read(media, (void *) (uintptr_t) stage.load, + f.data_offset + sizeof(stage), f.data_len); + final_size = f.data_len; + } + else { + data = media->map(media, f.data_offset + sizeof(stage), f.data_len); + DEBUG("Map Done\n"); + final_size = cbfs_decompress(stage.compression, data, + (void *) (uint32_t) stage.load, + stage.len); + + if (!final_size) + return (void *) -1; + } - entry = stage->entry; - // entry = ntohll(stage->entry); + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *)((uintptr_t)stage.load + final_size), 0, + stage.memlen - final_size); + DEBUG("stage loaded.\n"); + entry = stage.entry; return (void *) entry; + } + else { + ERROR("Stage not loaded\n"); + return (void *)-1; + } } /* Simple buffer */ diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 50c037e..ebf8b10 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 secunet Security Networks AG * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,148 +55,171 @@ /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +void cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header) { - const struct cbfs_header *header; + struct cbfs_header h; struct cbfs_media default_media; + ssize_t header_size; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; } } media->open(media); DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, CONFIG_ROM_SIZE); - header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); + header_size = media->read(media, &h, CBFS_HEADER_ROM_ADDRESS, sizeof(h)); media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (header_size == sizeof(h)) { ERROR("Failed to load CBFS header from 0x%x\n", CBFS_HEADER_ROM_ADDRESS); - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + else if (CBFS_HEADER_MAGIC != ntohl(h.magic)) { ERROR("Could not find valid CBFS master header at %x: " "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, - ntohl(header->magic)); - if (header->magic == 0xffffffff) { + ntohl(h.magic)); + if (h.magic == 0xffffffff) { ERROR("Maybe ROM is not mapped properly?\n"); } - return CBFS_HEADER_INVALID_ADDRESS; + header = CBFS_HEADER_INVALID_ADDRESS; + } + else { + header = &h; } - return header; } /* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +/* This functions finds the absolute data_offset of a file searched for by name/type + Returns 0 on success and -1 on failure + */ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handler *f, const char *name, int type) { - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; + uint32_t offset, align, romsize,name_len; struct cbfs_media default_media; + ssize_t value_read; + const char *file_name; + struct cbfs_header header; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return NULL; + return -1; } } - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; + cbfs_get_header(media, &header); + if (header == CBFS_HEADER_INVALID_ADDRESS) + return -1; // error // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); + // Now we know where the file lives + offset = ntohl(header.offset); + align = ntohl(header.align); + romsize = ntohl(header.romsize); - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. #if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - romsize -= htonl(header->bootblocksize); + romsize -= htonl(header.bootblocksize); #endif + int catch; DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); - while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { + while (offset < romsize) + { + value_read = media->read(media, &f->file, offset, sizeof(f->file)); + if(value_read != sizeof(f->file)){ + return -1; //error: since read not successful + } + //make all ntohl() at once place to avoid any gibberish later + f->file.len = ntohl(f->file.len); + f->file.offset = ntohl(f->file.offset); + f->file.type = ntohl(f->file.type); + + if (memcmp(CBFS_FILE_MAGIC, f->file.magic, + sizeof(f->file.magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); + ERROR("ERROR: No file header found at 0x%x - try next aligned address: 0x%x.\n", offset,offset+new_align); offset += new_align; continue; } - name_len = ntohl(file.offset) - sizeof(file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); - media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - return file_ptr; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } + if (f->file.type == type) { + + name_len = f->file.offset - sizeof(f->file); + DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,name_len); + // load file name (arbitrary length). + file_name = (const char *)media->map(media, offset + sizeof(f->file), name_len); + //this mapping done to verify name of file + if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); + } else if (strcmp(file_name, name) == 0) { + f->data_offset = offset + f->file.offset; + f->data_len = f->file.len; + media->unmap(media, file_name); + DEBUG("Found file:offset = 0x%x, len=%d\n", f->data_offset, f->data_len); + catch = 0; + return catch; + } else { + DEBUG("unmatched file offset = 0x%x : %s\n", offset, file_name); + media->unmap(media,file_name); + } + } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); + offset += f->file.len + f->file.offset; if (offset % align) offset += align - (offset % align); + DEBUG("Going for next offset\n"); } media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return NULL; + LOG("Warning: '%s' not found\n",name); + return -1; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) + +/*Returns pointer to file content inside CBFS after verifying type + */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz) { - struct cbfs_file *file = cbfs_get_file(media, name); + struct cbfs_file_handler f; + int c; + struct cbfs_media default_media; + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return NULL; + } + } + c = cbfs_find_file(media, &f, name, type); + if (c == 0){ + DEBUG("Found file. Will be mapping it now!\n"); if (sz) *sz = 0; - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); + if (f.file.type != type) { + ERROR("File '%s' is of type %x, but we requested %x.\n", name, f.file.type, type); return NULL; } - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); + if (sz) + *sz = f.data_len; + return media->map(media, f.data_offset, f.data_len + f.file.offset); + } + else { + DEBUG("condition not successful\n"); + ERROR("File Not Found\n"); return NULL; } - - if (sz) - *sz = ntohl(file->len); - - return (void *)CBFS_SUBHEADER(file); } int cbfs_decompress(int algo, void *src, void *dst, int len)

1 0

Patch merged into coreboot/master: 931c1dc stdlib: Drop duplicates of min() and max()
by gerrit＠coreboot.org 01 Jul '14

01 Jul '14

the following patch was just integrated into master: commit 931c1dcec043e6baac718a94f8731cc31461d4db Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 09:40:19 2014 +0300 stdlib: Drop duplicates of min() and max() Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6161 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6161 for details. -gerrit

1 0

Patch merged into coreboot/master: f41cb4e ROMCC: Fix collision with token name max
by gerrit＠coreboot.org 01 Jul '14

01 Jul '14

the following patch was just integrated into master: commit f41cb4ecd23c951e1c1c4fef0c99772983a3eba4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 13:15:42 2014 +0300 ROMCC: Fix collision with token name max Even with !defined(__ROMCC__) in the file, romcc chokes on these parameter names after we declare common max() macro in stdlib.h. Change-Id: Id4f2aa61d9c5b19f428452cd475b1b2ed9a70f52 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6165 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6165 for details. -gerrit

1 0

Patch set updated for coreboot: bcda7c3 AMD SPI: Optimise for longer writes
by Kyösti Mälkki 01 Jul '14

01 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6164 -gerrit commit bcda7c3d8c8f3f4d0782ec2046b2f52a8b743d32 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 07:34:36 2014 +0300 AMD SPI: Optimise for longer writes Leave it to the implementation of flash->write() to split the writes to match SPI controller and SPI flash part restrictions. This allows for some optimisation for auto-address-increment (AAI) commands. Kconfig AMD_SB_SPI_TX_LEN can be kept as local. Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/spi.c | 7 +------ src/southbridge/amd/Kconfig | 9 --------- src/southbridge/amd/agesa/hudson/spi.c | 14 ++++++++++++++ src/southbridge/amd/cimx/sb800/spi.c | 14 ++++++++++++++ 4 files changed, 29 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c index f4ffa62..78ddf5e 100644 --- a/src/cpu/amd/agesa/spi.c +++ b/src/cpu/amd/agesa/spi.c @@ -40,12 +40,7 @@ void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) flash->erase(flash, pos, size); flash->write(flash, pos, sizeof(len), &len); - - u32 nvram_pos; - for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { - flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); - } - flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); + flash->write(flash, pos + sizeof(len), len, buf); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 39aeb09..867afca 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,12 +14,3 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig - -if CPU_AMD_AGESA - -config AMD_SB_SPI_TX_LEN - int - default 4 - depends on SPI_FLASH - -endif diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 3f3543a..fbccf22 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -108,6 +109,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, bytesout = bitsout / 8; bytesin = bitsin / 8; + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f8cea7e..342685e 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -77,6 +78,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, bytesout = bitsout / 8; bytesin = bitsin / 8; + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; readwrite = (bytesin + readoffby1) << 4 | bytesout;

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coreboot-gerrit July 2014