coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 77fbb4b console: Split console_init()
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5331 -gerrit commit 77fbb4b38fd2a947e451ec82283b32082f255cf5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 10:04:31 2014 +0200 console: Split console_init() Splitting the version prompt satisfies some requirements ROMCC sets for the order in which we include source files. Also GDB stub will need console hardware before entering main(). Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/bootblock_simple.c | 2 +- src/arch/x86/lib/Makefile.inc | 2 -- src/arch/x86/lib/romcc_console.c | 3 +-- src/console/Makefile.inc | 12 ++++----- src/console/console.c | 38 ++------------------------ src/console/init.c | 56 +++++++++++++++++++++++++++++++++++++++ src/include/console/console.h | 1 + 7 files changed, 67 insertions(+), 47 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 2c8e053..bc3ef53 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -56,7 +56,7 @@ void main(void) bootblock_mainboard_init(); } -#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if CONFIG_BOOTBLOCK_CONSOLE console_init(); #endif diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 8588c76..c173011 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -27,5 +27,3 @@ smm-y += rom_media.c rmodules-y += memset.c rmodules-y += memcpy.c rmodules-y += memmove.c - -$(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 4bd3ad4..3f8f62f 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -129,7 +129,6 @@ static void __console_tx_string(int loglevel, const char *str) /* if included by romcc, include the sources, too. romcc can't use prototypes */ #include <console/console.c> +#include <console/init.c> #include <console/post.c> #include <console/die.c> - - diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index df08e80..f8bbf22 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += printk.c -ramstage-y += console.c +ramstage-y += init.c console.c ramstage-y += vtxprintf.c ramstage-y += vsprintf.c ramstage-y += post.c @@ -9,12 +9,12 @@ smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c -romstage-y += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += init.c console.c romstage-y += post.c romstage-y += die.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c -bootblock-y += console.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c @@ -25,6 +25,6 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c -$(obj)/console/console.ramstage.o : $(obj)/build.h -$(obj)/console/console.romstage.o : $(obj)/build.h -$(obj)/console/console.bootblock.o : $(obj)/build.h +$(obj)/console/init.ramstage.o : $(obj)/build.h +$(obj)/console/init.romstage.o : $(obj)/build.h +$(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 348264d..1712877 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,30 +24,13 @@ #include <console/ne2k.h> #include <console/spkmodem.h> -#include <build.h> -#include <arch/hlt.h> -#include <arch/io.h> - -#if CONFIG_EARLY_PCI_BRIDGE -/* FIXME: ROMCC chokes on PCI headers. */ -#include <device/pci.h> -#endif - #ifndef __PRE_RAM__ -#include <string.h> -#include <types.h> -#include <option.h> /* initialize the console */ -void console_init(void) +void console_hw_init(void) { struct console_driver *driver; - if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) - console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_EARLY_PCI_BRIDGE - pci_early_bridge_init(); -#endif for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -104,14 +87,8 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -void console_init(void) +void console_hw_init(void) { -#if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ - !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE - -#if CONFIG_EARLY_PCI_BRIDGE - pci_early_bridge_init(); -#endif #if CONFIG_CONSOLE_SERIAL uart_init(); #endif @@ -127,16 +104,5 @@ void console_init(void) #if CONFIG_CONSOLE_USB && CONFIG_USBDEBUG_IN_ROMSTAGE && !defined(__BOOT_BLOCK__) usbdebug_init(); #endif - - static const char console_test[] = - "\n\ncoreboot-" - COREBOOT_VERSION - COREBOOT_EXTRA_VERSION - " " - COREBOOT_BUILD - " starting...\n"; - print_info(console_test); - -#endif /* CONFIG_EARLY_CONSOLE */ } #endif diff --git a/src/console/init.c b/src/console/init.c new file mode 100644 index 0000000..28934e7 --- /dev/null +++ b/src/console/init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <build.h> +#include <console/console.h> +#include <console/uart.h> +#include <option.h> + +#if CONFIG_EARLY_PCI_BRIDGE +/* FIXME: ROMCC chokes on PCI headers. */ +#include <device/pci.h> +#endif + +void console_init(void) +{ +#if !defined(__PRE_RAM__) + if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) + console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#endif + +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); +#endif + + console_hw_init(); + +#if defined(__PRE_RAM__) + static const char console_test[] = + "\n\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION + " " + COREBOOT_BUILD + " starting...\n"; + + print_info(console_test); +#endif +} diff --git a/src/include/console/console.h b/src/include/console/console.h index a089729..6d1b01a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -53,6 +53,7 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); +void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); void post_code(u8 value);

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Patch set updated for coreboot: 89d34b8 OxPCIe uart: Move under drivers/uart
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5329 -gerrit commit 89d34b881b3da13ccd2657f2681c9e1928da6834 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 15:15:12 2014 +0200 OxPCIe uart: Move under drivers/uart This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/Kconfig | 1 - src/drivers/Makefile.inc | 1 - src/drivers/oxford/Kconfig | 1 - src/drivers/oxford/Makefile.inc | 1 - src/drivers/oxford/oxpcie/Kconfig | 10 --- src/drivers/oxford/oxpcie/Makefile.inc | 4 -- src/drivers/oxford/oxpcie/oxpcie.c | 73 -------------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 111 ------------------------------- src/drivers/uart/Kconfig | 11 +++ src/drivers/uart/Makefile.inc | 5 ++ src/drivers/uart/oxpcie.c | 73 ++++++++++++++++++++ src/drivers/uart/oxpcie_early.c | 111 +++++++++++++++++++++++++++++++ 12 files changed, 200 insertions(+), 202 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..1a5f8ff 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -27,7 +27,6 @@ source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig source src/drivers/ipmi/Kconfig source src/drivers/maxim/Kconfig -source src/drivers/oxford/Kconfig source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 148e257..f11e4b8 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -25,7 +25,6 @@ subdirs-y += i2c subdirs-y += intel subdirs-y += maxim subdirs-y += net -subdirs-y += oxford subdirs-y += parade subdirs-y += realtek subdirs-y += sil diff --git a/src/drivers/oxford/Kconfig b/src/drivers/oxford/Kconfig deleted file mode 100644 index cd7c27c..0000000 --- a/src/drivers/oxford/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/oxford/oxpcie/Kconfig diff --git a/src/drivers/oxford/Makefile.inc b/src/drivers/oxford/Makefile.inc deleted file mode 100644 index 732face..0000000 --- a/src/drivers/oxford/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig deleted file mode 100644 index c2ea7b6..0000000 --- a/src/drivers/oxford/oxpcie/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config DRIVERS_OXFORD_OXPCIE - bool "Oxford OXPCIe952" - default n - depends on PCI - select DRIVERS_UART_8250MEM - select EARLY_PCI_BRIDGE - help - Support for Oxford OXPCIe952 serial port PCIe cards. - Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc deleted file mode 100644 index 5e3e6e5..0000000 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) -ramstage-y += oxpcie_early.c oxpcie.c -romstage-y += oxpcie_early.c -endif diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c deleted file mode 100644 index 76119d2..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include <console/uart.h> -#include <arch/io.h> - -static void oxford_oxpcie_enable(device_t dev) -{ - printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - - struct resource *res = find_resource(dev, 0x10); - if (!res) { - printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); - return; - } - - printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); - printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); - printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); -} - - -static void oxford_oxpcie_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); - - /* Re-initialize OXPCIe base address after set_resources */ - u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - oxford_remap(mmio_base & ~0xf); -} - -static struct device_operations oxford_oxpcie_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = oxford_oxpcie_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = oxford_oxpcie_enable, - .scan_bus = 0, -}; - -static const struct pci_driver oxford_oxpcie_driver __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc158, -}; - -static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc11b, -}; diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c deleted file mode 100644 index b81fa89..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <stddef.h> -#include <arch/io.h> -#include <arch/early_variables.h> -#include <boot/coreboot_tables.h> -#include <console/uart.h> -#include <device/pci.h> -#include <device/pci_def.h> - -static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; - -int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) -{ - pci_devfn_t device = PCI_DEV(bus, dev, 0); - - u32 id = pci_read_config32(device, PCI_VENDOR_ID); - switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ - /* On this device function 0 is the parallel port, and - * function 3 is the serial port. So let's go look for - * the UART. - */ - device = PCI_DEV(bus, dev, 3); - id = pci_read_config32(device, PCI_VENDOR_ID); - if (id != 0xc11b1415) - return -1; - break; - case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ - case 0xc1581415: /* e.g. Startech MPEX2S952 */ - break; - default: - /* No UART here. */ - return -1; - } - - /* Sanity-check, we assume fixed location. */ - if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) - return -1; - - /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable memory on device */ - u16 reg16 = pci_read_config16(device, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(device, PCI_COMMAND, reg16); - - car_set_var(oxpcie_present, 1); - return 0; -} - -static int oxpcie_uart_active(void) -{ - return (car_get_var(oxpcie_present)); -} - -unsigned int uart_platform_base(int idx) -{ - if (idx == 0 && oxpcie_uart_active()) - return uart0_base; - if (idx == 1 && oxpcie_uart_active()) - return uart1_base; - return 0; -} - -#ifndef __PRE_RAM__ -void oxford_remap(u32 new_base) -{ - uart0_base = new_base + 0x1000; - uart1_base = new_base + 0x2000; -} - -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); - serial.baud = default_baudrate(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif - -unsigned int uart_platform_refclk(void) -{ - return 62500000; -} diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 889c69a..a979437 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -21,6 +21,17 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_OXPCIE + bool "Oxford OXPCIe952" + default n + depends on PCI + select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE + help + Support for Oxford OXPCIe952 serial port PCIe cards. + Currently only devices with the vendor ID 0x1415 and device ID + 0xc158 or 0xc11b will work. + config DRIVERS_UART_PL011 bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 286bff2..5164282 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -18,6 +18,11 @@ ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif +ifeq ($(CONFIG_DRIVERS_UART_OXPCIE),y) +ramstage-y += oxpcie_early.c oxpcie.c +romstage-y += oxpcie_early.c +endif + ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c new file mode 100644 index 0000000..76119d2 --- /dev/null +++ b/src/drivers/uart/oxpcie.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <console/uart.h> +#include <arch/io.h> + +static void oxford_oxpcie_enable(device_t dev) +{ + printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); + + struct resource *res = find_resource(dev, 0x10); + if (!res) { + printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", + (read32(res->base) >> 8), (read32(res->base) & 0xff)); + printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", + (read32(res->base + 4) & 3)); + printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); +} + + +static void oxford_oxpcie_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + /* Re-initialize OXPCIe base address after set_resources */ + u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); +} + +static struct device_operations oxford_oxpcie_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = oxford_oxpcie_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = oxford_oxpcie_enable, + .scan_bus = 0, +}; + +static const struct pci_driver oxford_oxpcie_driver __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc158, +}; + +static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc11b, +}; diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c new file mode 100644 index 0000000..b81fa89 --- /dev/null +++ b/src/drivers/uart/oxpcie_early.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <stddef.h> +#include <arch/io.h> +#include <arch/early_variables.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> + +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t device = PCI_DEV(bus, dev, 0); + + u32 id = pci_read_config32(device, PCI_VENDOR_ID); + switch (id) { + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ + /* On this device function 0 is the parallel port, and + * function 3 is the serial port. So let's go look for + * the UART. + */ + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); + if (id != 0xc11b1415) + return -1; + break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ + case 0xc1581415: /* e.g. Startech MPEX2S952 */ + break; + default: + /* No UART here. */ + return -1; + } + + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + + /* Setup base address on device */ + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable memory on device */ + u16 reg16 = pci_read_config16(device, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(device, PCI_COMMAND, reg16); + + car_set_var(oxpcie_present, 1); + return 0; +} + +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); +} + +unsigned int uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} + +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 62500000; +}

1 0

Patch set updated for coreboot: 12f4168 console: Simplify vtxprintf
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5334 -gerrit commit 12f4168c91f4bbd853d07cbb30a599166875c5ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 14:28:17 2014 +0200 console: Simplify vtxprintf We do not need ROMCC support here and using wrappers for console_tx_byte we can simplify this code. Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 10 ++++++++-- src/console/vsprintf.c | 2 +- src/console/vtxprintf.c | 42 ++++++++--------------------------------- src/include/console/console.h | 1 + src/include/console/vtxprintf.h | 7 ++----- 5 files changed, 20 insertions(+), 42 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index 63d37cc..1d6b9bf 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -5,6 +5,7 @@ * */ +#include <stddef.h> #include <smp/node.h> #include <smp/spinlock.h> #include <console/vtxprintf.h> @@ -20,6 +21,11 @@ void do_putchar(unsigned char byte) console_tx_byte(byte); } +void wrap_putchar(unsigned char byte, void *data) +{ + do_putchar(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -37,7 +43,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(do_putchar, fmt, args); + i = vtxprintf(wrap_putchar, fmt, args, NULL); va_end(args); console_tx_flush(); @@ -51,7 +57,7 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(do_putchar, fmt, args); + vtxprintf(wrap_putchar, fmt, args, NULL); console_tx_flush(); } #endif diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 1fb834f..fd6646b 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -48,7 +48,7 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) ctx.str_buf = buf; ctx.buf_limit = size ? size - 1 : 0; - i = vtxdprintf(str_tx_byte, fmt, args, &ctx); + i = vtxprintf(str_tx_byte, fmt, args, &ctx); if (size) *ctx.str_buf = '\0'; diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 502d53e..d4d70b6 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -8,15 +8,7 @@ #include <console/console.h> #include <console/vtxprintf.h> -#if !defined (__ROMCC__) && !defined(__SMM__) -#define DATA_ARG , data -#define DATA_ARG_DECL , void *data -#else -#define DATA_ARG -#define DATA_ARG_DECL -#endif - -#define call_tx(x) tx_byte(x DATA_ARG) +#define call_tx(x) tx_byte(x, data) /* haha, don't need ctype.c */ #define isdigit(c) ((c) >= '0' && (c) <= '9') @@ -40,9 +32,9 @@ static int skip_atoi(const char **s) #define SPECIAL 32 /* 0x */ #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), - unsigned long long num, int base, int size, int precision, int type - DATA_ARG_DECL) +static int number(void (*tx_byte)(unsigned char byte, void *data), + unsigned long long num, int base, int size, int precision, int type, + void *data) { char c,sign,tmp[66]; const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; @@ -112,12 +104,8 @@ static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), } -#if !defined (__ROMCC__) && !defined(__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data) -#else -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -#endif { int len; unsigned long long num; @@ -135,7 +123,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args #if defined(__SMM__) && CONFIG_SMM_TSEG /* Fix pointer in TSEG */ - tx_byte = console_tx_byte; + tx_byte = wrap_putchar; #endif for (count=0; *fmt ; ++fmt) { @@ -236,7 +224,7 @@ repeat: } count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, - field_width, precision, flags DATA_ARG); + field_width, precision, flags, data); continue; case 'n': @@ -300,21 +288,7 @@ repeat: } else { num = va_arg(args, unsigned int); } - count += number(tx_byte, num, base, field_width, precision, flags DATA_ARG); + count += number(tx_byte, num, base, field_width, precision, flags, data); } return count; } - - -#if !defined (__ROMCC__) && !defined(__SMM__) -static void wrap_tx_byte (unsigned char byte, void *data) -{ - void (*tx_byte)(unsigned char byte) = data; - tx_byte (byte); -} - -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -{ - return vtxdprintf(wrap_tx_byte, fmt, args, tx_byte); -} -#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index c184f83..e19abec 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -75,6 +75,7 @@ static inline void do_putchar(unsigned char byte) {} int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); +void wrap_putchar(unsigned char byte, void *data); #define printk(LEVEL, fmt, args...) \ do { \ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index c5daf9d..3f0c63e 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -34,10 +34,7 @@ typedef __builtin_va_list va_list; #include <stdarg.h> #endif -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args); - -#if !defined (__ROMCC__) && !defined (__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data); -#endif +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), + const char *fmt, va_list args, void *data); #endif

1 0

Patch set updated for coreboot: e7b08bb console: Remove old fix for DEBUG_SMI
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5335 -gerrit commit e7b08bb4800ecf30dbcc22ed78410f14973f44e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 19:50:07 2014 +0200 console: Remove old fix for DEBUG_SMI No longer needed as wrap_putchar() survives SMM relocation to TSEG. Change-Id: I6143844b0b9902ef63baf3e5781a5dc4f54234be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 3 +-- src/console/vtxprintf.c | 5 ----- src/include/console/console.h | 1 - 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index 1d6b9bf..2fa160b 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -21,7 +21,7 @@ void do_putchar(unsigned char byte) console_tx_byte(byte); } -void wrap_putchar(unsigned char byte, void *data) +static void wrap_putchar(unsigned char byte, void *data) { do_putchar(byte); } @@ -61,4 +61,3 @@ void do_vtxprintf(const char *fmt, va_list args) console_tx_flush(); } #endif - diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index d4d70b6..23db037 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -121,11 +121,6 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), int count; -#if defined(__SMM__) && CONFIG_SMM_TSEG - /* Fix pointer in TSEG */ - tx_byte = wrap_putchar; -#endif - for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { call_tx(*fmt), count++; diff --git a/src/include/console/console.h b/src/include/console/console.h index e19abec..c184f83 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -75,7 +75,6 @@ static inline void do_putchar(unsigned char byte) {} int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); -void wrap_putchar(unsigned char byte, void *data); #define printk(LEVEL, fmt, args...) \ do { \

1 0

Patch set updated for coreboot: b6d4859 console: Unify do_printk()
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5332 -gerrit commit b6d4859443aa8dfab53ce942976ad101447943a3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 27 15:09:13 2014 +0200 console: Unify do_printk() Change-Id: I6c50e47d9d2d0d1f42beee477e49b2a0054d1786 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 21 +-------------------- src/arch/x86/lib/romstage_console.c | 25 ------------------------- src/console/Makefile.inc | 8 +++----- src/console/init.c | 4 ++++ src/console/printk.c | 9 ++++++--- 5 files changed, 14 insertions(+), 53 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 7614531..a85f554 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <console/cbmem_console.h> #include <console/uart.h> -#include <console/vtxprintf.h> /* FIXME: need to make console driver more generic */ void console_tx_byte(unsigned char byte) @@ -36,27 +35,9 @@ void console_tx_byte(unsigned char byte) #endif } -static void _console_tx_flush(void) +void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif } - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0337245..c80cf8c 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -17,14 +17,12 @@ * MA 02110-1301 USA */ -#include <smp/node.h> #include <console/console.h> #include <console/cbmem_console.h> #include <console/uart.h> #include <console/usb.h> #include <console/ne2k.h> #include <console/spkmodem.h> -#include <console/vtxprintf.h> void console_tx_byte(unsigned char byte) { @@ -60,26 +58,3 @@ void console_tx_flush(void) usb_tx_flush(0); #endif } - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - -#if CONFIG_SQUELCH_EARLY_SMP - if (!boot_cpu()) - return 0; -#endif - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - console_tx_flush(); - - return i; -} diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index f8bbf22..ef917da 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -1,19 +1,17 @@ -ramstage-y += printk.c +ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c -ramstage-y += vtxprintf.c -ramstage-y += vsprintf.c ramstage-y += post.c ramstage-y += die.c smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c printk.c romstage-$(CONFIG_EARLY_CONSOLE) += init.c console.c romstage-y += post.c romstage-y += die.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c diff --git a/src/console/init.c b/src/console/init.c index 28934e7..c6ceab5 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -29,6 +29,10 @@ #include <device/pci.h> #endif +#if !defined(__PRE_RAM__) +int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#endif + void console_init(void) { #if !defined(__PRE_RAM__) diff --git a/src/console/printk.c b/src/console/printk.c index e24c752..7ea8c06 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -5,14 +5,12 @@ * */ +#include <smp/node.h> #include <smp/spinlock.h> #include <console/vtxprintf.h> #include <console/console.h> #include <trace.h> -int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - DECLARE_SPIN_LOCK(console_lock) int do_printk(int msg_level, const char *fmt, ...) @@ -24,6 +22,11 @@ int do_printk(int msg_level, const char *fmt, ...) return 0; } +#if CONFIG_SQUELCH_EARLY_SMP && defined(__PRE_RAM__) + if (!boot_cpu()) + return 0; +#endif + DISABLE_TRACE; spin_lock(&console_lock);

1 0

Patch set updated for coreboot: dade9a0 console: Hide global console_loglevel
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5333 -gerrit commit dade9a017fe0e99e41d657ad7ced2c47c5cdf41e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 14:37:27 2014 +0200 console: Hide global console_loglevel Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 21 +++++++-------------- src/console/init.c | 10 ++++++++-- src/console/printk.c | 3 +-- src/include/console/console.h | 10 +--------- 4 files changed, 17 insertions(+), 27 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 3f8f62f..a6e8ecc 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,18 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <console/loglevel.h> -#include <console/post_codes.h> #include <console/uart.h> #include <console/ne2k.h> -/* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL +/* While in romstage, console loglevel is built-time constant. */ +#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" @@ -60,7 +53,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif @@ -73,7 +66,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) static void __console_tx_hex8(int loglevel, unsigned char value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } @@ -84,7 +77,7 @@ static void __console_tx_hex8(int loglevel, unsigned char value) static void __console_tx_hex16(int loglevel, unsigned short value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 12U) & 0x0fU); __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); @@ -97,7 +90,7 @@ static void __console_tx_hex16(int loglevel, unsigned short value) static void __console_tx_hex32(int loglevel, unsigned int value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 28U) & 0x0fU); __console_tx_nibble((value >> 24U) & 0x0fU); __console_tx_nibble((value >> 20U) & 0x0fU); @@ -114,7 +107,7 @@ static void __console_tx_hex32(int loglevel, unsigned int value) static void __console_tx_string(int loglevel, const char *str) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { unsigned char ch; while((ch = *str++) != '\0') { if (ch == '\n') diff --git a/src/console/init.c b/src/console/init.c index c6ceab5..d7c8cc3 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -29,8 +29,14 @@ #include <device/pci.h> #endif -#if !defined(__PRE_RAM__) -int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if !defined(__ROMCC__) +/* While in romstage, console loglevel is built-time constant. */ +static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + +int console_log_level(int msg_level) +{ + return (console_loglevel >= msg_level); +} #endif void console_init(void) diff --git a/src/console/printk.c b/src/console/printk.c index 7ea8c06..fb1194e 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -18,9 +18,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_list args; int i; - if (msg_level > console_loglevel) { + if (!console_log_level(msg_level)) return 0; - } #if CONFIG_SQUELCH_EARLY_SMP && defined(__PRE_RAM__) if (!boot_cpu()) diff --git a/src/include/console/console.h b/src/include/console/console.h index 6d1b01a..aa5273f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -40,18 +40,10 @@ struct console_driver { /* Defined by the linker... */ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[]; - -extern int console_loglevel; -#else -/* __PRE_RAM__ */ -/* Using a global variable can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL #endif #ifndef __ROMCC__ +int console_log_level(int msg_level); void console_init(void); void console_hw_init(void); void console_tx_byte(unsigned char byte);

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Patch set updated for coreboot: be6f6b4 console: Add printk helper for ChromeOS
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5347 -gerrit commit be6f6b4282b33506c3bc6f58d545774939cd641b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 6 16:55:05 2014 +0200 console: Add printk helper for ChromeOS Do not expose console_tx_flush() to ChromeOS as that function is part of lower-level implementation. Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 8 ++++++++ src/include/console/console.h | 10 ++++++++++ src/vendorcode/google/chromeos/vboot_loader.c | 3 +-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index fb1194e..c61f63e 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -40,3 +40,11 @@ int do_printk(int msg_level, const char *fmt, ...) return i; } + +#if CONFIG_CHROMEOS +void do_vtxprintf(const char *fmt, va_list args) +{ + vtxprintf(console_tx_byte, fmt, args); + console_tx_flush(); +} +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index aa5273f..e7b4253 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -82,6 +82,16 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#if CONFIG_CHROMEOS +/* FIXME: Collision of varargs with AMD headers without guard. */ +#include <console/vtxprintf.h> +#if !defined(__PRE_RAM__) || CONFIG_EARLY_CONSOLE +void do_vtxprintf(const char *fmt, va_list args); +#else +static inline void do_vtxprintf(const char *fmt, va_list args) {}; +#endif +#endif + #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) #define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 0c5220a..943ad17 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -64,8 +64,7 @@ out: /* Helper routines for the vboot stub. */ static void log_msg(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); - console_tx_flush(); + do_vtxprintf(fmt, args); } static void fatal_error(void)

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Patch merged into coreboot/master: 96d6f0d hp/pavilion_m6_1035dx: Remove inexistent devices from devicetree
by gerrit＠coreboot.org 06 Apr '14

06 Apr '14

the following patch was just integrated into master: commit 96d6f0de6526c79e3f0518c36a2c14d3008aa092 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 11:11:14 2014 -0500 hp/pavilion_m6_1035dx: Remove inexistent devices from devicetree This removes ominous "PCI: xx:xx.x not found" messages from coreboot console. Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5461 for details. -gerrit

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Patch set updated for coreboot: eadcc77 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
by Idwer Vollering 06 Apr '14

06 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit eadcc770b07e24d3bb01f4e9253516f0a6a6a345 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index fe7dc9b..628d6f3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -599,13 +599,8 @@ config PAYLOAD_TIANOCORE endchoice -choice - prompt "SeaBIOS version" - default SEABIOS_STABLE - depends on PAYLOAD_SEABIOS - config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

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Patch set updated for coreboot: a7d7cf8 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
by Idwer Vollering 06 Apr '14

06 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit a7d7cf8d6025b929db60a649e89028bcd60e3612 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index fe7dc9b..628d6f3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -599,13 +599,8 @@ config PAYLOAD_TIANOCORE endchoice -choice - prompt "SeaBIOS version" - default SEABIOS_STABLE - depends on PAYLOAD_SEABIOS - config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

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coreboot-gerrit April 2014