Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093
-gerrit
commit 61ca9e575b52c0b2e890f8747b7f32b94d1bebae
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Feb 2 11:23:26 2014 +0100
payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4
On Monday, 12/23/2013, 12:34 -0500 Kevin O'Connor wrote:
> The 1.7.4 version of SeaBIOS has now been released. For more
> information on the release, please see:
>
> http://seabios.org/Releases
>
>
> New in this release:
>
> * Support for obtaining ACPI tables directly from QEMU.
> * Initial support for XHCI USB controllers (initially for QEMU only).
> * Support for booting from "pvscsi" devices on QEMU.
> * Enhanced floppy driver - improved support for real hardware.
> * coreboot cbmem console support.
> * Optional support for using the 9-segment instead of the e-segment
> for local variables.
> * Improved internal timer code and accuracy.
> * SeaVGABIOS improvements
> * Better support for legacy X.org releases with incomplete x86emu
> emulation.
> * Support for using an internal stack to reduce caller's stack
> usage.
> * Back port of new "bochs dispi" interface video modes.
> * Several bug fixes and code cleanups
> * Source code separated out into additional hardware and firmware
> directories.
> * Update to latest version of Kconfig
>
>
> For information on obtaining SeaBIOS, please see:
>
> http://seabios.org/Download
Successfully tested on the Asus M2V-MX SE.
----- [ SeaBIOS rel-1.7.4-0-g96917a8-20140201_152655-my-asus-m2v-mx_se ] -----
Found coreboot cbmem console @ 7dec0400
Found mainboard ASUS M2V-MX SE
Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
payloads/external/SeaBIOS/Makefile.inc | 2 +-
src/Kconfig | 7 +------
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 84f1515..23b064c 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116
+TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59
unexport KCONFIG_AUTOCONFIG
diff --git a/src/Kconfig b/src/Kconfig
index fe7dc9b..628d6f3 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -599,13 +599,8 @@ config PAYLOAD_TIANOCORE
endchoice
-choice
- prompt "SeaBIOS version"
- default SEABIOS_STABLE
- depends on PAYLOAD_SEABIOS
-
config SEABIOS_STABLE
- bool "1.7.2.1"
+ bool "1.7.4"
help
Stable SeaBIOS version
config SEABIOS_MASTER
Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093
-gerrit
commit f991e4f8458f1e344c3683c0455054cd50aa577d
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Feb 2 11:23:26 2014 +0100
payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4
On Monday, 12/23/2013, 12:34 -0500 Kevin O'Connor wrote:
> The 1.7.4 version of SeaBIOS has now been released. For more
> information on the release, please see:
>
> http://seabios.org/Releases
>
>
> New in this release:
>
> * Support for obtaining ACPI tables directly from QEMU.
> * Initial support for XHCI USB controllers (initially for QEMU only).
> * Support for booting from "pvscsi" devices on QEMU.
> * Enhanced floppy driver - improved support for real hardware.
> * coreboot cbmem console support.
> * Optional support for using the 9-segment instead of the e-segment
> for local variables.
> * Improved internal timer code and accuracy.
> * SeaVGABIOS improvements
> * Better support for legacy X.org releases with incomplete x86emu
> emulation.
> * Support for using an internal stack to reduce caller's stack
> usage.
> * Back port of new "bochs dispi" interface video modes.
> * Several bug fixes and code cleanups
> * Source code separated out into additional hardware and firmware
> directories.
> * Update to latest version of Kconfig
>
>
> For information on obtaining SeaBIOS, please see:
>
> http://seabios.org/Download
Successfully tested on the Asus M2V-MX SE.
----- [ SeaBIOS rel-1.7.4-0-g96917a8-20140201_152655-my-asus-m2v-mx_se ] -----
Found coreboot cbmem console @ 7dec0400
Found mainboard ASUS M2V-MX SE
Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
payloads/external/SeaBIOS/Makefile.inc | 2 +-
src/Kconfig | 7 +------
src/arch/x86/Makefile.inc | 2 +-
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 84f1515..23b064c 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116
+TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59
unexport KCONFIG_AUTOCONFIG
diff --git a/src/Kconfig b/src/Kconfig
index fe7dc9b..628d6f3 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -599,13 +599,8 @@ config PAYLOAD_TIANOCORE
endchoice
-choice
- prompt "SeaBIOS version"
- default SEABIOS_STABLE
- depends on PAYLOAD_SEABIOS
-
config SEABIOS_STABLE
- bool "1.7.2.1"
+ bool "1.7.4"
help
Stable SeaBIOS version
config SEABIOS_MASTER
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3b17ce3..4435703 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -467,7 +467,7 @@ seabios:
OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
AS="$(AS)" CPP="$(CPP)" \
CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
- CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \
+ CONFIG_SEABIOS_STABLE=$(call strip_quotes,$(CONFIG_SEABIOS_STABLE)) \
OUT=$(abspath $(obj)) IASL="$(IASL)"
filo:
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5467
-gerrit
commit 5c95341b3d6bf206302adf3234d9694610904ff3
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Apr 6 15:19:56 2014 -0500
vendorcode/amd/agesa: Do not hardcode ROM base address
The ROM address range is set up in the LPC PCI device, register 0x6c.
Coreboot already sets that up correctly in the bootblock, however
AGESA overrides that to 0xffffff00, which will always map the ROM from
0xff000000. This may conflict with other devices which are assigned
address space in that range.
If a device is assigned a range between 0xff000000 and the real ROM
base, accesses to that device will be diverted to the system ROM,
regardless of how other BARs are set up. Since we already need to set
up the ROM address range in the bootblock, before calling AGESA, just
remove the override from AGESA.
Note that not all AGESA versions override this mapping.
Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c | 2 --
.../agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c | 2 --
.../agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c
index 8e9bee7..e4aca36 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c
@@ -98,8 +98,6 @@ FchInitResetLpc (
//
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader);
-
ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetLpcPciTable[0]), sizeof (FchInitResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->LegacyFree ) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
index adbfab3..36259d3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
@@ -99,8 +99,6 @@ FchInitResetLpcProgram (
//
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader);
-
ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
//
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
index 1a02218..ab71bb9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
@@ -125,8 +125,6 @@ FchInitResetLpcProgram (
//
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader);
-
ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), sizeof (FchInitYangtzeResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->Spi.LpcClk0 ) {
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444
-gerrit
commit 4908fbaa32f1016dd52178e218dd5e3e8cb68903
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Apr 1 16:02:08 2014 -0500
ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
The GP15 ACPI object was used to get the state of the lid. However
GP15 is specific to certain Intel chipsets, and will not always be in
the ACPI namespace. Instead of hardcoding this object, let the
mainboard define it.
Also, document the ACPI interface for the EC.
Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/ec/compal/ene932/acpi/ec.asl | 2 +-
src/ec/compal/ene932/documentation.txt | 24 ++++++++++++++++++++++++
src/mainboard/google/parrot/acpi/ec.asl | 3 +++
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl
index cb50a21..a042d75 100644
--- a/src/ec/compal/ene932/acpi/ec.asl
+++ b/src/ec/compal/ene932/acpi/ec.asl
@@ -273,7 +273,7 @@ Device (EC0)
Store (ADPT, \PWRS)
// Initialize LID switch state
- Store (GP15, \LIDS)
+ Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS)
// Force a read of CPU temperature
Store (CTML, Local0)
diff --git a/src/ec/compal/ene932/documentation.txt b/src/ec/compal/ene932/documentation.txt
new file mode 100644
index 0000000..9b29415
--- /dev/null
+++ b/src/ec/compal/ene932/documentation.txt
@@ -0,0 +1,24 @@
+
+Accessing the EC space
+======================
+
+The ACPI implementation uses the standard I/O ports 0x62 and 0x66 to access the
+EC functionality. Accesses to these ports must be directed to the LPC bus to
+which the EC is connected.
+
+
+Interfacing with the ASL files
+==============================
+
+The mainboard code must define several variables for the ASL files.
+
+* EC_SMI
+ Defines the General Purpose Event (GPE) corresponding to the embedded
+ controller's SCI line.
+* EC_ACPI_LID_SWITCH_OBJECT
+ Defines the APCI object which reads the state of the lid, with 0 = open, and
+ 1 = closed. This is usually the bit which reads the GPIO input coresponding to
+ the lid switch.
+* PNOT()
+ The mainboard must define a PNOT method to handle power state notifications
+ and Notify CPU device objects to re-evaluate their _PPC and _CST tables.
diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl
index 522a0b9..a0ee9d5 100644
--- a/src/mainboard/google/parrot/acpi/ec.asl
+++ b/src/mainboard/google/parrot/acpi/ec.asl
@@ -21,5 +21,8 @@
#include "../ec.h"
#define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI
+/* GP15 is defined in the southbridge's ASL */
+#define EC_ACPI_LID_SWITCH_OBJECT GP15
+
/* ACPI code for EC functions */
#include "../../../../ec/compal/ene932/acpi/ec.asl"
the following patch was just integrated into master:
commit 56fa0f2fd91ba89d1fe7ff2bcab773ffcf9bff4b
Author: Idwer Vollering <vidwer(a)gmail.com>
Date: Sat Mar 29 13:13:10 2014 +0100
asus/f2a85-m: Sanitize #includes
Based on the same reasoning as this commit:
1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
See http://review.coreboot.org/5420 for details.
-gerrit
the following patch was just integrated into master:
commit 4deb1ef15c47bb30ad995cf232dd356bf67fc7f7
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Sat Dec 7 22:29:36 2013 +0100
amd/agesa/hudson: Implement PNP resource setup in LPC bridge
The previous SBxxx generations were setting up LPC bridge based
on the PNP resources. Implement it also for AGESA Hudson.
The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS
(512 bytes). Make the code smart enough to detect already used
region and if any resource fits into AGESA defined region, do nothing.
Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
See http://review.coreboot.org/4497 for details.
-gerrit