coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 95e54da superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 06 Apr '14

06 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 95e54dad55ccfa7656c4b2c1ef99da30018da6a9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Note that these three Intel boards are ROMCC and so we can not clean up the early_serial #include directives in these particular mainboard/romstage's. However we fix here the superio so that other boards that are not ROMCC do not include early_serial.c Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 1 + src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 5 +++-- src/superio/intel/i3100/i3100.h | 6 +++++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..dbe824b 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,6 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..7d01dd3 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,7 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..fe8ab2f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,9 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..a7376b7 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..a0a9d15 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); + +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

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Patch merged into coreboot/master: eb9861b superio/winbond/w83627thg: Avoid .c includes
by gerrit＠coreboot.org 06 Apr '14

06 Apr '14

the following patch was just integrated into master: commit eb9861b742b851faff1fcf447e118c7acee59eff Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 14:40:24 2014 +1100 superio/winbond/w83627thg: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5449 for details. -gerrit

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Patch merged into coreboot/master: 583ecde jetway/nf81-t56n-lf: Sanitize #includes
by gerrit＠coreboot.org 06 Apr '14

06 Apr '14

the following patch was just integrated into master: commit 583ecdebec749cc6e052371f63e845c571adc465 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 17:54:26 2014 +1100 jetway/nf81-t56n-lf: Sanitize #includes Following the same reasoning as commit 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this board support. Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5414 for details. -gerrit

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Patch merged into coreboot/master: d74b6b4 superio/nuvoton/nct5104d: Avoid .c includes
by gerrit＠coreboot.org 06 Apr '14

06 Apr '14

the following patch was just integrated into master: commit d74b6b4803a1c95cef2476722fb6203571abf034 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 03:19:41 2014 +1100 superio/nuvoton/nct5104d: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5446 for details. -gerrit

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Patch merged into coreboot/master: 5b77158 superio/winbond/w83627ehg: Avoid .c includes
by gerrit＠coreboot.org 06 Apr '14

06 Apr '14

the following patch was just integrated into master: commit 5b77158891d28675c067fe5783a76fd0012df6ed Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 14:30:58 2014 +1100 superio/winbond/w83627ehg: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5448 for details. -gerrit

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Patch set updated for coreboot: aff48a9 AMD Fam15tn: Fix IOMMU scratch support in AGESA
by Rudolf Marek 06 Apr '14

06 Apr '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3316 -gerrit commit aff48a9c9517954eb79f5c73fb5c73c2c44ef569 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:00:25 2013 +0200 AMD Fam15tn: Fix IOMMU scratch support in AGESA The IOMMU support is broken and does not even compile. Adding the header file `GnbIommuScratch.h` for the function `GnbIommuScratchMemoryRangeInterface()` and fixing the 64-bit versus 32-bit address issue, the file compiles now and is therefore hooked up into the build system. Change-Id: I1924a113af12b186edcdf1956cb5ec5453aee34c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 8 +++- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 55 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..815ab48 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -203,6 +203,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..3fe0ff0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -78,6 +78,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 45d0cd7..9bdc854 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -57,6 +57,7 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" +#include "GnbIommuScratch.h" #define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S @@ -111,9 +112,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; } + /* align the address to 64 bytes boundary */ +#ifdef __x86_64__ AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; - +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..4edcb37 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * IOMMU scratch page + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: $ @e \$Date: $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif

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New patch to review for coreboot: fb0f9f3 mainboard/jetway/nf81-t56n-lf: Improve diags in romstage
by Edward O'Callaghan 06 Apr '14

06 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5465 -gerrit commit fb0f9f30bf5f7fcf1a59a8fa992d37ad409024f3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 6 12:34:56 2014 +1000 mainboard/jetway/nf81-t56n-lf: Improve diags in romstage romstage reports a completely unintelligible printf of "error level:", fix this and document meaning of the return values in source. Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 846d5c7..46c08a2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -52,6 +52,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) +/* + * Possible AGESA_STATUS values: + * + * 0x0 = AGESA_SUCCESS + * 0x1 = AGESA_UNSUPPORTED + * 0x2 = AGESA_BOUNDS_CHK + * 0x3 = AGESA_ALERT + * 0x4 = AGESA_WARNING + * 0x5 = AGESA_ERROR + * 0x6 = AGESA_CRITICAL + * 0x7 = AGESA_FATAL + */ + + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -92,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); @@ -100,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); @@ -108,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); @@ -119,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); @@ -127,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); @@ -139,14 +153,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); + printk(BIOS_DEBUG, "AGESA_STATUS: %x \n", val); else printk(BIOS_DEBUG, "passed.\n");

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Patch set updated for coreboot: d0f7cf7 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444 -gerrit commit d0f7cf78e55be565638dd870042d13646b6e23ab Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Apr 1 16:02:08 2014 -0500 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/mainboard/google/parrot/acpi/ec.asl | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..a042d75 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -273,7 +273,7 @@ Device (EC0) Store (ADPT, \PWRS) // Initialize LID switch state - Store (GP15, \LIDS) + Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS) // Force a read of CPU temperature Store (CTML, Local0) diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 522a0b9..a0ee9d5 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -21,5 +21,8 @@ #include "../ec.h" #define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI +/* GP15 is defined in the southbridge's ASL */ +#define EC_ACPI_LID_SWITCH_OBJECT GP15 + /* ACPI code for EC functions */ #include "../../../../ec/compal/ene932/acpi/ec.asl"

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Patch set updated for coreboot: 08a1c5d hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit 08a1c5d672a9b980b425f120d2534b6afacc349a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 14 ++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..e0d92fa --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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Patch set updated for coreboot: 18f70ae hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5463 -gerrit commit 18f70aef719ff1dc2bdc7a870ea9c472c289249c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:02:28 2014 -0500 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 0ddb038..5c8fc67 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -47,6 +47,17 @@ USBS, 1, } + /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ + OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) + Field (GPIO, ByteAcc, NoLock, Preserve) { + Offset (0x39), + , 6, + GP57, 1, /* out: WLAN control (rf-kill) */ + Offset (0x76), + , 7, + GE22, 1, /* General event 22 - connected to lid switch */ + } + /* * Used by EC code on certain events *

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coreboot-gerrit April 2014