coreboot-gerrit April 2014

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Patch set updated for coreboot: db5f70c hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5462 -gerrit commit db5f70c446c5010ab157753815cb9c614244a83a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 18:51:33 2014 -0500 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 108 ++---------------------- 1 file changed, 6 insertions(+), 102 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3a80e01..2b47baa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -368,72 +368,14 @@ GPIO_CONTROL parmer_gpio[] = { */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -447,44 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);

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Patch set updated for coreboot: 9d5f0a8 hp/pavilion_m6_1035dx: Add ACPI support for lid switch
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5464 -gerrit commit 9d5f0a879b56602bae0e3078467145b530e39f9d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:26:56 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for lid switch This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 5c8fc67..47d7872 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -71,3 +71,15 @@ Store("Received PNOT call (probably from EC)", Debug) /* TODO: Implement this */ } + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (GE22, \LIDS) + Return (\LIDS) + } + } +}

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New patch to review for coreboot: d61b1f7 hp/pavilion_m6_1035dx: Add ACPI support for lid switch
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5464 -gerrit commit d61b1f73b5f23a58414bb5736671bb37ef537182 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:26:56 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for lid switch This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 5c8fc67..47d7872 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -71,3 +71,15 @@ Store("Received PNOT call (probably from EC)", Debug) /* TODO: Implement this */ } + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (GE22, \LIDS) + Return (\LIDS) + } + } +}

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New patch to review for coreboot: b92476f hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5463 -gerrit commit b92476f1d610226ab87ed79f921564f806400b81 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:02:28 2014 -0500 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 0ddb038..5c8fc67 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -47,6 +47,17 @@ USBS, 1, } + /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ + OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) + Field (GPIO, ByteAcc, NoLock, Preserve) { + Offset (0x39), + , 6, + GP57, 1, /* out: WLAN control (rf-kill) */ + Offset (0x76), + , 7, + GE22, 1, /* General event 22 - connected to lid switch */ + } + /* * Used by EC code on certain events *

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New patch to review for coreboot: 66eb4c8 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5462 -gerrit commit 66eb4c8227160e4edbe383e53844748f32589f6d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 18:51:33 2014 -0500 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 108 ++---------------------- 1 file changed, 6 insertions(+), 102 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3a80e01..2b47baa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -368,72 +368,14 @@ GPIO_CONTROL parmer_gpio[] = { */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -447,44 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);

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Patch set updated for coreboot: a27bb0e ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444 -gerrit commit a27bb0e085f77f822b76378b5c4489e2e51e5778 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Apr 1 16:02:08 2014 -0500 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/mainboard/google/parrot/acpi/ec.asl | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..a042d75 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -273,7 +273,7 @@ Device (EC0) Store (ADPT, \PWRS) // Initialize LID switch state - Store (GP15, \LIDS) + Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS) // Force a read of CPU temperature Store (CTML, Local0) diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 522a0b9..a0ee9d5 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -21,5 +21,8 @@ #include "../ec.h" #define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI +/* GP15 is defined in the southbridge's ASL */ +#define EC_ACPI_LID_SWITCH_OBJECT GP15 + /* ACPI code for EC functions */ #include "../../../../ec/compal/ene932/acpi/ec.asl"

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Patch set updated for coreboot: a520bd3 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 06 Apr '14

06 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit a520bd37a050d9e8e15d1dfa52d6c21416eebffa Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 14 ++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..e0d92fa --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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Patch set updated for coreboot: 5ebddfa payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4
by Idwer Vollering 05 Apr '14

05 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit 5ebddfa759e16be4021450eb8f7633b1aa0411ba Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4 Successfully tested on the Asus M2V-MX SE. Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 5 +++- src/Kconfig | 55 ++++++++++++++++++++++++++++++++-- src/arch/x86/Makefile.inc | 2 +- 3 files changed, 58 insertions(+), 4 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..670f977 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=$(call strip_quotes,$(CONFIG_SEABIOS_STABLE)) unexport KCONFIG_AUTOCONFIG @@ -27,6 +27,9 @@ config: checkout echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config +ifeq ($(SEABIOS_STABLE_1_7_4),y) + echo "CONFIG_DEBUG_COREBOOT=y" >> $(OUT)/seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config diff --git a/src/Kconfig b/src/Kconfig index fe7dc9b..7182ec1 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -599,13 +599,54 @@ config PAYLOAD_TIANOCORE endchoice +#config SEABIOS_STABLE_1_7_2 +# bool +#config SEABIOS_STABLE_1_7_2_1 +# bool +#config SEABIOS_STABLE_1_7_2_2 +# bool +#config SEABIOS_STABLE_1_7_3 +# bool +#config SEABIOS_STABLE_1_7_3_1 +# bool +#config SEABIOS_STABLE_1_7_3_2 +# bool +#config SEABIOS_STABLE_1_7_4 +# bool + choice prompt "SeaBIOS version" - default SEABIOS_STABLE +# default COREBOOT_SEABIOS_STABLE_1_7_2 if SEABIOS_STABLE_1_7_2 +# default COREBOOT_SEABIOS_STABLE_1_7_2_1 if SEABIOS_STABLE_1_7_2_1 +# default COREBOOT_SEABIOS_STABLE_1_7_2_2 if SEABIOS_STABLE_1_7_2_2 +# default COREBOOT_SEABIOS_STABLE_1_7_3 if SEABIOS_STABLE_1_7_3 +# default COREBOOT_SEABIOS_STABLE_1_7_3_1 if SEABIOS_STABLE_1_7_3_1 +# default COREBOOT_SEABIOS_STABLE_1_7_3_2 if SEABIOS_STABLE_1_7_3_2 +# default COREBOOT_SEABIOS_STABLE_1_7_4 if SEABIOS_STABLE_1_7_4 depends on PAYLOAD_SEABIOS -config SEABIOS_STABLE +config SEABIOS_STABLE_1_7_2 +#config COREBOOT_SEABIOS_STABLE_1_7_2 + bool "1.7.2" +config SEABIOS_STABLE_1_7_2_1 +#config COREBOOT_SEABIOS_STABLE_1_7_2_1 bool "1.7.2.1" +config SEABIOS_STABLE_1_7_2_2 +#config COREBOOT_SEABIOS_STABLE_1_7_2_2 + bool "1.7.2.2" +config SEABIOS_STABLE_1_7_3 +#config COREBOOT_SEABIOS_STABLE_1_7_3 + bool "1.7.3" +config SEABIOS_STABLE_1_7_3_1 +#config COREBOOT_SEABIOS_STABLE_1_7_3_1 + bool "1.7.3.1" +config SEABIOS_STABLE_1_7_3_2 +#config COREBOOT_SEABIOS_STABLE_1_7_3_2 + bool "1.7.3.2" +config SEABIOS_STABLE_1_7_4 +#config COREBOOT_SEABIOS_STABLE_1_7_4 + bool "1.7.4" + help Stable SeaBIOS version config SEABIOS_MASTER @@ -614,6 +655,16 @@ config SEABIOS_MASTER Newest SeaBIOS version endchoice +config SEABIOS_STABLE + string + default "4bd8aebf3534e10d9aa21e820903f2cf9120708c" if SEABIOS_STABLE_1_7_2 + default "88cb66ea542906ffff8a80ef397b9e3adbb33116" if SEABIOS_STABLE_1_7_2_1 + default "d4f7d90f47462b4e8836899adc5060fbde5253e9" if SEABIOS_STABLE_1_7_2_2 + default "c02c219cd79299a0a153ecf862f0e301a057f2cb" if SEABIOS_STABLE_1_7_3 + default "7d9cbe613694924921ed1a6f8947d711c5832eee" if SEABIOS_STABLE_1_7_3_1 + default "ece025f5980bae88fa677bc9c0d24d2e580e205d" if SEABIOS_STABLE_1_7_3_2 + default "96917a8ed761f017fc8c72ba3b9181fbac03ac59" if SEABIOS_STABLE_1_7_4 + config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS default 0 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3b17ce3..4435703 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -467,7 +467,7 @@ seabios: OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ - CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_STABLE=$(call strip_quotes,$(CONFIG_SEABIOS_STABLE)) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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Patch set updated for coreboot: b77a3b2 SeaBIOS: have coreboot pass the choice to run optionroms in parallel
by Idwer Vollering 05 Apr '14

05 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5443 -gerrit commit b77a3b2c44d373e0a1610da03ec2eb12fba30b60 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Apr 1 22:47:33 2014 +0000 SeaBIOS: have coreboot pass the choice to run optionroms in parallel Introduce the tunable CONFIG_SEABIOS_THREAD_OPTIONROMS. Change-Id: Ifd4d9fca7316eb739ff184e54bdc1cdb0262f0c6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 11 +++++++++++ src/arch/x86/Makefile.inc | 1 + 3 files changed, 16 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 23b064c..e8bcaec 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -21,12 +21,16 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" $(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out/ echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + echo "CONFIG_THREAD_OPTIONROMS=y" >> $(OUT)/seabios/.config +endif echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_COREBOOT=y" >> $(OUT)/seabios/.config # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config diff --git a/src/Kconfig b/src/Kconfig index 291b166..7fbeb0f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -636,6 +636,17 @@ config SEABIOS_PS2_TIMEOUT after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up. +config SEABIOS_THREAD_OPTIONROMS + prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS + default n + bool + help + Allow hardware init to run in parallel with optionrom execution. + + This can reduce boot time, but can cause some timing + variations during option ROM code execution. It is not + known if all option ROMs will behave properly with this option. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 80e731f..3bf3326 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -448,6 +448,7 @@ seabios: AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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Patch set updated for coreboot: 583ecde jetway/nf81-t56n-lf: Sanitize #includes
by Edward O'Callaghan 05 Apr '14

05 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5414 -gerrit commit 583ecdebec749cc6e052371f63e845c571adc465 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 17:54:26 2014 +1100 jetway/nf81-t56n-lf: Sanitize #includes Following the same reasoning as commit 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this board support. Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 7 ++-- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 7 +--- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 6 +-- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 22 ++++------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 4 +- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 44 +++++++++------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 12 +++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 5 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 15 ++++---- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 35 +++++++++-------- 12 files changed, 82 insertions(+), 97 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 700da08..1d2aef0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -18,11 +18,12 @@ */ #include "agesawrapper.h" -#include "amdlib.h" #include "BiosCallOuts.h" -#include "heapManager.h" -#include "SB800.h" + +#include <Lib/amdlib.h> #include <northbridge/amd/agesa/family14/dimmSpd.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <vendorcode/amd/cimx/sb800/SB800.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cd69f1..d7413cd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include "BiosCallOuts.h" +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> + #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index ec8a6e3..47ed1a5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -20,10 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 43ee9c9..e7772aa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam14.h> +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 0572335..e6633f3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -22,25 +22,19 @@ *----------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE UNASSIGNED_FILE_FILECODE diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index ba47c53..6544d25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -26,8 +26,8 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c6383a2..c6594d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -33,7 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "Filecode.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +/* AGESA nonesense: the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -224,8 +238,6 @@ * Uncomment and specify the value for the configuration options * needed by the system. */ -#include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = @@ -244,20 +256,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - /***************************************************************************** * Define the RELEASE VERSION string * @@ -314,8 +312,9 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. -#include "PlatformInstall.h" +/* AGESA nonsense: this header depends on the definitions above */ +/* Instantiate all solution relevant data. */ +#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -390,11 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" //DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = @@ -454,5 +448,3 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL // /* platform code to read an SPD... */ // return Status; //} - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 258d895..1491f29 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b9577cf..b77c375 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -18,12 +18,11 @@ */ +#include <arch/pirq_routing.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/amd/amdfam14.h> #include <string.h> #include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdfam14.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 44f9c48..d5f2d03 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -17,18 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h" void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 6b8aaa6..d7fe6a0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -18,14 +18,15 @@ */ -#include <console/console.h> +#include <arch/io.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> extern u8 bus_sb800[6]; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 1214921..846d5c7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -18,30 +18,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> + +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> + #include <console/loglevel.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" +#include <cpu/x86/cache.h> +#include <cpu/amd/mtrr.h> +#include <sb_cimx.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include "superio/fintek/f71869ad/f71869ad.h" -#include "cpu/x86/lapic.h" + +/* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

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coreboot-gerrit April 2014