coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: dafc2ca x86/Makefile: Allow addition of link libraries for rom/ramstage
by gerrit＠coreboot.org 04 Apr '14

04 Apr '14

the following patch was just integrated into master: commit dafc2ca40dbd9223dfa16cf351f49d1d19b085ad Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:01:11 2014 -0500 x86/Makefile: Allow addition of link libraries for rom/ramstage This is useful, for example, when using stage-independent code, as it allows us to compile that code only once. It's also useful for vendor code which needs wonky compiler definitions and include paths which we'd rather not include in the other files. Subsequent patches will make use of this when lib-izing AGESA. Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5425 for details. -gerrit

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Patch set updated for coreboot: 0408e2e vendorcode/amd/agesa/fam15tn: Build as a static library
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5430 -gerrit commit 0408e2ed19792ac61c436bcb66a898bf2fc908c5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:15:18 2014 -0500 vendorcode/amd/agesa/fam15tn: Build as a static library Up until now, we were building AGESA by specifying each AGESA source file and adding it to the list of romstage and ramstage source files. As a result, we were compiling each AGESA source twice, despite the fact that it does not depend on the stage we're in. Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. We still keep the practice of specifying every single AGESA directory as an include dir and adding the AGESA CFLAGS to our global CFLAGS; this is needed due to the way AGESA builds. Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 436 --------------------------- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 437 ++++++++++++++++++++++++++++ 2 files changed, 437 insertions(+), 436 deletions(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..a5a7071 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -20,442 +20,6 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn - -agesa_lib_src = -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c -agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c -agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c - -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c - - -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..00ace78 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -93,3 +93,440 @@ export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### + +classes-y += libagesa + +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Lib/amdlib.c +libagesa-y += Lib/helper.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnC6State.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnCpb.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnIoCstate.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMsrTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPciTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnUtilities.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c +libagesa-y += Proc/CPU/Family/0x15/cpuCommonF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15BrandId.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15CacheDefaults.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Dmi.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15MmioMap.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15MsrTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PciTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PowerCheck.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +libagesa-y += Proc/CPU/Feature/PreserveMailbox.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/CPU/Feature/cpuCoreLeveling.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/CPU/Feature/cpuHtc.c +libagesa-y += Proc/CPU/Feature/cpuHwC1e.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/CPU/Feature/cpuPsi.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cahaltasm.S +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/CPU/cpuBrandId.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/CPU/cpuInitEarlyTable.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/GNB/Common/GnbLibFeatures.c +libagesa-y += Proc/GNB/GnbInitAtEarly.c +libagesa-y += Proc/GNB/GnbInitAtEnv.c +libagesa-y += Proc/GNB/GnbInitAtLate.c +libagesa-y += Proc/GNB/GnbInitAtMid.c +libagesa-y += Proc/GNB/GnbInitAtPost.c +libagesa-y += Proc/GNB/GnbInitAtReset.c +libagesa-y += Proc/GNB/GnbInitAtS3Save.c +libagesa-y += Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieLibTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +libagesa-y += Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c +libagesa-y += Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +libagesa-y += Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c +libagesa-y += Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +libagesa-y += Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +libagesa-y += Proc/GNB/Modules/GnbSview/GnbSview.c +libagesa-y += Proc/GNB/Modules/GnbTable/GnbTable.c +libagesa-y += Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c +libagesa-y += Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/IDS/Debug/IdsDebug.c +libagesa-y += Proc/IDS/Debug/IdsDebugPrint.c +libagesa-y += Proc/IDS/Debug/IdsDpSerial.c +libagesa-y += Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c +libagesa-y += Proc/IDS/Library/IdsLib.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Main/TN/mmflowtn.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Main/mu.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/NB/TN/mndcttn.c +libagesa-y += Proc/Mem/NB/TN/mnflowtn.c +libagesa-y += Proc/Mem/NB/TN/mnidendimmtn.c +libagesa-y += Proc/Mem/NB/TN/mnmcttn.c +libagesa-y += Proc/Mem/NB/TN/mnottn.c +libagesa-y += Proc/Mem/NB/TN/mnphytn.c +libagesa-y += Proc/Mem/NB/TN/mnregtn.c +libagesa-y += Proc/Mem/NB/TN/mns3tn.c +libagesa-y += Proc/Mem/NB/TN/mntn.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/Mem/Ps/TN/FM2/mpUtnfm2.c +libagesa-y += Proc/Mem/Ps/TN/FP2/mpStnfp2.c +libagesa-y += Proc/Mem/Ps/TN/FS1/mpStnfs1.c +libagesa-y += Proc/Mem/Ps/TN/mpStn3.c +libagesa-y += Proc/Mem/Ps/TN/mpUtn3.c +libagesa-y += Proc/Mem/Ps/TN/mptn3.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Ps/mpmaxfreq.c +libagesa-y += Proc/Mem/Ps/mpmr0.c +libagesa-y += Proc/Mem/Ps/mpodtpat.c +libagesa-y += Proc/Mem/Ps/mprtt.c +libagesa-y += Proc/Mem/Ps/mpsao.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/Mem/Tech/mtthrcSeedTrain.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Tech/mttsrc.c +libagesa-y += Proc/Fch/Azalia/AzaliaEnv.c +libagesa-y += Proc/Fch/Azalia/AzaliaLate.c +libagesa-y += Proc/Fch/Azalia/AzaliaMid.c +libagesa-y += Proc/Fch/Azalia/AzaliaReset.c +libagesa-y += Proc/Fch/Common/AcpiLib.c +libagesa-y += Proc/Fch/Common/FchCommon.c +libagesa-y += Proc/Fch/Common/FchLib.c +libagesa-y += Proc/Fch/Common/FchPeLib.c +libagesa-y += Proc/Fch/Common/MemLib.c +libagesa-y += Proc/Fch/Common/PciLib.c +libagesa-y += Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c +libagesa-y += Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c +libagesa-y += Proc/Fch/Gec/GecEnv.c +libagesa-y += Proc/Fch/Gec/GecLate.c +libagesa-y += Proc/Fch/Gec/GecMid.c +libagesa-y += Proc/Fch/Gec/GecReset.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiEnv.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiLate.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiMid.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiReset.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c +libagesa-y += Proc/Fch/Hwm/HwmEnv.c +libagesa-y += Proc/Fch/Hwm/HwmLate.c +libagesa-y += Proc/Fch/Hwm/HwmMid.c +libagesa-y += Proc/Fch/Hwm/HwmReset.c +libagesa-y += Proc/Fch/Ide/IdeEnv.c +libagesa-y += Proc/Fch/Ide/IdeLate.c +libagesa-y += Proc/Fch/Ide/IdeMid.c +libagesa-y += Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c +libagesa-y += Proc/Fch/Imc/FchEcEnv.c +libagesa-y += Proc/Fch/Imc/FchEcLate.c +libagesa-y += Proc/Fch/Imc/FchEcMid.c +libagesa-y += Proc/Fch/Imc/FchEcReset.c +libagesa-y += Proc/Fch/Imc/ImcEnv.c +libagesa-y += Proc/Fch/Imc/ImcLate.c +libagesa-y += Proc/Fch/Imc/ImcLib.c +libagesa-y += Proc/Fch/Imc/ImcMid.c +libagesa-y += Proc/Fch/Imc/ImcReset.c +libagesa-y += Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c +libagesa-y += Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c +libagesa-y += Proc/Fch/Interface/FchInitEnv.c +libagesa-y += Proc/Fch/Interface/FchInitLate.c +libagesa-y += Proc/Fch/Interface/FchInitMid.c +libagesa-y += Proc/Fch/Interface/FchInitReset.c +libagesa-y += Proc/Fch/Interface/FchInitS3.c +libagesa-y += Proc/Fch/Interface/FchTaskLauncher.c +libagesa-y += Proc/Fch/Interface/InitEnvDef.c +libagesa-y += Proc/Fch/Interface/InitResetDef.c +libagesa-y += Proc/Fch/Ir/IrEnv.c +libagesa-y += Proc/Fch/Ir/IrLate.c +libagesa-y += Proc/Fch/Ir/IrMid.c +libagesa-y += Proc/Fch/Pcib/PcibEnv.c +libagesa-y += Proc/Fch/Pcib/PcibLate.c +libagesa-y += Proc/Fch/Pcib/PcibMid.c +libagesa-y += Proc/Fch/Pcib/PcibReset.c +libagesa-y += Proc/Fch/Pcie/AbEnv.c +libagesa-y += Proc/Fch/Pcie/AbLate.c +libagesa-y += Proc/Fch/Pcie/AbMid.c +libagesa-y += Proc/Fch/Pcie/AbReset.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c +libagesa-y += Proc/Fch/Pcie/GppEnv.c +libagesa-y += Proc/Fch/Pcie/GppHp.c +libagesa-y += Proc/Fch/Pcie/GppLate.c +libagesa-y += Proc/Fch/Pcie/GppLib.c +libagesa-y += Proc/Fch/Pcie/GppMid.c +libagesa-y += Proc/Fch/Pcie/GppPortInit.c +libagesa-y += Proc/Fch/Pcie/GppReset.c +libagesa-y += Proc/Fch/Pcie/PcieEnv.c +libagesa-y += Proc/Fch/Pcie/PcieLate.c +libagesa-y += Proc/Fch/Pcie/PcieMid.c +libagesa-y += Proc/Fch/Pcie/PcieReset.c +libagesa-y += Proc/Fch/Sata/AhciEnv.c +libagesa-y += Proc/Fch/Sata/AhciLate.c +libagesa-y += Proc/Fch/Sata/AhciLib.c +libagesa-y += Proc/Fch/Sata/AhciMid.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c +libagesa-y += Proc/Fch/Sata/Ide2AhciEnv.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLate.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLib.c +libagesa-y += Proc/Fch/Sata/Ide2AhciMid.c +libagesa-y += Proc/Fch/Sata/RaidEnv.c +libagesa-y += Proc/Fch/Sata/RaidLate.c +libagesa-y += Proc/Fch/Sata/RaidLib.c +libagesa-y += Proc/Fch/Sata/RaidMid.c +libagesa-y += Proc/Fch/Sata/SataEnv.c +libagesa-y += Proc/Fch/Sata/SataEnvLib.c +libagesa-y += Proc/Fch/Sata/SataIdeEnv.c +libagesa-y += Proc/Fch/Sata/SataIdeLate.c +libagesa-y += Proc/Fch/Sata/SataIdeLib.c +libagesa-y += Proc/Fch/Sata/SataIdeMid.c +libagesa-y += Proc/Fch/Sata/SataLate.c +libagesa-y += Proc/Fch/Sata/SataLib.c +libagesa-y += Proc/Fch/Sata/SataMid.c +libagesa-y += Proc/Fch/Sata/SataReset.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c +libagesa-y += Proc/Fch/Sd/SdEnv.c +libagesa-y += Proc/Fch/Sd/SdLate.c +libagesa-y += Proc/Fch/Sd/SdMid.c +libagesa-y += Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c +libagesa-y += Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +libagesa-y += Proc/Fch/Spi/LpcEnv.c +libagesa-y += Proc/Fch/Spi/LpcLate.c +libagesa-y += Proc/Fch/Spi/LpcMid.c +libagesa-y += Proc/Fch/Spi/LpcReset.c +libagesa-y += Proc/Fch/Spi/SpiEnv.c +libagesa-y += Proc/Fch/Spi/SpiLate.c +libagesa-y += Proc/Fch/Spi/SpiMid.c +libagesa-y += Proc/Fch/Spi/SpiReset.c +libagesa-y += Proc/Fch/Usb/EhciEnv.c +libagesa-y += Proc/Fch/Usb/EhciLate.c +libagesa-y += Proc/Fch/Usb/EhciMid.c +libagesa-y += Proc/Fch/Usb/EhciReset.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c +libagesa-y += Proc/Fch/Usb/OhciEnv.c +libagesa-y += Proc/Fch/Usb/OhciLate.c +libagesa-y += Proc/Fch/Usb/OhciMid.c +libagesa-y += Proc/Fch/Usb/OhciReset.c +libagesa-y += Proc/Fch/Usb/UsbEnv.c +libagesa-y += Proc/Fch/Usb/UsbLate.c +libagesa-y += Proc/Fch/Usb/UsbMid.c +libagesa-y += Proc/Fch/Usb/UsbReset.c +libagesa-y += Proc/Fch/Usb/XhciEnv.c +libagesa-y += Proc/Fch/Usb/XhciLate.c +libagesa-y += Proc/Fch/Usb/XhciMid.c +libagesa-y += Proc/Fch/Usb/XhciReset.c + +$(obj)/libagesa.fam15tn.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/libagesa.fam15tn.a +ramstage-libs += $(obj)/libagesa.fam15tn.a

1 0

Patch set updated for coreboot: dafc2ca x86/Makefile: Allow addition of link libraries for rom/ramstage
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5425 -gerrit commit dafc2ca40dbd9223dfa16cf351f49d1d19b085ad Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:01:11 2014 -0500 x86/Makefile: Allow addition of link libraries for rom/ramstage This is useful, for example, when using stage-independent code, as it allows us to compile that code only once. It's also useful for vendor code which needs wonky compiler definitions and include paths which we'd rather not include in the other files. Subsequent patches will make use of this when lib-izing AGESA. Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index acb4e98..3b17ce3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -207,6 +207,8 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ################################################################################ # Build the coreboot_ram (stage 2) +ramstage-libs ?= + ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) $(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE))) @@ -227,12 +229,12 @@ endif endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ @@ -404,24 +406,26 @@ endif ################################################################################ # Build the romstage -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld +romstage-libs ?= + +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ else true; fi -$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld +$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions

1 0

Patch set updated for coreboot: aed6ffd jetway/nf81-t56n-lf: Sanitize #includes
by Edward O'Callaghan 04 Apr '14

04 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5414 -gerrit commit aed6ffd91db2709f15285375624f3689f07789df Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 17:54:26 2014 +1100 jetway/nf81-t56n-lf: Sanitize #includes Following the same reasoning as commit 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this northbridge code. Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 6 +-- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 7 +--- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 6 +-- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 22 ++++------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 4 +- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 44 +++++++++------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 12 +++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 5 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 15 ++++---- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 35 +++++++++-------- 12 files changed, 81 insertions(+), 97 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 700da08..9174183 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -18,10 +18,10 @@ */ #include "agesawrapper.h" -#include "amdlib.h" +#include <Lib/amdlib.h> #include "BiosCallOuts.h" -#include "heapManager.h" -#include "SB800.h" +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <vendorcode/amd/cimx/sb800/SB800.h> #include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cd69f1..d7413cd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include "BiosCallOuts.h" +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> + #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index ec8a6e3..47ed1a5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -20,10 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 43ee9c9..e7772aa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam14.h> +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 0572335..e6633f3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -22,25 +22,19 @@ *----------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE UNASSIGNED_FILE_FILECODE diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index ba47c53..6544d25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -26,8 +26,8 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c6383a2..c6594d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -33,7 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "Filecode.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +/* AGESA nonesense: the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -224,8 +238,6 @@ * Uncomment and specify the value for the configuration options * needed by the system. */ -#include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = @@ -244,20 +256,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - /***************************************************************************** * Define the RELEASE VERSION string * @@ -314,8 +312,9 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. -#include "PlatformInstall.h" +/* AGESA nonsense: this header depends on the definitions above */ +/* Instantiate all solution relevant data. */ +#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -390,11 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" //DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = @@ -454,5 +448,3 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL // /* platform code to read an SPD... */ // return Status; //} - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 258d895..1491f29 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b9577cf..b77c375 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -18,12 +18,11 @@ */ +#include <arch/pirq_routing.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/amd/amdfam14.h> #include <string.h> #include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdfam14.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 44f9c48..d5f2d03 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -17,18 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h" void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 6b8aaa6..d7fe6a0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -18,14 +18,15 @@ */ -#include <console/console.h> +#include <arch/io.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> extern u8 bus_sb800[6]; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 1214921..846d5c7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -18,30 +18,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> + +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> + #include <console/loglevel.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" +#include <cpu/x86/cache.h> +#include <cpu/amd/mtrr.h> +#include <sb_cimx.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include "superio/fintek/f71869ad/f71869ad.h" -#include "cpu/x86/lapic.h" + +/* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

1 0

Patch set updated for coreboot: 8a024ea cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5426 -gerrit commit 8a024ea4bd89580df435103addff2237eb544cbd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 18:06:57 2014 -0500 cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT Following the same reasoning as in commit * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes include AGESA files with a path relative to AGESA_ROOT. We cannot with more than one generation of AGESA, hence the path being relative to AGESA_ROOT. Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 7b1157d..d51203e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" +#include <AGESA.h> +#include <Lib/amdlib.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h>

1 0

Patch set updated for coreboot: 4bf70b7 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5424 -gerrit commit 4bf70b747a1a0702d239b1073b0c6cfca7b9c384 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 16:52:46 2014 -0500 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h | 2 +- .../agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionFamily15hInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h | 8 ++++---- src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h | 4 ++-- .../amd/agesa/f15tn/Include/OptionIoCstateInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h | 10 +++++----- .../amd/agesa/f15tn/Include/OptionMemoryRecovery.h | 6 +++--- .../amd/agesa/f15tn/Include/OptionMmioMapInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h | 2 +- .../amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionS3ScriptInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h | 12 ++++++------ .../f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h | 6 +++--- src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h | 6 +++--- 29 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h index e88d35b..368104c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_APM_INSTALL_H_ #define _OPTION_APM_INSTALL_H_ -#include "cpuApm.h" +#include <Proc/CPU/Feature/cpuApm.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h index 088d303..b6186c6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h @@ -44,7 +44,7 @@ #ifndef _OPTION_C6_STATE_INSTALL_H_ #define _OPTION_C6_STATE_INSTALL_H_ -#include "cpuC6State.h" +#include <Proc/CPU/Feature/cpuC6State.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h index b2fa7d6..308dc73 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_CPB_INSTALL_H_ #define _OPTION_CPB_INSTALL_H_ -#include "cpuCpb.h" +#include <Proc/CPU/Feature/cpuCpb.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h index f00ee23..8b5db5a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ #define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ -#include "cpuPostInit.h" +#include "Proc/CPU/cpuPostInit.h" /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h index 73e5041..fb1b54d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_DMI_INSTALL_H_ #define _OPTION_DMI_INSTALL_H_ -#include "cpuLateInit.h" +#include <Proc/CPU/cpuLateInit.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h index d1e5c5b..f0d9194 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h @@ -43,7 +43,7 @@ #ifndef _OPTION_FAMILY_15H_INSTALL_H_ #define _OPTION_FAMILY_15H_INSTALL_H_ -#include "cpuFamilyTranslation.h" +#include <Proc/CPU/cpuFamilyTranslation.h> /* * Pull in family specific services based on entry point diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h index bf4c208..4a8237a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h @@ -42,7 +42,7 @@ #ifndef _OPTION_FCH_INSTALL_H_ #define _OPTION_FCH_INSTALL_H_ -#include "AmdFch.h" +#include <Proc/Common/AmdFch.h> #ifndef FCH_SUPPORT #define FCH_SUPPORT FALSE diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h index 022eee3..f6fc162 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_GNB_INSTALL_H_ #define _OPTION_GNB_INSTALL_H_ -#include "S3SaveState.h" +#include <Proc/Common/S3SaveState.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. * Check to validate the definition @@ -82,13 +82,13 @@ // Service installation //--------------------------------------------------------------------------------------------------- - #include "Gnb.h" - #include "GnbPcie.h" - #include "GnbGfx.h" + #include <Proc/GNB/Common/Gnb.h> + #include <Proc/GNB/Common/GnbPcie.h> + #include <Proc/GNB/Common/GnbGfx.h> #define SERVICES_POINTER NULL #if (GNB_TYPE_TN == TRUE) - #include "GnbInitTNInstall.h" + #include <Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h> #endif GNB_SERVICE *ServiceTable = SERVICES_POINTER; diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h index d6055bc..5069412 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h @@ -45,10 +45,10 @@ #define _OPTION_HT_INSTALL_H_ #include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htTopologies.h" +#include <Proc/HT/htFeat.h> +#include <Proc/HT/htInterface.h> +#include <Proc/HT/htNb.h> +#include <Proc/HT/htTopologies.h> /* * Advanced Option only, hardware socket naming is the preferred method. */ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h index 0b6f4f0..671b0fb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_HTC_INSTALL_H_ #define _OPTION_HTC_INSTALL_H_ -#include "cpuHtc.h" +#include <Proc/CPU/Feature/cpuHtc.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h index 0f85c71..374ceb4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_HW_C1E_INSTALL_H_ #define _OPTION_HW_C1E_INSTALL_H_ -#include "cpuHwC1e.h" +#include <Proc/CPU/Feature/cpuHwC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h index 83c28d2..a60667f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h @@ -43,8 +43,8 @@ #define _OPTION_IDS_INSTALL_H_ #include "Ids.h" #include "IdsHt.h" -#include "IdsLib.h" -#include "IdsDebugPrint.h" +#include <Proc/IDS/IdsLib.h> +#include <Proc/IDS/Debug/IdsDebugPrint.h> #ifdef __IDS_EXTENDED__ #include OPTION_IDS_EXT_INSTALL_FILE #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h index b94b043..b83ee6b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_IO_CSTATE_INSTALL_H_ #define _OPTION_IO_CSTATE_INSTALL_H_ -#include "cpuIoCstate.h" +#include <Proc/CPU/Feature/cpuIoCstate.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h index 981e7c9..5d188e2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_L3_FEATURES_INSTALL_H_ #define _OPTION_L3_FEATURES_INSTALL_H_ -#include "cpuL3Features.h" +#include <Proc/CPU/Feature/cpuL3Features.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h index 017c981..2494ba9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h @@ -45,11 +45,11 @@ #define _OPTION_MEMORY_H_ /* Memory Includes */ -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mp.h" +#include <Proc/Mem/mm.h> +#include <Proc/Mem/mn.h> +#include <Proc/Mem/mt.h> +#include <Proc/Mem/ma.h> +#include <Proc/Mem/mp.h> /*---------------------------------------------------------------------------------------- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h index 713e73d..710d218 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h @@ -44,9 +44,9 @@ #ifndef _OPTION_MEMORY_RECOVERY_H_ #define _OPTION_MEMORY_RECOVERY_H_ -#include "mm.h" -#include "mn.h" -#include "mt.h" +#include <Proc/Mem/mm.h> +#include <Proc/Mem/mn.h> +#include <Proc/Mem/mt.h> typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR ( IN OUT MEM_NB_BLOCK *NBPtr, diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h index f43ff86..5ba255d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_MMIO_MAP_INSTALL_H_ #define _OPTION_MMIO_MAP_INSTALL_H_ -#include "mmioMapManager.h" +#include <Proc/CPU/mmioMapManager.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h index 986690b..6d0aeef 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ #define _OPTION_MSG_BASED_C1E_INSTALL_H_ -#include "cpuMsgBasedC1e.h" +#include <Proc/CPU/Feature/cpuMsgBasedC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h index d42175c..310dc54 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ #define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#include "PreserveMailbox.h" +#include <Proc/CPU/Feature/PreserveMailbox.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h index 83e4734..0053a49 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSI_INSTALL_H_ #define _OPTION_PSI_INSTALL_H_ -#include "cpuPsi.h" +#include <Proc/CPU/Feature/cpuPsi.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h index 1ffaf94..2b576b1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_H_ #define _OPTION_PSTATE_H_ -#include "cpuPstateTables.h" +#include <Proc/CPU/Feature/cpuPstateTables.h> /*---------------------------------------------------------------------------------------- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h index 6b7f7f7..5106ed2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_ #define _OPTION_PSTATE_HPC_MODE_INSTALL_H_ -#include "cpuPstateHpcMode.h" +#include <Proc/CPU/Feature/cpuPstateHpcMode.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h index 18f22ac..e80a69d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_INSTALL_H_ #define _OPTION_PSTATE_INSTALL_H_ -#include "cpuPstateTables.h" +#include <Proc/CPU/Feature/cpuPstateTables.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h index 5b62bdf..f470042 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_S3SCRIPT_INSTALL_H_ #define _OPTION_S3SCRIPT_INSTALL_H_ -#include "S3SaveState.h" +#include <Proc/Common/S3SaveState.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. * Check to validate the definition diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h index 34886ee..4fa53ce 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_SW_C1E_INSTALL_H_ #define _OPTION_SW_C1E_INSTALL_H_ -#include "cpuSwC1e.h" +#include <Proc/CPU/Feature/cpuSwC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index f3e7116..48fcb24 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -45,7 +45,7 @@ #ifndef _CPU_REGISTERS_H_ #define _CPU_REGISTERS_H_ -#include "cpuFamRegisters.h" +#include "Family/cpuFamRegisters.h" /* *-------------------------------------------------------------- * diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h index aeace64..55ff7c0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h @@ -106,12 +106,12 @@ #endif #include "Fch.h" -#include "amdlib.h" -#include "FchCommonCfg.h" -#include "AcpiLib.h" -#include "FchDef.h" -#include "FchBiosRamUsage.h" -#include "AmdFch.h" +#include <Lib/amdlib.h> +#include "Common/FchCommonCfg.h" +#include "Common/AcpiLib.h" +#include "Common/FchDef.h" +#include "Common/FchBiosRamUsage.h" +#include <Proc/Common/AmdFch.h> extern BUILD_OPT_CFG UserOptions; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h index 6055818..1be9d7c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -50,9 +50,9 @@ // Specify definition used by module services //----------------------------------------------------------------------- -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbFamServices.h" +#include <Proc/GNB/Common/GnbPcie.h> +#include <Proc/GNB/Common/GnbPcieFamServices.h> +#include <Proc/GNB/Common/GnbFamServices.h> //----------------------------------------------------------------------- // Export services diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h index 904e72d..a30dc37 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h @@ -43,9 +43,9 @@ #ifndef _IDS_LIB_H_ #define _IDS_LIB_H_ #include "OptionsIds.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Table.h" +#include <Proc/CPU/cpuRegisters.h> +#include <Proc/CPU/cpuApicUtilities.h> +#include <Proc/CPU/Table.h> ///Specific time stamp performance analysis which need ids control support #if IDSOPT_CONTROL_ENABLED == TRUE #define PERF_SPEC_TS_ANALYSE(StdHeader) IdsPerfSpecTsAnalyse(StdHeader)

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Patch set updated for coreboot: 5351fa4 northbridge/amd/agesa/family15tn: Sanitize #includes
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5422 -gerrit commit 5351fa44f1699548b440001df6ee599f7ac76384 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 17:19:50 2014 -0500 northbridge/amd/agesa/family15tn: Sanitize #includes NOTFORMERGE: Following the same reasoning as commit <HASH HERE> (pavilion) hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this northbridge code. Change-Id: I8e27ddb9cbd1c9e5c2f15626815875047de18a0b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/northbridge/amd/agesa/family15tn/chip.h | 2 ++ src/northbridge/amd/agesa/family15tn/dimmSpd.c | 12 +++----- src/northbridge/amd/agesa/family15tn/dimmSpd.h | 2 ++ .../amd/agesa/family15tn/fam15tn_callouts.c | 14 +++++---- .../amd/agesa/family15tn/fam15tn_callouts.h | 3 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 33 +++++++++++----------- 6 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h index 41571db..8a7ce9b 100644 --- a/src/northbridge/amd/agesa/family15tn/chip.h +++ b/src/northbridge/amd/agesa/family15tn/chip.h @@ -20,6 +20,8 @@ #ifndef _AGESA_FAM15TN_CHIP_H_ #define _AGESA_FAM15TN_CHIP_H_ +#include <stdint.h> + struct northbridge_amd_agesa_family15tn_config { u8 spdAddrLookup[2][2][4]; diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 5b8a9b5..38eee7f 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -17,16 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/pci_def.h> -#include <device/device.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "dimmSpd.h" #include "chip.h" +#include "dimmSpd.h" +#include <device/pci_def.h> +#include <device/device.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> #define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.h b/src/northbridge/amd/agesa/family15tn/dimmSpd.h index e50d53e..ac324cb 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.h +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.h @@ -25,6 +25,8 @@ #ifndef _DIMMSPD_H_ #define _DIMMSPD_H_ +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index cf84b39..f907e02 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -18,15 +18,17 @@ */ #include "agesawrapper.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionsIds.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" #include "dimmSpd.h" #include "fam15tn_callouts.h" + +#include <cbfs.h> #include <cbmem.h> +#include <vendorcode/amd/agesa/f15tn/Include/Ids.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h> + #define AGESA_RUNTIME_SIZE 4096 diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h index ff0cc44..7560230 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h @@ -20,8 +20,7 @@ #ifndef CALLOUTS_AMD_AGESA_FAM15TN_H #define CALLOUTS_AMD_AGESA_FAM15TN_H -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> #define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2b5549d..1848210 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -17,30 +17,29 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include "agesawrapper.h" +#include "northbridge.h" + #include <arch/io.h> -#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/amd/amdfam15.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> #include <device/device.h> +#include <device/hypertransport.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> +#include <lib.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <lib.h> -#include <cpu/cpu.h> -#include <cbmem.h> -#include <AGESA.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/mtrr.h> - -#include <Porting.h> -#include <Options.h> -#include <Topology.h> -#include <cpu/amd/amdfam15.h> -#include <cpuRegisters.h> -#include "agesawrapper.h" -#include "northbridge.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Include/Options.h> +#include <vendorcode/amd/agesa/f15tn/Include/Topology.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)

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Patch set updated for coreboot: 55d0059 southbridge/amd/agesa/hudson: Clean up AGESA #includes
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5423 -gerrit commit 55d0059d464327008eaf85d76580859389c8e41c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 17:07:26 2014 -0500 southbridge/amd/agesa/hudson: Clean up AGESA #includes Just like in commit * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Include AGESA headers specifying the path relative to AGESA_ROOT. The path is specified relative to AGESA_ROOT as opposed to src/ since this code may include headers from different AGESA families, depending on the board. Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/imc.c | 8 ++++---- src/southbridge/amd/agesa/hudson/resume.c | 4 ++-- src/southbridge/amd/agesa/hudson/spi.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index af9e865..d706292 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -22,10 +22,10 @@ #include <delay.h> #include "Porting.h" #include "AGESA.h" -#include "amdlib.h" -#include "Fch.h" -#include "FchCommonCfg.h" -#include "FchPlatform.h" +#include <Lib/amdlib.h> +#include <Proc/Fch/Fch.h> +#include <Proc/Fch/Common/FchCommonCfg.h> +#include <Proc/Fch/FchPlatform.h> void imc_reg_init(void) { diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 0d40d6c..ecf06a0 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "FchPlatform.h" -#include "Fch.h" +#include <Proc/Fch/FchPlatform.h> +#include <Proc/Fch/Fch.h> #include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index b89ea5d..a46bf08 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> #if defined (CONFIG_HUDSON_IMC_FWM) -#include "FchPlatform.h" +#include <Proc/Fch/FchPlatform.h> static int bus_claimed = 0; #endif

1 0

Patch set updated for coreboot: 0a9fa51 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit 0a9fa510c4a56739ef029243bfc5383c8e3d2248 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 14 ++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..e0d92fa --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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Patch set updated for coreboot: 4a94cba hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 04 Apr '14

04 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit 4a94cba2cbac43402727a73f02e0256f53a69a24 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 16 ++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 39 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..cf8747b --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> + + diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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coreboot-gerrit April 2014