coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: a1fb008 util/cbmem: handle larger than 1MiB mappings for console
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit a1fb008419278739520377b6d03bc60b6f5cce68 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 31 11:59:58 2014 -0500 util/cbmem: handle larger than 1MiB mappings for console In some cases the cbmem console can be larger than the default mapping size of 1MiB. Therefore, add the ability to do a mapping that is larger than the default mapping using map_memory_size(). The console printing code will unconditionally map the console based on the size it finds in the cbmem entry. Change-Id: I016420576b9523ce81195160ae86ad16952b761c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5440 for details. -gerrit

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Patch merged into coreboot/master: 3131502 superio/fintek/f71859: Avoid .c includes
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit 313150290c5b70162b9de5f9d767f6f1859143f0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 20:42:58 2014 +1100 superio/fintek/f71859: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5417 for details. -gerrit

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Patch merged into coreboot/master: 7016536 superio/fintek/f71889: Avoid .c includes
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit 70165365bc95dc2e12e5c9db15a6e3db7cb147dd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:14:14 2014 +1100 superio/fintek/f71889: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5437 for details. -gerrit

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Patch merged into coreboot/master: 01e8ec0 superio/fintek/f71872: Avoid .c includes
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit 01e8ec0edef0d92dd4d8a44b561cd0a27b10ce47 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:13:07 2014 +1100 superio/fintek/f71872: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5436 for details. -gerrit

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Patch merged into coreboot/master: c005e7e superio/fintek/f71863fg: Avoid .c includes
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit c005e7e76c270da4b4e4b7e39ac63e721bb262b5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:08:35 2014 +1100 superio/fintek/f71863fg: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I863c16634873224c17e43100271e9b91419724d0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5435 for details. -gerrit

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Patch merged into coreboot/master: 48471ec superio/fintek/f71805f: Avoid .c includes
by gerrit＠coreboot.org 02 Apr '14

02 Apr '14

the following patch was just integrated into master: commit 48471ece71ec7fcb5139743de231c38bdf250630 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:01:16 2014 +1100 superio/fintek/f71805f: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5434 for details. -gerrit

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New patch to review for coreboot: e29fb68 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 02 Apr '14

02 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit e29fb6808fa900fff28b797c44cffd34531d9348 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the hardware is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 16 ++++++++++++++++ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 3 files changed, 39 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..34bd876 --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 /* TODO: Unclear whether this is the correct SCI */ +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> + + diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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New patch to review for coreboot: 5e0f7ff ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
by Alexandru Gagniuc 02 Apr '14

02 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444 -gerrit commit 5e0f7ff06903e8d3fea8bacfaf1f630a816b68dd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Apr 1 16:02:08 2014 -0500 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/mainboard/google/parrot/acpi/ec.asl | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..a042d75 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -273,7 +273,7 @@ Device (EC0) Store (ADPT, \PWRS) // Initialize LID switch state - Store (GP15, \LIDS) + Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS) // Force a read of CPU temperature Store (CTML, Local0) diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 522a0b9..a0ee9d5 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -21,5 +21,8 @@ #include "../ec.h" #define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI +/* GP15 is defined in the southbridge's ASL */ +#define EC_ACPI_LID_SWITCH_OBJECT GP15 + /* ACPI code for EC functions */ #include "../../../../ec/compal/ene932/acpi/ec.asl"

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Patch set updated for coreboot: a1fb008 util/cbmem: handle larger than 1MiB mappings for console
by Aaron Durbin 01 Apr '14

01 Apr '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5440 -gerrit commit a1fb008419278739520377b6d03bc60b6f5cce68 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 31 11:59:58 2014 -0500 util/cbmem: handle larger than 1MiB mappings for console In some cases the cbmem console can be larger than the default mapping size of 1MiB. Therefore, add the ability to do a mapping that is larger than the default mapping using map_memory_size(). The console printing code will unconditionally map the console based on the size it finds in the cbmem entry. Change-Id: I016420576b9523ce81195160ae86ad16952b761c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 50 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index dd80c08..9ad1214 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -79,19 +79,45 @@ static u16 ipchcksum(const void *addr, unsigned size) * functions always maps 1MB at a time and can only map one area at once. */ static void *mapped_virtual; -static void *map_memory(u64 physical) +static size_t mapped_size; + +static inline size_t size_to_mib(size_t sz) +{ + return sz >> 20; +} + +static void unmap_memory(void) +{ + if (mapped_virtual == NULL) { + fprintf(stderr, "Error unmapping memory\n"); + return; + } + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + munmap(mapped_virtual, mapped_size); + mapped_virtual = NULL; + mapped_size = 0; +} + +static void *map_memory_size(u64 physical, size_t size) { void *v; off_t p; u64 page = getpagesize(); - int padding; + size_t padding; + + if (mapped_virtual != NULL) + unmap_memory(); /* Mapped memory must be aligned to page size */ p = physical & ~(page - 1); + padding = physical & (page-1); + size += padding; - debug("Mapping 1MB of physical memory at 0x%jx.\n", (intmax_t)p); + debug("Mapping %zuMB of physical memory at 0x%jx.\n", + size_to_mib(size), (intmax_t)p); - v = mmap(NULL, MAP_BYTES, PROT_READ, MAP_SHARED, fd, p); + v = mmap(NULL, size, PROT_READ, MAP_SHARED, fd, p); if (v == MAP_FAILED) { fprintf(stderr, "Failed to mmap /dev/mem: %s\n", @@ -101,26 +127,20 @@ static void *map_memory(u64 physical) /* Remember what we actually mapped ... */ mapped_virtual = v; + mapped_size = size; /* ... but return address to the physical memory that was requested */ - padding = physical & (page-1); if (padding) - debug(" ... padding virtual address with 0x%x bytes.\n", + debug(" ... padding virtual address with 0x%zx bytes.\n", padding); v += padding; return v; } -static void unmap_memory(void) +static void *map_memory(u64 physical) { - if (mapped_virtual == NULL) { - fprintf(stderr, "Error unmapping memory\n"); - return; - } - debug("Unmapping 1MB of virtual memory at %p.\n", mapped_virtual); - munmap(mapped_virtual, MAP_BYTES); - mapped_virtual = NULL; + return map_memory_size(physical, MAP_BYTES); } /* @@ -464,6 +484,8 @@ static void dump_console(void) exit(1); } + console_p = map_memory_size((unsigned long)console.cbmem_addr, + size + sizeof(size) + sizeof(cursor)); memcpy(console_c, console_p + 8, size); console_c[size] = 0;

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New patch to review for coreboot: 4c64378 SeaBIOS: have coreboot pass the choice to run optionroms in parallel
by Idwer Vollering 01 Apr '14

01 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5443 -gerrit commit 4c643785b2b28033fc1091d3414346a63fb6893e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Apr 1 22:47:33 2014 +0000 SeaBIOS: have coreboot pass the choice to run optionroms in parallel Introduce the tunable CONFIG_SEABIOS_THREAD_OPTIONROMS. Change-Id: Ifd4d9fca7316eb739ff184e54bdc1cdb0262f0c6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 11 +++++++++++ src/arch/x86/Makefile.inc | 1 + 3 files changed, 16 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 23b064c..e8bcaec 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -21,12 +21,16 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" $(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out/ echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + echo "CONFIG_THREAD_OPTIONROMS=y" >> $(OUT)/seabios/.config +endif echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_COREBOOT=y" >> $(OUT)/seabios/.config # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config diff --git a/src/Kconfig b/src/Kconfig index 291b166..243fd40 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -636,6 +636,17 @@ config SEABIOS_PS2_TIMEOUT after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up. +config SEABIOS_THREAD_OPTIONROMS + prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS + default n + boolean + help + Allow hardware init to run in parallel with optionrom execution. + + This can reduce boot time, but can cause some timing + variations during option ROM code execution. It is not + known if all option ROMs will behave properly with this option. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 80e731f..3bf3326 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -448,6 +448,7 @@ seabios: AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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coreboot-gerrit April 2014