coreboot-gerrit April 2014

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Patch set updated for coreboot: 56fa0f2 asus/f2a85-m: Sanitize #includes
by Idwer Vollering 03 Apr '14

03 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5420 -gerrit commit 56fa0f2fd91ba89d1fe7ff2bcab773ffcf9bff4b Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Mar 29 13:13:10 2014 +0100 asus/f2a85-m: Sanitize #includes Based on the same reasoning as this commit: 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 8 ++-- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 7 +--- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 5 +-- src/mainboard/asus/f2a85-m/acpi_tables.c | 13 +++---- src/mainboard/asus/f2a85-m/agesawrapper.c | 27 +++++--------- src/mainboard/asus/f2a85-m/agesawrapper.h | 3 +- src/mainboard/asus/f2a85-m/buildOpts.c | 43 +++++++++------------- src/mainboard/asus/f2a85-m/get_bus_conf.c | 7 ++-- src/mainboard/asus/f2a85-m/irq_tables.c | 7 ++-- src/mainboard/asus/f2a85-m/mainboard.c | 14 +++---- src/mainboard/asus/f2a85-m/mptable.c | 12 +++--- src/mainboard/asus/f2a85-m/romstage.c | 36 +++++++++--------- 12 files changed, 76 insertions(+), 106 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 2bc0055..89b002b 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,13 +18,11 @@ */ #include "agesawrapper.h" -#include "amdlib.h" #include "BiosCallOuts.h" -#include "Ids.h" #include "OptionsIds.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" + +#include <cbfs.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ff64c6..ee5b5ff 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index b3c69cf..add9008 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -20,9 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index d93fecc..d23c2ea 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -17,19 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam15.h> - -#include "agesawrapper.h" +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 233d2bb..3b7b263 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -22,30 +22,21 @@ *---------------------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> + #include <arch/acpi.h> #include <arch/io.h> +#include <cbmem.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> -#include "hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <stdint.h> +#include <string.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h index 5007510..29eedaf 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -26,8 +26,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 0091cd9..cbd1071 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -33,9 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "AGESA.h" -//#include "CommonReturns.h" -#include "Filecode.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the cpu family. */ @@ -251,22 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList -//#include "VirgoInstall.h" - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} @@ -364,7 +360,8 @@ GPIO_CONTROL f2a85_m_gpio[] = { #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -#include "PlatformInstall.h" +/* Moving this include up will break AGESA. */ +#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -451,12 +448,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" - // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index c92fea9..b915d76 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -17,14 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" +#include <string.h> /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index d5339ad..a7552e8 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -17,12 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> #include <arch/pirq_routing.h> +#include <console/console.h> #include <cpu/amd/amdfam15.h> +#include <stdint.h> +#include <string.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 266c813..16a2e1c 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include "BiosCallOuts.h" -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/acpi.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" /************************************************* * enable the dedicated function in thatcher board. diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 97df048..fc16211 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -17,18 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> +#include <arch/cpu.h> #include <arch/io.h> -#include <string.h> -#include <stdint.h> +#include <arch/smp/mpspec.h> #include <cpu/amd/amdfam15.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ - //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..bc7546c 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -18,27 +18,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> -#include <console/loglevel.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" -#include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" -#include "cbmem.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> +/* TODO: remove .c includes */ +#include <drivers/pc80/i8254.c> +#include <drivers/pc80/i8259.c> +#include <superio/ite/it8712f/early_serial.c> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void);

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Patch set updated for coreboot: eb1f114 asus/f2a85-m: Sanitize #includes
by Idwer Vollering 03 Apr '14

03 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5420 -gerrit commit eb1f1147512890e26e3430676a39fcd0dc8fb3f0 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Mar 29 13:13:10 2014 +0100 asus/f2a85-m: Sanitize #includes Based on the same reasoning as this commit: 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 8 ++-- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 7 +--- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 5 +-- src/mainboard/asus/f2a85-m/acpi_tables.c | 13 +++---- src/mainboard/asus/f2a85-m/agesawrapper.c | 27 +++++--------- src/mainboard/asus/f2a85-m/agesawrapper.h | 3 +- src/mainboard/asus/f2a85-m/buildOpts.c | 43 +++++++++------------- src/mainboard/asus/f2a85-m/get_bus_conf.c | 7 ++-- src/mainboard/asus/f2a85-m/irq_tables.c | 7 ++-- src/mainboard/asus/f2a85-m/mainboard.c | 14 +++---- src/mainboard/asus/f2a85-m/mptable.c | 12 +++--- src/mainboard/asus/f2a85-m/romstage.c | 36 +++++++++--------- 12 files changed, 76 insertions(+), 106 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 2bc0055..89b002b 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,13 +18,11 @@ */ #include "agesawrapper.h" -#include "amdlib.h" #include "BiosCallOuts.h" -#include "Ids.h" #include "OptionsIds.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" + +#include <cbfs.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ff64c6..ee5b5ff 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index b3c69cf..add9008 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -20,9 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index d93fecc..d23c2ea 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -17,19 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam15.h> - -#include "agesawrapper.h" +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 233d2bb..3b7b263 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -22,30 +22,21 @@ *---------------------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> + #include <arch/acpi.h> #include <arch/io.h> +#include <cbmem.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> -#include "hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <stdint.h> +#include <string.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h index 5007510..29eedaf 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -26,8 +26,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 0091cd9..cbd1071 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -33,9 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "AGESA.h" -//#include "CommonReturns.h" -#include "Filecode.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the cpu family. */ @@ -251,22 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList -//#include "VirgoInstall.h" - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} @@ -364,7 +360,8 @@ GPIO_CONTROL f2a85_m_gpio[] = { #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -#include "PlatformInstall.h" +/* Moving this include up will break AGESA. */ +#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -451,12 +448,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" - // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index c92fea9..b915d76 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -17,14 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" +#include <string.h> /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index d5339ad..a7552e8 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -17,12 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> #include <arch/pirq_routing.h> +#include <console/console.h> #include <cpu/amd/amdfam15.h> +#include <stdint.h> +#include <string.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 266c813..16a2e1c 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include "BiosCallOuts.h" -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/acpi.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" /************************************************* * enable the dedicated function in thatcher board. diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 97df048..fc16211 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -17,18 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> +#include <arch/cpu.h> #include <arch/io.h> -#include <string.h> -#include <stdint.h> +#include <arch/smp/mpspec.h> #include <cpu/amd/amdfam15.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ - //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..bc7546c 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -18,27 +18,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> -#include <console/loglevel.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" -#include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" -#include "cbmem.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> +/* TODO: remove .c includes */ +#include <drivers/pc80/i8254.c> +#include <drivers/pc80/i8259.c> +#include <superio/ite/it8712f/early_serial.c> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void);

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Patch set updated for coreboot: 01c20d5 asus/f2a85-m: Sanitize #includes
by Idwer Vollering 03 Apr '14

03 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5420 -gerrit commit 01c20d5b2ad3eb5464779e1973d6e0cfc10d082e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Mar 29 13:13:10 2014 +0100 asus/f2a85-m: Sanitize #includes There were a number of things wrong with the includes. First, The includes did not use paths to AGESA files, thus relying on the compiler include paths to find the correct file. This made it unclear where the file included was located, and whether it was local, under vendorcode, or under a different directory. Instead, use full paths for each non-local include. Second, the local includes were mixed with the rest, making it unclear which file is local and which one is not. Keep the local includes at the top. This also prevents us from polluting the namespace of local headers, with library definitions, and allows us to catch if we missed an otherwise needed external header. Thirdly, alphabetize the order of includes where possible. Based on the same reasoning as this commit: 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 8 ++-- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 7 +--- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 5 +-- src/mainboard/asus/f2a85-m/acpi_tables.c | 13 +++---- src/mainboard/asus/f2a85-m/agesawrapper.c | 27 +++++--------- src/mainboard/asus/f2a85-m/agesawrapper.h | 3 +- src/mainboard/asus/f2a85-m/buildOpts.c | 43 +++++++++------------- src/mainboard/asus/f2a85-m/get_bus_conf.c | 7 ++-- src/mainboard/asus/f2a85-m/irq_tables.c | 7 ++-- src/mainboard/asus/f2a85-m/mainboard.c | 14 +++---- src/mainboard/asus/f2a85-m/mptable.c | 12 +++--- src/mainboard/asus/f2a85-m/romstage.c | 36 +++++++++--------- 12 files changed, 76 insertions(+), 106 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 2bc0055..89b002b 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,13 +18,11 @@ */ #include "agesawrapper.h" -#include "amdlib.h" #include "BiosCallOuts.h" -#include "Ids.h" #include "OptionsIds.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" + +#include <cbfs.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ff64c6..ee5b5ff 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index b3c69cf..add9008 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -20,9 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index d93fecc..d23c2ea 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -17,19 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam15.h> - -#include "agesawrapper.h" +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 233d2bb..3b7b263 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -22,30 +22,21 @@ *---------------------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> + #include <arch/acpi.h> #include <arch/io.h> +#include <cbmem.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> -#include "hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <stdint.h> +#include <string.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h index 5007510..29eedaf 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -26,8 +26,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 0091cd9..cbd1071 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -33,9 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "AGESA.h" -//#include "CommonReturns.h" -#include "Filecode.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the cpu family. */ @@ -251,22 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList -//#include "VirgoInstall.h" - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} @@ -364,7 +360,8 @@ GPIO_CONTROL f2a85_m_gpio[] = { #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -#include "PlatformInstall.h" +/* Moving this include up will break AGESA. */ +#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -451,12 +448,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" - // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index c92fea9..b915d76 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -17,14 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" +#include <string.h> /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index d5339ad..a7552e8 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -17,12 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> #include <arch/pirq_routing.h> +#include <console/console.h> #include <cpu/amd/amdfam15.h> +#include <stdint.h> +#include <string.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 266c813..16a2e1c 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include "BiosCallOuts.h" -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/acpi.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" /************************************************* * enable the dedicated function in thatcher board. diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 97df048..fc16211 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -17,18 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> +#include <arch/cpu.h> #include <arch/io.h> -#include <string.h> -#include <stdint.h> +#include <arch/smp/mpspec.h> #include <cpu/amd/amdfam15.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ - //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..bc7546c 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -18,27 +18,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> -#include <console/loglevel.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" -#include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" -#include "cbmem.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> +/* TODO: remove .c includes */ +#include <drivers/pc80/i8254.c> +#include <drivers/pc80/i8259.c> +#include <superio/ite/it8712f/early_serial.c> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void);

1 0

Patch set updated for coreboot: b4dc78b Enable pages. Tested and working on QEMU.
by Ronald G. Minnich 03 Apr '14

03 Apr '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5354 -gerrit commit b4dc78b5c865c6c6ea3e06acd548699815593439 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Mar 8 17:33:12 2014 +0100 Enable pages. Tested and working on QEMU. Enable page tables in coreboot. We're going to have to do this at some point, when we hit x86_64; the ARM ports do paging in both 32- and 64-bit modes; MTRR is a PITA; and it's easy. The non-paging architectures are outnumbered by the paging architectures! This trial example just sets up a 4G identity map using 4M pages. It works for QEMU just fine to boot tinycore linux. The next step is to map the low 4M much more finely, with 4K pages, so we can catch NULL pointers. This will require reworking VGA bios support, which uses page 0. For SMP, we'll need to add code to let them also load page tables, but one thing at a time. Next I'll add code to support page table manipulation. With luck, we can stop fighting the MTRRs with all their pain and suffering. We can use the MTRRs for very coarse mappings and use the page tables to refine them. For example, we could stop using fixed MTRRs entirely since we can map parts of the low 1M as WP or even UC on a 4k granularity. For now we use this for machines where coreboot can live in the low 4G. For other cases, it's time to start thinking about 64-bit mode; since entering Long Mode requires page tables, we need to figure it out. The ARM V8 port is carving the way so this is as good a time as any. This code is enabled by CONFIG_PGE, which defaults to n. To turn it on navigate to architecture options in menuconfig. A remaining question is whether to turn off paging when we start the payload. For now, we turn it off. Also, if they payload returns, we hang until such time as we turn paging back on (which is easy, actually). Change-Id: Iea0192e5187c47e63d25f88eaa3e88cb6c58feb1 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 11 ++ src/arch/x86/Makefile.inc | 3 + src/arch/x86/boot/boot.c | 20 +++ src/arch/x86/init/ldscript_failover.lb | 2 +- src/arch/x86/lib/c_start.S | 5 +- src/arch/x86/lib/pagetables.S | 244 +++++++++++++++++++++++++++++++++ src/arch/x86/lib/paging.S | 58 ++++++++ 7 files changed, 341 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 8854e6b..0c0f91c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -78,6 +78,17 @@ config UPDATE_IMAGE is a suitable file for further processing. The bootblock will not be modified. +config PGE + bool "Enable x86 page tables." + default n + help + In original coreboot we did not use page tables. The + MTRR code just keeps getting messier and if we turn + on paging it gets very easy. We can enable disable + caching on anything down to a 4k boundary. We can + control cache disable and write-back/writethrough + on each page. For now, this code creates an identity + map for 4G using 4M pages. config ROMCC bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index acb4e98..f004be8 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -354,6 +354,9 @@ bootblock_inc = $(src)/arch/x86/init/prologue.inc bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc +ifeq ($(CONFIG_PGE),y) +bootblock_inc += $(src)/arch/x86/lib/paging.S +endif bootblock_inc += $(src)/arch/x86/lib/id.inc ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) bootblock_inc += $(src)/cpu/intel/fit/fit.inc diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 29070a0..ca8af27 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -11,6 +11,12 @@ static void jmp_payload_no_bounce_buffer(void *entry) /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" + /* Paging might have been on. We need to turn it off + * right before we jump + */ + " movl %%cr0, %%eax\n\t" + " andl $0x7fffffff, %%eax\n\t" + " movl %%edx, %%cr0\n\t" /* Now jump to the loaded image */ " call *%0\n\t" @@ -73,6 +79,16 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " jmp *%%eax\n\t" "1: \n\t" + /* Paging might have been on. It's ok, + * the bounce buffer runs at same VA and PA. + * So we can turn paging off now. + */ + " movl %%cr0, %%eax\n\t" + " andl $0x7fffffff, %%eax\n\t" + " movl %%eax, %%cr0\n\t" + " jmp 1f\n\t" + "1:\n\t" + /* Copy the coreboot bounce buffer over coreboot */ /* Move ``longs'' the coreboot size is 4 byte aligned */ " movl 16(%%esp), %%edi\n\t" @@ -85,6 +101,10 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " movl %5, %%eax\n\t" " movl 0(%%esp), %%ebx\n\t" " call *4(%%esp)\n\t" +#if CONFIG_PGE + /* TODO: turn paging back on. For now, just hang. */ + "1: jmp 1b\n\t" +#endif /* The loaded image returned? */ " cli \n\t" diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 318f429..4d24e73 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -54,7 +54,7 @@ SECTIONS * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0) - 8192; /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index faea22d..bbf3308 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -33,7 +33,10 @@ _start: movl %eax, %gs post_code(POST_ENTRY_C_START) /* post 13 */ - + /* turn on paging (conditional on CONFIG_PGE) */ +#if CONFIG_PGE +#include "paging.S" +#endif cld /** poison the stack. Code should not count on the diff --git a/src/arch/x86/lib/pagetables.S b/src/arch/x86/lib/pagetables.S new file mode 100644 index 0000000..e87c1bf --- /dev/null +++ b/src/arch/x86/lib/pagetables.S @@ -0,0 +1,244 @@ + .long 1 + .align 4096 + +/* Create a PTE given an address. It's your responsibility to make + * sure the address meets all requirements, viz., low order 12 bits + * are zero. The PTE will have the Present (1) and Write (4) bits set. + */ +#define PTE(x) ((x)|5) +/* Create an entry for a 4K page, with Present bit (1) and Write bit (4) set + * The parameter is a page number, not an address. For 32-bit mode, use .long; + * for 64-bit mode, use .llong + */ +#define P4K(x) ((x<<12)|5) + +/* Create an entry for a 32-bit 4M page, with Page Size (0x80), Present bit + * (1) and Write bit (4) set The parameter is a 4M page number, not an + * address. + */ +#define P4M(x) ((x<<22) | 0x80 | 5) + +/* Create an entry for a 64-bit 2M page, with Page Size (0x80), + * Present bit (1) and Write bit (4) set The parameter is a page + * number, not an address. + */ +#define P2M(x) ((x<<21) | 0x80 | 5) + +/* Define a Page Map Level 2 of 4M entries to identity-map + * the low 4G of memory. This is just enough to get us into + * Long Mode. + */ +PageMapLevel2: + .long P4M(0x000),P4M(0x001),P4M(0x002),P4M(0x003),P4M(0x004),P4M(0x005),P4M(0x006),P4M(0x007) + .long P4M(0x008),P4M(0x009),P4M(0x00a),P4M(0x00b),P4M(0x00c),P4M(0x00d),P4M(0x00e),P4M(0x00f) + .long P4M(0x010),P4M(0x011),P4M(0x012),P4M(0x013),P4M(0x014),P4M(0x015),P4M(0x016),P4M(0x017) + .long P4M(0x018),P4M(0x019),P4M(0x01a),P4M(0x01b),P4M(0x01c),P4M(0x01d),P4M(0x01e),P4M(0x01f) + .long P4M(0x020),P4M(0x021),P4M(0x022),P4M(0x023),P4M(0x024),P4M(0x025),P4M(0x026),P4M(0x027) + .long P4M(0x028),P4M(0x029),P4M(0x02a),P4M(0x02b),P4M(0x02c),P4M(0x02d),P4M(0x02e),P4M(0x02f) + .long P4M(0x030),P4M(0x031),P4M(0x032),P4M(0x033),P4M(0x034),P4M(0x035),P4M(0x036),P4M(0x037) + .long P4M(0x038),P4M(0x039),P4M(0x03a),P4M(0x03b),P4M(0x03c),P4M(0x03d),P4M(0x03e),P4M(0x03f) + .long P4M(0x040),P4M(0x041),P4M(0x042),P4M(0x043),P4M(0x044),P4M(0x045),P4M(0x046),P4M(0x047) + .long P4M(0x048),P4M(0x049),P4M(0x04a),P4M(0x04b),P4M(0x04c),P4M(0x04d),P4M(0x04e),P4M(0x04f) + .long P4M(0x050),P4M(0x051),P4M(0x052),P4M(0x053),P4M(0x054),P4M(0x055),P4M(0x056),P4M(0x057) + .long P4M(0x058),P4M(0x059),P4M(0x05a),P4M(0x05b),P4M(0x05c),P4M(0x05d),P4M(0x05e),P4M(0x05f) + .long P4M(0x060),P4M(0x061),P4M(0x062),P4M(0x063),P4M(0x064),P4M(0x065),P4M(0x066),P4M(0x067) + .long P4M(0x068),P4M(0x069),P4M(0x06a),P4M(0x06b),P4M(0x06c),P4M(0x06d),P4M(0x06e),P4M(0x06f) + .long P4M(0x070),P4M(0x071),P4M(0x072),P4M(0x073),P4M(0x074),P4M(0x075),P4M(0x076),P4M(0x077) + .long P4M(0x078),P4M(0x079),P4M(0x07a),P4M(0x07b),P4M(0x07c),P4M(0x07d),P4M(0x07e),P4M(0x07f) + .long P4M(0x080),P4M(0x081),P4M(0x082),P4M(0x083),P4M(0x084),P4M(0x085),P4M(0x086),P4M(0x087) + .long P4M(0x088),P4M(0x089),P4M(0x08a),P4M(0x08b),P4M(0x08c),P4M(0x08d),P4M(0x08e),P4M(0x08f) + .long P4M(0x090),P4M(0x091),P4M(0x092),P4M(0x093),P4M(0x094),P4M(0x095),P4M(0x096),P4M(0x097) + .long P4M(0x098),P4M(0x099),P4M(0x09a),P4M(0x09b),P4M(0x09c),P4M(0x09d),P4M(0x09e),P4M(0x09f) + .long P4M(0x0a0),P4M(0x0a1),P4M(0x0a2),P4M(0x0a3),P4M(0x0a4),P4M(0x0a5),P4M(0x0a6),P4M(0x0a7) + .long P4M(0x0a8),P4M(0x0a9),P4M(0x0aa),P4M(0x0ab),P4M(0x0ac),P4M(0x0ad),P4M(0x0ae),P4M(0x0af) + .long P4M(0x0b0),P4M(0x0b1),P4M(0x0b2),P4M(0x0b3),P4M(0x0b4),P4M(0x0b5),P4M(0x0b6),P4M(0x0b7) + .long P4M(0x0b8),P4M(0x0b9),P4M(0x0ba),P4M(0x0bb),P4M(0x0bc),P4M(0x0bd),P4M(0x0be),P4M(0x0bf) + .long P4M(0x0c0),P4M(0x0c1),P4M(0x0c2),P4M(0x0c3),P4M(0x0c4),P4M(0x0c5),P4M(0x0c6),P4M(0x0c7) + .long P4M(0x0c8),P4M(0x0c9),P4M(0x0ca),P4M(0x0cb),P4M(0x0cc),P4M(0x0cd),P4M(0x0ce),P4M(0x0cf) + .long P4M(0x0d0),P4M(0x0d1),P4M(0x0d2),P4M(0x0d3),P4M(0x0d4),P4M(0x0d5),P4M(0x0d6),P4M(0x0d7) + .long P4M(0x0d8),P4M(0x0d9),P4M(0x0da),P4M(0x0db),P4M(0x0dc),P4M(0x0dd),P4M(0x0de),P4M(0x0df) + .long P4M(0x0e0),P4M(0x0e1),P4M(0x0e2),P4M(0x0e3),P4M(0x0e4),P4M(0x0e5),P4M(0x0e6),P4M(0x0e7) + .long P4M(0x0e8),P4M(0x0e9),P4M(0x0ea),P4M(0x0eb),P4M(0x0ec),P4M(0x0ed),P4M(0x0ee),P4M(0x0ef) + .long P4M(0x0f0),P4M(0x0f1),P4M(0x0f2),P4M(0x0f3),P4M(0x0f4),P4M(0x0f5),P4M(0x0f6),P4M(0x0f7) + .long P4M(0x0f8),P4M(0x0f9),P4M(0x0fa),P4M(0x0fb),P4M(0x0fc),P4M(0x0fd),P4M(0x0fe),P4M(0x0ff) + .long P4M(0x100),P4M(0x101),P4M(0x102),P4M(0x103),P4M(0x104),P4M(0x105),P4M(0x106),P4M(0x107) + .long P4M(0x108),P4M(0x109),P4M(0x10a),P4M(0x10b),P4M(0x10c),P4M(0x10d),P4M(0x10e),P4M(0x10f) + .long P4M(0x110),P4M(0x111),P4M(0x112),P4M(0x113),P4M(0x114),P4M(0x115),P4M(0x116),P4M(0x117) + .long P4M(0x118),P4M(0x119),P4M(0x11a),P4M(0x11b),P4M(0x11c),P4M(0x11d),P4M(0x11e),P4M(0x11f) + .long P4M(0x120),P4M(0x121),P4M(0x122),P4M(0x123),P4M(0x124),P4M(0x125),P4M(0x126),P4M(0x127) + .long P4M(0x128),P4M(0x129),P4M(0x12a),P4M(0x12b),P4M(0x12c),P4M(0x12d),P4M(0x12e),P4M(0x12f) + .long P4M(0x130),P4M(0x131),P4M(0x132),P4M(0x133),P4M(0x134),P4M(0x135),P4M(0x136),P4M(0x137) + .long P4M(0x138),P4M(0x139),P4M(0x13a),P4M(0x13b),P4M(0x13c),P4M(0x13d),P4M(0x13e),P4M(0x13f) + .long P4M(0x140),P4M(0x141),P4M(0x142),P4M(0x143),P4M(0x144),P4M(0x145),P4M(0x146),P4M(0x147) + .long P4M(0x148),P4M(0x149),P4M(0x14a),P4M(0x14b),P4M(0x14c),P4M(0x14d),P4M(0x14e),P4M(0x14f) + .long P4M(0x150),P4M(0x151),P4M(0x152),P4M(0x153),P4M(0x154),P4M(0x155),P4M(0x156),P4M(0x157) + .long P4M(0x158),P4M(0x159),P4M(0x15a),P4M(0x15b),P4M(0x15c),P4M(0x15d),P4M(0x15e),P4M(0x15f) + .long P4M(0x160),P4M(0x161),P4M(0x162),P4M(0x163),P4M(0x164),P4M(0x165),P4M(0x166),P4M(0x167) + .long P4M(0x168),P4M(0x169),P4M(0x16a),P4M(0x16b),P4M(0x16c),P4M(0x16d),P4M(0x16e),P4M(0x16f) + .long P4M(0x170),P4M(0x171),P4M(0x172),P4M(0x173),P4M(0x174),P4M(0x175),P4M(0x176),P4M(0x177) + .long P4M(0x178),P4M(0x179),P4M(0x17a),P4M(0x17b),P4M(0x17c),P4M(0x17d),P4M(0x17e),P4M(0x17f) + .long P4M(0x180),P4M(0x181),P4M(0x182),P4M(0x183),P4M(0x184),P4M(0x185),P4M(0x186),P4M(0x187) + .long P4M(0x188),P4M(0x189),P4M(0x18a),P4M(0x18b),P4M(0x18c),P4M(0x18d),P4M(0x18e),P4M(0x18f) + .long P4M(0x190),P4M(0x191),P4M(0x192),P4M(0x193),P4M(0x194),P4M(0x195),P4M(0x196),P4M(0x197) + .long P4M(0x198),P4M(0x199),P4M(0x19a),P4M(0x19b),P4M(0x19c),P4M(0x19d),P4M(0x19e),P4M(0x19f) + .long P4M(0x1a0),P4M(0x1a1),P4M(0x1a2),P4M(0x1a3),P4M(0x1a4),P4M(0x1a5),P4M(0x1a6),P4M(0x1a7) + .long P4M(0x1a8),P4M(0x1a9),P4M(0x1aa),P4M(0x1ab),P4M(0x1ac),P4M(0x1ad),P4M(0x1ae),P4M(0x1af) + .long P4M(0x1b0),P4M(0x1b1),P4M(0x1b2),P4M(0x1b3),P4M(0x1b4),P4M(0x1b5),P4M(0x1b6),P4M(0x1b7) + .long P4M(0x1b8),P4M(0x1b9),P4M(0x1ba),P4M(0x1bb),P4M(0x1bc),P4M(0x1bd),P4M(0x1be),P4M(0x1bf) + .long P4M(0x1c0),P4M(0x1c1),P4M(0x1c2),P4M(0x1c3),P4M(0x1c4),P4M(0x1c5),P4M(0x1c6),P4M(0x1c7) + .long P4M(0x1c8),P4M(0x1c9),P4M(0x1ca),P4M(0x1cb),P4M(0x1cc),P4M(0x1cd),P4M(0x1ce),P4M(0x1cf) + .long P4M(0x1d0),P4M(0x1d1),P4M(0x1d2),P4M(0x1d3),P4M(0x1d4),P4M(0x1d5),P4M(0x1d6),P4M(0x1d7) + .long P4M(0x1d8),P4M(0x1d9),P4M(0x1da),P4M(0x1db),P4M(0x1dc),P4M(0x1dd),P4M(0x1de),P4M(0x1df) + .long P4M(0x1e0),P4M(0x1e1),P4M(0x1e2),P4M(0x1e3),P4M(0x1e4),P4M(0x1e5),P4M(0x1e6),P4M(0x1e7) + .long P4M(0x1e8),P4M(0x1e9),P4M(0x1ea),P4M(0x1eb),P4M(0x1ec),P4M(0x1ed),P4M(0x1ee),P4M(0x1ef) + .long P4M(0x1f0),P4M(0x1f1),P4M(0x1f2),P4M(0x1f3),P4M(0x1f4),P4M(0x1f5),P4M(0x1f6),P4M(0x1f7) + .long P4M(0x1f8),P4M(0x1f9),P4M(0x1fa),P4M(0x1fb),P4M(0x1fc),P4M(0x1fd),P4M(0x1fe),P4M(0x1ff) + .long P4M(0x200),P4M(0x201),P4M(0x202),P4M(0x203),P4M(0x204),P4M(0x205),P4M(0x206),P4M(0x207) + .long P4M(0x208),P4M(0x209),P4M(0x20a),P4M(0x20b),P4M(0x20c),P4M(0x20d),P4M(0x20e),P4M(0x20f) + .long P4M(0x210),P4M(0x211),P4M(0x212),P4M(0x213),P4M(0x214),P4M(0x215),P4M(0x216),P4M(0x217) + .long P4M(0x218),P4M(0x219),P4M(0x21a),P4M(0x21b),P4M(0x21c),P4M(0x21d),P4M(0x21e),P4M(0x21f) + .long P4M(0x220),P4M(0x221),P4M(0x222),P4M(0x223),P4M(0x224),P4M(0x225),P4M(0x226),P4M(0x227) + .long P4M(0x228),P4M(0x229),P4M(0x22a),P4M(0x22b),P4M(0x22c),P4M(0x22d),P4M(0x22e),P4M(0x22f) + .long P4M(0x230),P4M(0x231),P4M(0x232),P4M(0x233),P4M(0x234),P4M(0x235),P4M(0x236),P4M(0x237) + .long P4M(0x238),P4M(0x239),P4M(0x23a),P4M(0x23b),P4M(0x23c),P4M(0x23d),P4M(0x23e),P4M(0x23f) + .long P4M(0x240),P4M(0x241),P4M(0x242),P4M(0x243),P4M(0x244),P4M(0x245),P4M(0x246),P4M(0x247) + .long P4M(0x248),P4M(0x249),P4M(0x24a),P4M(0x24b),P4M(0x24c),P4M(0x24d),P4M(0x24e),P4M(0x24f) + .long P4M(0x250),P4M(0x251),P4M(0x252),P4M(0x253),P4M(0x254),P4M(0x255),P4M(0x256),P4M(0x257) + .long P4M(0x258),P4M(0x259),P4M(0x25a),P4M(0x25b),P4M(0x25c),P4M(0x25d),P4M(0x25e),P4M(0x25f) + .long P4M(0x260),P4M(0x261),P4M(0x262),P4M(0x263),P4M(0x264),P4M(0x265),P4M(0x266),P4M(0x267) + .long P4M(0x268),P4M(0x269),P4M(0x26a),P4M(0x26b),P4M(0x26c),P4M(0x26d),P4M(0x26e),P4M(0x26f) + .long P4M(0x270),P4M(0x271),P4M(0x272),P4M(0x273),P4M(0x274),P4M(0x275),P4M(0x276),P4M(0x277) + .long P4M(0x278),P4M(0x279),P4M(0x27a),P4M(0x27b),P4M(0x27c),P4M(0x27d),P4M(0x27e),P4M(0x27f) + .long P4M(0x280),P4M(0x281),P4M(0x282),P4M(0x283),P4M(0x284),P4M(0x285),P4M(0x286),P4M(0x287) + .long P4M(0x288),P4M(0x289),P4M(0x28a),P4M(0x28b),P4M(0x28c),P4M(0x28d),P4M(0x28e),P4M(0x28f) + .long P4M(0x290),P4M(0x291),P4M(0x292),P4M(0x293),P4M(0x294),P4M(0x295),P4M(0x296),P4M(0x297) + .long P4M(0x298),P4M(0x299),P4M(0x29a),P4M(0x29b),P4M(0x29c),P4M(0x29d),P4M(0x29e),P4M(0x29f) + .long P4M(0x2a0),P4M(0x2a1),P4M(0x2a2),P4M(0x2a3),P4M(0x2a4),P4M(0x2a5),P4M(0x2a6),P4M(0x2a7) + .long P4M(0x2a8),P4M(0x2a9),P4M(0x2aa),P4M(0x2ab),P4M(0x2ac),P4M(0x2ad),P4M(0x2ae),P4M(0x2af) + .long P4M(0x2b0),P4M(0x2b1),P4M(0x2b2),P4M(0x2b3),P4M(0x2b4),P4M(0x2b5),P4M(0x2b6),P4M(0x2b7) + .long P4M(0x2b8),P4M(0x2b9),P4M(0x2ba),P4M(0x2bb),P4M(0x2bc),P4M(0x2bd),P4M(0x2be),P4M(0x2bf) + .long P4M(0x2c0),P4M(0x2c1),P4M(0x2c2),P4M(0x2c3),P4M(0x2c4),P4M(0x2c5),P4M(0x2c6),P4M(0x2c7) + .long P4M(0x2c8),P4M(0x2c9),P4M(0x2ca),P4M(0x2cb),P4M(0x2cc),P4M(0x2cd),P4M(0x2ce),P4M(0x2cf) + .long P4M(0x2d0),P4M(0x2d1),P4M(0x2d2),P4M(0x2d3),P4M(0x2d4),P4M(0x2d5),P4M(0x2d6),P4M(0x2d7) + .long P4M(0x2d8),P4M(0x2d9),P4M(0x2da),P4M(0x2db),P4M(0x2dc),P4M(0x2dd),P4M(0x2de),P4M(0x2df) + .long P4M(0x2e0),P4M(0x2e1),P4M(0x2e2),P4M(0x2e3),P4M(0x2e4),P4M(0x2e5),P4M(0x2e6),P4M(0x2e7) + .long P4M(0x2e8),P4M(0x2e9),P4M(0x2ea),P4M(0x2eb),P4M(0x2ec),P4M(0x2ed),P4M(0x2ee),P4M(0x2ef) + .long P4M(0x2f0),P4M(0x2f1),P4M(0x2f2),P4M(0x2f3),P4M(0x2f4),P4M(0x2f5),P4M(0x2f6),P4M(0x2f7) + .long P4M(0x2f8),P4M(0x2f9),P4M(0x2fa),P4M(0x2fb),P4M(0x2fc),P4M(0x2fd),P4M(0x2fe),P4M(0x2ff) + .long P4M(0x300),P4M(0x301),P4M(0x302),P4M(0x303),P4M(0x304),P4M(0x305),P4M(0x306),P4M(0x307) + .long P4M(0x308),P4M(0x309),P4M(0x30a),P4M(0x30b),P4M(0x30c),P4M(0x30d),P4M(0x30e),P4M(0x30f) + .long P4M(0x310),P4M(0x311),P4M(0x312),P4M(0x313),P4M(0x314),P4M(0x315),P4M(0x316),P4M(0x317) + .long P4M(0x318),P4M(0x319),P4M(0x31a),P4M(0x31b),P4M(0x31c),P4M(0x31d),P4M(0x31e),P4M(0x31f) + .long P4M(0x320),P4M(0x321),P4M(0x322),P4M(0x323),P4M(0x324),P4M(0x325),P4M(0x326),P4M(0x327) + .long P4M(0x328),P4M(0x329),P4M(0x32a),P4M(0x32b),P4M(0x32c),P4M(0x32d),P4M(0x32e),P4M(0x32f) + .long P4M(0x330),P4M(0x331),P4M(0x332),P4M(0x333),P4M(0x334),P4M(0x335),P4M(0x336),P4M(0x337) + .long P4M(0x338),P4M(0x339),P4M(0x33a),P4M(0x33b),P4M(0x33c),P4M(0x33d),P4M(0x33e),P4M(0x33f) + .long P4M(0x340),P4M(0x341),P4M(0x342),P4M(0x343),P4M(0x344),P4M(0x345),P4M(0x346),P4M(0x347) + .long P4M(0x348),P4M(0x349),P4M(0x34a),P4M(0x34b),P4M(0x34c),P4M(0x34d),P4M(0x34e),P4M(0x34f) + .long P4M(0x350),P4M(0x351),P4M(0x352),P4M(0x353),P4M(0x354),P4M(0x355),P4M(0x356),P4M(0x357) + .long P4M(0x358),P4M(0x359),P4M(0x35a),P4M(0x35b),P4M(0x35c),P4M(0x35d),P4M(0x35e),P4M(0x35f) + .long P4M(0x360),P4M(0x361),P4M(0x362),P4M(0x363),P4M(0x364),P4M(0x365),P4M(0x366),P4M(0x367) + .long P4M(0x368),P4M(0x369),P4M(0x36a),P4M(0x36b),P4M(0x36c),P4M(0x36d),P4M(0x36e),P4M(0x36f) + .long P4M(0x370),P4M(0x371),P4M(0x372),P4M(0x373),P4M(0x374),P4M(0x375),P4M(0x376),P4M(0x377) + .long P4M(0x378),P4M(0x379),P4M(0x37a),P4M(0x37b),P4M(0x37c),P4M(0x37d),P4M(0x37e),P4M(0x37f) + .long P4M(0x380),P4M(0x381),P4M(0x382),P4M(0x383),P4M(0x384),P4M(0x385),P4M(0x386),P4M(0x387) + .long P4M(0x388),P4M(0x389),P4M(0x38a),P4M(0x38b),P4M(0x38c),P4M(0x38d),P4M(0x38e),P4M(0x38f) + .long P4M(0x390),P4M(0x391),P4M(0x392),P4M(0x393),P4M(0x394),P4M(0x395),P4M(0x396),P4M(0x397) + .long P4M(0x398),P4M(0x399),P4M(0x39a),P4M(0x39b),P4M(0x39c),P4M(0x39d),P4M(0x39e),P4M(0x39f) + .long P4M(0x3a0),P4M(0x3a1),P4M(0x3a2),P4M(0x3a3),P4M(0x3a4),P4M(0x3a5),P4M(0x3a6),P4M(0x3a7) + .long P4M(0x3a8),P4M(0x3a9),P4M(0x3aa),P4M(0x3ab),P4M(0x3ac),P4M(0x3ad),P4M(0x3ae),P4M(0x3af) + .long P4M(0x3b0),P4M(0x3b1),P4M(0x3b2),P4M(0x3b3),P4M(0x3b4),P4M(0x3b5),P4M(0x3b6),P4M(0x3b7) + .long P4M(0x3b8),P4M(0x3b9),P4M(0x3ba),P4M(0x3bb),P4M(0x3bc),P4M(0x3bd),P4M(0x3be),P4M(0x3bf) + .long P4M(0x3c0),P4M(0x3c1),P4M(0x3c2),P4M(0x3c3),P4M(0x3c4),P4M(0x3c5),P4M(0x3c6),P4M(0x3c7) + .long P4M(0x3c8),P4M(0x3c9),P4M(0x3ca),P4M(0x3cb),P4M(0x3cc),P4M(0x3cd),P4M(0x3ce),P4M(0x3cf) + .long P4M(0x3d0),P4M(0x3d1),P4M(0x3d2),P4M(0x3d3),P4M(0x3d4),P4M(0x3d5),P4M(0x3d6),P4M(0x3d7) + .long P4M(0x3d8),P4M(0x3d9),P4M(0x3da),P4M(0x3db),P4M(0x3dc),P4M(0x3dd),P4M(0x3de),P4M(0x3df) + .long P4M(0x3e0),P4M(0x3e1),P4M(0x3e2),P4M(0x3e3),P4M(0x3e4),P4M(0x3e5),P4M(0x3e6),P4M(0x3e7) + .long P4M(0x3e8),P4M(0x3e9),P4M(0x3ea),P4M(0x3eb),P4M(0x3ec),P4M(0x3ed),P4M(0x3ee),P4M(0x3ef) + .long P4M(0x3f0),P4M(0x3f1),P4M(0x3f2),P4M(0x3f3),P4M(0x3f4),P4M(0x3f5),P4M(0x3f6),P4M(0x3f7) + .long P4M(0x3f8),P4M(0x3f9),P4M(0x3fa),P4M(0x3fb),P4M(0x3fc),P4M(0x3fd),P4M(0x3fe),P4M(0x3ff) + +#if 0 // someday +#if CONFIG_ARCH_X86_64 +/* 64 bit GDT ... */ +gdt64: + .quad $0x0000000000000000 /* NULL descriptor */ + .quad $0x0020980000000000 /* CS */ + +gdt64p: + .word 15 // 2*8-1 + .quad $gdt64 +.align 4096 + +pml2: .quad P2M(0x000),P2M(0x001),P2M(0x002),P2M(0x003),P2M(0x004),P2M(0x005),P2M(0x006),P2M(0x007) + .quad P2M(0x008),P2M(0x009),P2M(0x00a),P2M(0x00b),P2M(0x00c),P2M(0x00d),P2M(0x00e),P2M(0x00f) + .quad P2M(0x010),P2M(0x011),P2M(0x012),P2M(0x013),P2M(0x014),P2M(0x015),P2M(0x016),P2M(0x017) + .quad P2M(0x018),P2M(0x019),P2M(0x01a),P2M(0x01b),P2M(0x01c),P2M(0x01d),P2M(0x01e),P2M(0x01f) + .quad P2M(0x020),P2M(0x021),P2M(0x022),P2M(0x023),P2M(0x024),P2M(0x025),P2M(0x026),P2M(0x027) + .quad P2M(0x028),P2M(0x029),P2M(0x02a),P2M(0x02b),P2M(0x02c),P2M(0x02d),P2M(0x02e),P2M(0x02f) + .quad P2M(0x030),P2M(0x031),P2M(0x032),P2M(0x033),P2M(0x034),P2M(0x035),P2M(0x036),P2M(0x037) + .quad P2M(0x038),P2M(0x039),P2M(0x03a),P2M(0x03b),P2M(0x03c),P2M(0x03d),P2M(0x03e),P2M(0x03f) + .quad P2M(0x040),P2M(0x041),P2M(0x042),P2M(0x043),P2M(0x044),P2M(0x045),P2M(0x046),P2M(0x047) + .quad P2M(0x048),P2M(0x049),P2M(0x04a),P2M(0x04b),P2M(0x04c),P2M(0x04d),P2M(0x04e),P2M(0x04f) + .quad P2M(0x050),P2M(0x051),P2M(0x052),P2M(0x053),P2M(0x054),P2M(0x055),P2M(0x056),P2M(0x057) + .quad P2M(0x058),P2M(0x059),P2M(0x05a),P2M(0x05b),P2M(0x05c),P2M(0x05d),P2M(0x05e),P2M(0x05f) + .quad P2M(0x060),P2M(0x061),P2M(0x062),P2M(0x063),P2M(0x064),P2M(0x065),P2M(0x066),P2M(0x067) + .quad P2M(0x068),P2M(0x069),P2M(0x06a),P2M(0x06b),P2M(0x06c),P2M(0x06d),P2M(0x06e),P2M(0x06f) + .quad P2M(0x070),P2M(0x071),P2M(0x072),P2M(0x073),P2M(0x074),P2M(0x075),P2M(0x076),P2M(0x077) + .quad P2M(0x078),P2M(0x079),P2M(0x07a),P2M(0x07b),P2M(0x07c),P2M(0x07d),P2M(0x07e),P2M(0x07f) + .quad P2M(0x080),P2M(0x081),P2M(0x082),P2M(0x083),P2M(0x084),P2M(0x085),P2M(0x086),P2M(0x087) + .quad P2M(0x088),P2M(0x089),P2M(0x08a),P2M(0x08b),P2M(0x08c),P2M(0x08d),P2M(0x08e),P2M(0x08f) + .quad P2M(0x090),P2M(0x091),P2M(0x092),P2M(0x093),P2M(0x094),P2M(0x095),P2M(0x096),P2M(0x097) + .quad P2M(0x098),P2M(0x099),P2M(0x09a),P2M(0x09b),P2M(0x09c),P2M(0x09d),P2M(0x09e),P2M(0x09f) + .quad P2M(0x0a0),P2M(0x0a1),P2M(0x0a2),P2M(0x0a3),P2M(0x0a4),P2M(0x0a5),P2M(0x0a6),P2M(0x0a7) + .quad P2M(0x0a8),P2M(0x0a9),P2M(0x0aa),P2M(0x0ab),P2M(0x0ac),P2M(0x0ad),P2M(0x0ae),P2M(0x0af) + .quad P2M(0x0b0),P2M(0x0b1),P2M(0x0b2),P2M(0x0b3),P2M(0x0b4),P2M(0x0b5),P2M(0x0b6),P2M(0x0b7) + .quad P2M(0x0b8),P2M(0x0b9),P2M(0x0ba),P2M(0x0bb),P2M(0x0bc),P2M(0x0bd),P2M(0x0be),P2M(0x0bf) + .quad P2M(0x0c0),P2M(0x0c1),P2M(0x0c2),P2M(0x0c3),P2M(0x0c4),P2M(0x0c5),P2M(0x0c6),P2M(0x0c7) + .quad P2M(0x0c8),P2M(0x0c9),P2M(0x0ca),P2M(0x0cb),P2M(0x0cc),P2M(0x0cd),P2M(0x0ce),P2M(0x0cf) + .quad P2M(0x0d0),P2M(0x0d1),P2M(0x0d2),P2M(0x0d3),P2M(0x0d4),P2M(0x0d5),P2M(0x0d6),P2M(0x0d7) + .quad P2M(0x0d8),P2M(0x0d9),P2M(0x0da),P2M(0x0db),P2M(0x0dc),P2M(0x0dd),P2M(0x0de),P2M(0x0df) + .quad P2M(0x0e0),P2M(0x0e1),P2M(0x0e2),P2M(0x0e3),P2M(0x0e4),P2M(0x0e5),P2M(0x0e6),P2M(0x0e7) + .quad P2M(0x0e8),P2M(0x0e9),P2M(0x0ea),P2M(0x0eb),P2M(0x0ec),P2M(0x0ed),P2M(0x0ee),P2M(0x0ef) + .quad P2M(0x0f0),P2M(0x0f1),P2M(0x0f2),P2M(0x0f3),P2M(0x0f4),P2M(0x0f5),P2M(0x0f6),P2M(0x0f7) + .quad P2M(0x0f8),P2M(0x0f9),P2M(0x0fa),P2M(0x0fb),P2M(0x0fc),P2M(0x0fd),P2M(0x0fe),P2M(0x0ff) + .quad P2M(0x100),P2M(0x101),P2M(0x102),P2M(0x103),P2M(0x104),P2M(0x105),P2M(0x106),P2M(0x107) + .quad P2M(0x108),P2M(0x109),P2M(0x10a),P2M(0x10b),P2M(0x10c),P2M(0x10d),P2M(0x10e),P2M(0x10f) + .quad P2M(0x110),P2M(0x111),P2M(0x112),P2M(0x113),P2M(0x114),P2M(0x115),P2M(0x116),P2M(0x117) + .quad P2M(0x118),P2M(0x119),P2M(0x11a),P2M(0x11b),P2M(0x11c),P2M(0x11d),P2M(0x11e),P2M(0x11f) + .quad P2M(0x120),P2M(0x121),P2M(0x122),P2M(0x123),P2M(0x124),P2M(0x125),P2M(0x126),P2M(0x127) + .quad P2M(0x128),P2M(0x129),P2M(0x12a),P2M(0x12b),P2M(0x12c),P2M(0x12d),P2M(0x12e),P2M(0x12f) + .quad P2M(0x130),P2M(0x131),P2M(0x132),P2M(0x133),P2M(0x134),P2M(0x135),P2M(0x136),P2M(0x137) + .quad P2M(0x138),P2M(0x139),P2M(0x13a),P2M(0x13b),P2M(0x13c),P2M(0x13d),P2M(0x13e),P2M(0x13f) + .quad P2M(0x140),P2M(0x141),P2M(0x142),P2M(0x143),P2M(0x144),P2M(0x145),P2M(0x146),P2M(0x147) + .quad P2M(0x148),P2M(0x149),P2M(0x14a),P2M(0x14b),P2M(0x14c),P2M(0x14d),P2M(0x14e),P2M(0x14f) + .quad P2M(0x150),P2M(0x151),P2M(0x152),P2M(0x153),P2M(0x154),P2M(0x155),P2M(0x156),P2M(0x157) + .quad P2M(0x158),P2M(0x159),P2M(0x15a),P2M(0x15b),P2M(0x15c),P2M(0x15d),P2M(0x15e),P2M(0x15f) + .quad P2M(0x160),P2M(0x161),P2M(0x162),P2M(0x163),P2M(0x164),P2M(0x165),P2M(0x166),P2M(0x167) + .quad P2M(0x168),P2M(0x169),P2M(0x16a),P2M(0x16b),P2M(0x16c),P2M(0x16d),P2M(0x16e),P2M(0x16f) + .quad P2M(0x170),P2M(0x171),P2M(0x172),P2M(0x173),P2M(0x174),P2M(0x175),P2M(0x176),P2M(0x177) + .quad P2M(0x178),P2M(0x179),P2M(0x17a),P2M(0x17b),P2M(0x17c),P2M(0x17d),P2M(0x17e),P2M(0x17f) + .quad P2M(0x180),P2M(0x181),P2M(0x182),P2M(0x183),P2M(0x184),P2M(0x185),P2M(0x186),P2M(0x187) + .quad P2M(0x188),P2M(0x189),P2M(0x18a),P2M(0x18b),P2M(0x18c),P2M(0x18d),P2M(0x18e),P2M(0x18f) + .quad P2M(0x190),P2M(0x191),P2M(0x192),P2M(0x193),P2M(0x194),P2M(0x195),P2M(0x196),P2M(0x197) + .quad P2M(0x198),P2M(0x199),P2M(0x19a),P2M(0x19b),P2M(0x19c),P2M(0x19d),P2M(0x19e),P2M(0x19f) + .quad P2M(0x1a0),P2M(0x1a1),P2M(0x1a2),P2M(0x1a3),P2M(0x1a4),P2M(0x1a5),P2M(0x1a6),P2M(0x1a7) + .quad P2M(0x1a8),P2M(0x1a9),P2M(0x1aa),P2M(0x1ab),P2M(0x1ac),P2M(0x1ad),P2M(0x1ae),P2M(0x1af) + .quad P2M(0x1b0),P2M(0x1b1),P2M(0x1b2),P2M(0x1b3),P2M(0x1b4),P2M(0x1b5),P2M(0x1b6),P2M(0x1b7) + .quad P2M(0x1b8),P2M(0x1b9),P2M(0x1ba),P2M(0x1bb),P2M(0x1bc),P2M(0x1bd),P2M(0x1be),P2M(0x1bf) + .quad P2M(0x1c0),P2M(0x1c1),P2M(0x1c2),P2M(0x1c3),P2M(0x1c4),P2M(0x1c5),P2M(0x1c6),P2M(0x1c7) + .quad P2M(0x1c8),P2M(0x1c9),P2M(0x1ca),P2M(0x1cb),P2M(0x1cc),P2M(0x1cd),P2M(0x1ce),P2M(0x1cf) + .quad P2M(0x1d0),P2M(0x1d1),P2M(0x1d2),P2M(0x1d3),P2M(0x1d4),P2M(0x1d5),P2M(0x1d6),P2M(0x1d7) + .quad P2M(0x1d8),P2M(0x1d9),P2M(0x1da),P2M(0x1db),P2M(0x1dc),P2M(0x1dd),P2M(0x1de),P2M(0x1df) + .quad P2M(0x1e0),P2M(0x1e1),P2M(0x1e2),P2M(0x1e3),P2M(0x1e4),P2M(0x1e5),P2M(0x1e6),P2M(0x1e7) + .quad P2M(0x1e8),P2M(0x1e9),P2M(0x1ea),P2M(0x1eb),P2M(0x1ec),P2M(0x1ed),P2M(0x1ee),P2M(0x1ef) + .quad P2M(0x1f0),P2M(0x1f1),P2M(0x1f2),P2M(0x1f3),P2M(0x1f4),P2M(0x1f5),P2M(0x1f6),P2M(0x1f7) + .quad P2M(0x1f8),P2M(0x1f9),P2M(0x1fa),P2M(0x1fb),P2M(0x1fc),P2M(0x1fd),P2M(0x1fe),P2M(0x1ff) + +pml3: + .quad pml2 + 5 // PTE(pml2) +.align 4096 +pml4: + .quad pml3 + 5 // PTE(pml3) +#endif +#endif // someday diff --git a/src/arch/x86/lib/paging.S b/src/arch/x86/lib/paging.S new file mode 100644 index 0000000..71d3b36 --- /dev/null +++ b/src/arch/x86/lib/paging.S @@ -0,0 +1,58 @@ +#include <cpu/x86/cr.h> + + jmp code + +#include "pagetables.S" + +code: + movl $PageMapLevel2, %ecx /* load address of page directory */ + movl %ecx, %cr3 + jmp 1f +1: + movl %cr4, %edx + orl $CR4_PSE, %edx /* 4m pages */ + movl %edx, %cr4 + + movl %cr0, %edx + orl $CR0_PG, %edx + + movl $paging32, %ecx + movl %edx, %cr0 + jmp *%ecx + +/* if we get here, we're in paged 32-bit mode */ +paging32: +#if 0 // someday +#if CONFIG_ARCH_X86_64 + movl %cr4, %eax + andl $~Pse, %eax /* Page Size */ + orl $(Pge|Pae), %eax /* Page Global, Phys. Address */ + movl %eax, %cr4 + + movl $Efer, %ecx /* Extended Feature Enable */ + rdmsr + orl $Lme, %eax /* Long Mode Enable */ + wrmsr + + movl %cr0, %dx + andl $~(Cd|Nw|Ts|Mp), %edx + orl $(Pg|Wp), %edx /* Enable Paging */ + movl %edx, %cr0 + + jmp paging64 + +.code64 +paging64: + + movq gdt64, %RX + movl (%RX), %gdtr + + XORQ %edx, %edx + movw %edx, %ds /* not used in long mode */ + movw %edx, %es /* not used in long mode */ + movw %edx, %fs + movw %edx, %gs + movw %edx, %ss /* not used in long mode */ + +#endif +#endif //someday

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Patch merged into coreboot/master: d78ff54 hp/pavilion_m6_1035dx: Sanitize #includes
by gerrit＠coreboot.org 03 Apr '14

03 Apr '14

the following patch was just integrated into master: commit d78ff54110c6216a1800fc2f62cf85701a171587 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Mar 28 14:48:13 2014 -0500 hp/pavilion_m6_1035dx: Sanitize #includes There were a number of things wrong with the includes. First, The includes did not use paths to AGESA files, thus relying on the compiler include paths to find the correct file. This made it unclear where the file included was located, and whether it was local, under vendorcode, or under a different directory. Instead, use full paths for each non-local include. Second, the local includes were mixed with the rest, making it unclear which file is local and which one is not. Keep the local includes at the top. This also prevents us from polluting the namespace of local headers, with library definitions, and allows us to catch if we missed an otherwise needed external header. Thirdly, alphabetize the order of includes where possible. Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5412 for details. -gerrit

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Patch merged into coreboot/master: 5822332 lenovo/x60: Remove duplicate console_init()
by gerrit＠coreboot.org 03 Apr '14

03 Apr '14

the following patch was just integrated into master: commit 5822332b263571e1a81d4d349bc67a056148d7df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 31 00:09:23 2014 +0300 lenovo/x60: Remove duplicate console_init() For romstage, console_init() was called twice. The one in dock_connect() should have done only UART programming and not touch CBMEM console and/or USBDEBUG when those are enabled. Second case where dock_connect() is called is in SMI handler. If DEBUG_SMI is not enabled, console_init() does nothing in SMM. If DEBUG_SMI is enabled, console_init() is already called every time when enterining SMM. Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5433 for details. -gerrit

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Patch set updated for coreboot: d3d5653 cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded value
by Patrick Georgi 03 Apr '14

03 Apr '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5431 -gerrit commit d3d56538c386b11550279ee85a65bf885b242e2b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 30 18:53:12 2014 +0200 cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded value Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 8f0abce..dd02f6c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -160,7 +160,7 @@ CAR_FAM10_out: #else #error "bad MMCONF_BUS_NUMBER value" #endif - movl $(0xc0010058), %ecx + movl $MSR_MCFG_BASE, %ecx wrmsr #endif

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Patch merged into coreboot/master: 9a10b32 amd/agesa/s3_resume: Make compiler agnostic.
by gerrit＠coreboot.org 03 Apr '14

03 Apr '14

the following patch was just integrated into master: commit 9a10b32aa8198865e9eb1dd680aea448068d673d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 30 22:28:26 2014 +1100 amd/agesa/s3_resume: Make compiler agnostic. Clang does not like inline functions defined in C files with prototypes in headers. Rather Clang expects inline function bodies to be in headers if they are to be used out of scope. Since inline is purely advisory to the compiler, drop its usage here. Change-Id: I08a7a3d2cdf841ffbab10c017c75917768aac209 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5429 for details. -gerrit

1 0

Patch set updated for coreboot: dd74c9f superio/winbond/w83977f: Avoid .c includes
by Edward O'Callaghan 03 Apr '14

03 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5447 -gerrit commit dd74c9f8837956a797fe2ded13513f02c980b6b3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 03:29:22 2014 +1100 superio/winbond/w83977f: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I97f14306b2c269b99d60327a6f9869de6a7d7cc3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advantech/pcm-5820/romstage.c | 2 +- src/superio/winbond/w83977f/Makefile.inc | 2 +- src/superio/winbond/w83977f/early_serial.c | 3 ++- src/superio/winbond/w83977f/w83977f.h | 4 +++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index b710aad..1262300 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -25,7 +25,7 @@ #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977f/early_serial.c" +#include <superio/winbond/w83977f/w83977f.h> #include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) diff --git a/src/superio/winbond/w83977f/Makefile.inc b/src/superio/winbond/w83977f/Makefile.inc index e52c09d..60edac9 100644 --- a/src/superio/winbond/w83977f/Makefile.inc +++ b/src/superio/winbond/w83977f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83977F) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83977F) += superio.c - diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..c412449 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "w83977f.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -34,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +void w83977f_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977f/w83977f.h b/src/superio/winbond/w83977f/w83977f.h index f2b68ed..44c6a4a 100644 --- a/src/superio/winbond/w83977f/w83977f.h +++ b/src/superio/winbond/w83977f/w83977f.h @@ -31,4 +31,6 @@ #define W83977F_GPIO1 7 /* General Purpose I/O 1 */ #define W83977F_GPIO2 8 /* General Purpose I/O 2 */ -#endif +void w83977f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_W83977F_W83977F_H */

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Patch set updated for coreboot: d74b6b4 superio/nuvoton/nct5104d: Avoid .c includes
by Edward O'Callaghan 03 Apr '14

03 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5446 -gerrit commit d74b6b4803a1c95cef2476722fb6203571abf034 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 03:19:41 2014 +1100 superio/nuvoton/nct5104d: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/nuvoton/nct5104d/Makefile.inc | 1 - src/superio/nuvoton/nct5104d/early_init.c | 5 ++--- src/superio/nuvoton/nct5104d/nct5104d.h | 4 +++- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc index b9345aa..7c97d05 100644 --- a/src/superio/nuvoton/nct5104d/Makefile.inc +++ b/src/superio/nuvoton/nct5104d/Makefile.inc @@ -20,4 +20,3 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c - diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index 9c0cf0f..f3d8990 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -19,8 +19,7 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pnp_def.h> +#include <device/pnp.h> #include "nct5104d.h" static void pnp_enter_extended_mode(device_t dev) @@ -36,7 +35,7 @@ static void pnp_exit_extended_mode(device_t dev) outb(0xaa,port); } -static void nct5104d_enable_serial(device_t dev, u16 iobase) +void nct5104d_enable_serial(device_t dev, u16 iobase) { pnp_enter_extended_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 2f833af..98baf81 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -37,4 +37,6 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -#endif +void nct5104d_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_NUVOTON_NCT5104D_NCT5104D_H */

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coreboot-gerrit April 2014