coreboot-gerrit April 2014

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Patch set updated for coreboot: 3000c61 console: Move newline translation outside console_tx_byte
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5336 -gerrit commit 3000c619cecf29c91e9c341c8cacfdf4b3afd1ad Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 19:03:57 2014 +0200 console: Move newline translation outside console_tx_byte This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 3 --- src/arch/x86/lib/romstage_console.c | 3 --- src/console/console.c | 9 +-------- src/console/printk.c | 12 ++++++++++-- src/cpu/x86/smm/smiutil.c | 3 --- src/include/console/console.h | 15 ++++++++------- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/soc/intel/baytrail/romstage/raminit.c | 2 +- 9 files changed, 22 insertions(+), 29 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index a85f554..599cbc7 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -24,9 +24,6 @@ /* FIXME: need to make console driver more generic */ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index c80cf8c..4971f01 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,9 +26,6 @@ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/console/console.c b/src/console/console.c index 1712877..d5aadf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -48,7 +48,7 @@ void console_tx_flush(void) } } -static void __console_tx_byte(unsigned char byte) +void console_tx_byte(unsigned char byte) { struct console_driver *driver; for(driver = console_drivers; driver < econsole_drivers; driver++) { @@ -56,13 +56,6 @@ static void __console_tx_byte(unsigned char byte) } } -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - __console_tx_byte('\r'); - __console_tx_byte(byte); -} - unsigned char console_rx_byte(void) { struct console_driver *driver; diff --git a/src/console/printk.c b/src/console/printk.c index c61f63e..63d37cc 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -13,6 +13,13 @@ DECLARE_SPIN_LOCK(console_lock) +void do_putchar(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + console_tx_byte(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -30,7 +37,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); + i = vtxprintf(do_putchar, fmt, args); va_end(args); console_tx_flush(); @@ -44,7 +51,8 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); + vtxprintf(do_putchar, fmt, args); console_tx_flush(); } #endif + diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 6e9822e..644cab7 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -29,9 +29,6 @@ void console_tx_flush(void) void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index e7b4253..c184f83 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -62,25 +62,26 @@ void post_log_clear(void); /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ defined(__SMM__) && !CONFIG_DEBUG_SMI || \ (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE -static inline void printk(int LEVEL, const char *fmt, ...); -static inline void printk(int LEVEL, const char *fmt, ...) { - /* Do nothing. */ -} +/* Do nothing. */ +static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void do_putchar(unsigned char byte) {} -#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#else + +int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ do { \ do_printk(LEVEL, fmt, ##args); \ } while(0) -#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#endif #if CONFIG_CHROMEOS /* FIXME: Collision of varargs with AMD headers without guard. */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 316f7fd..1e020f9 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -166,7 +166,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content( diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index bfb4033..61e1545 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -248,7 +248,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 7bcd54f..98d389e 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -55,7 +55,7 @@ static void enable_smbus(void) static void ABI_X86 send_to_console(unsigned char b) { - console_tx_byte(b); + do_putchar(b); } static void print_dram_info(void)

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Patch set updated for coreboot: 754f741 uart: Redefine Kconfig options
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5311 -gerrit commit 754f741896880af2d383b2d465c1ce5610fa5a76 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 17:16:22 2014 +0200 uart: Redefine Kconfig options Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 4 +-- src/arch/x86/lib/romcc_console.c | 6 ++--- src/arch/x86/lib/romstage_console.c | 10 ++----- src/console/Kconfig | 43 +++++++++++++----------------- src/console/uart_console.c | 2 +- src/cpu/allwinner/a10/Kconfig | 2 +- src/cpu/allwinner/a10/Makefile.inc | 12 ++++----- src/cpu/samsung/exynos5250/Kconfig | 4 +-- src/cpu/samsung/exynos5250/Makefile.inc | 6 ++--- src/cpu/samsung/exynos5420/Kconfig | 4 +-- src/cpu/samsung/exynos5420/Makefile.inc | 6 ++--- src/cpu/ti/am335x/Makefile.inc | 7 +++-- src/cpu/x86/smm/smiutil.c | 10 ++----- src/drivers/Makefile.inc | 2 +- src/drivers/oxford/oxpcie/Kconfig | 2 +- src/drivers/oxford/oxpcie/Makefile.inc | 2 +- src/drivers/uart/Kconfig | 15 ++++++++--- src/drivers/uart/Makefile.inc | 13 ++++----- src/lib/coreboot_table.c | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/samsung/lumpy/romstage.c | 4 +-- src/mainboard/samsung/stumpy/romstage.c | 4 +-- src/mainboard/ti/beaglebone/Kconfig | 4 +-- src/superio/via/vt1211/vt1211.c | 2 +- 24 files changed, 79 insertions(+), 89 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 93ea38d..7614531 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -28,7 +28,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) @@ -38,7 +38,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif } diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 66c81db..4bd3ad4 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -30,7 +30,7 @@ */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" #endif @@ -40,7 +40,7 @@ static void __console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K @@ -61,7 +61,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 5e7923e..0337245 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -31,10 +31,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) @@ -53,10 +50,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/console/Kconfig b/src/console/Kconfig index d77bb9e..65fc1aa 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,37 +29,29 @@ config SQUELCH_EARLY_SMP config CONSOLE_SERIAL bool "Serial port console output" default y + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL help - Send coreboot debug output to a serial port (should be one or more of - CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) + Send coreboot debug output to a serial port. -config CONSOLE_SERIAL8250 - bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_IO_MAPPED - default y - help - Send coreboot debug output to an I/O mapped serial port console. + The type of serial port driver selected based on your configuration is + shown on the following menu line. Supporting multiple different types + of UARTs in one build is not supported. -config CONSOLE_SERIAL8250MEM - bool "Serial port console output (memory mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_MEMORY_MAPPED - help - Send coreboot debug output to a memory mapped serial port console. +if CONSOLE_SERIAL + + comment "I/O mapped, 8250-compatible" + depends on DRIVERS_UART_8250IO -config CONSOLE_SERIAL_UART - bool "Serial port console output (device-specific UART)" - depends on CONSOLE_SERIAL + comment "memory mapped, 8250-compatible" + depends on DRIVERS_UART_8250MEM + + comment "device-specific UART" depends on HAVE_UART_SPECIAL - default y - help - Send coreboot debug output to a device-specific serial port console. choice prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO config CONSOLE_SERIAL_COM1 bool "COM1/ttyS0, I/O port 0x3f8" @@ -82,7 +74,7 @@ endchoice config TTYS0_BASE hex - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO default 0x3f8 if CONSOLE_SERIAL_COM1 default 0x2f8 if CONSOLE_SERIAL_COM2 default 0x3e8 if CONSOLE_SERIAL_COM3 @@ -93,7 +85,6 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" @@ -133,7 +124,9 @@ config TTYS0_BAUD config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM + +endif # CONSOLE_SERIAL config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/console/uart_console.c b/src/console/uart_console.c index e2cd6a8..f5535d7 100644 --- a/src/console/uart_console.c +++ b/src/console/uart_console.c @@ -43,7 +43,7 @@ static unsigned char uartmem_rx_byte(void) /* This only relevant with x86 with GDB_STUB enabled.*/ static int uartmem_tst_byte(void) { -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM return uart_can_rx_byte(); #else return 0; diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 72e3630..8512c38 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -76,7 +76,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a86d719..716e463 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -4,8 +4,6 @@ bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += raminit.c bootblock-y += timer.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c romstage-y += cbmem.c @@ -13,8 +11,6 @@ romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c romstage-y += twi.c -romstage-y += uart.c -romstage-y += uart_console.c ramstage-y += bootblock_media.c ramstage-y += cbmem.c @@ -23,8 +19,12 @@ ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += uart.c -ramstage-y += uart_console.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +romstage-y += uart.c uart_console.c +ramstage-y += uart.c uart_console.c +endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 63038c3..9320184 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -91,7 +91,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -117,7 +117,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6d7ae16..3d5b5b4 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index dd35c35..5f78cc5 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -93,7 +93,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -119,7 +119,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 4169a2e..844b835 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..5b10bd8 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,16 +1,19 @@ bootblock-y += dmtimer.c bootblock-y += bootblock_media.c bootblock-y += pinmux.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c -romstage-y += uart.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +romstage-y += uart.c ramstage-y += uart.c +endif $(call add-class,omap-header) diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 3325c32..6e9822e 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,10 +32,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif } @@ -45,10 +42,7 @@ void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL8250 - uart_init(); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #endif diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..148e257 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += parade subdirs-y += realtek subdirs-y += sil subdirs-y += trident -subdirs-y += uart +subdirs-$(CONFIG_DRIVERS_UART) += uart subdirs-y += usb subdirs-y += ics subdirs-y += spi diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..5ad42aa 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n - select HAVE_UART_MEMORY_MAPPED + select DRIVERS_UART_8250MEM help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 1922425..5e3e6e5 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_CONSOLE_SERIAL),y) ramstage-y += oxpcie_early.c oxpcie.c romstage-y += oxpcie_early.c endif diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 5c9a9d1..889c69a 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,10 +1,19 @@ -# This should default to N and be set by SuperI/O drivers that have an UART -config HAVE_UART_IO_MAPPED +config DRIVERS_UART bool + default y if CONSOLE_SERIAL + default n + +config DRIVERS_UART_8250IO + bool "Serial port on SuperIO" depends on !ARCH_ARMV7 + default n if NO_UART_ON_SUPERIO default y if ARCH_X86 -config HAVE_UART_MEMORY_MAPPED +# Select this for mainboard without SuperIO serial port. +config NO_UART_ON_SUPERIO + def_bool n + +config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 415c5bb..286bff2 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,28 +1,25 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c smm-$(CONFIG_DEBUG_SMI) += util.c -endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +# Add the driver, only one can be enabled. The driver files may +# be located in the soc/ or cpu/ directories instead of here. + +ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) romstage-y += uart8250io.c ramstage-y += uart8250io.c smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_DRIVERS_UART_8250MEM),y) romstage-y += uart8250mem.c ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) - ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c ramstage-y += pl011.c endif - -endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e4554d7..8e7f85d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -390,7 +390,7 @@ unsigned long write_coreboot_table( lb_mainboard(head); /* Record the serial ports and consoles */ -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_fill_lb(head); #endif #if CONFIG_CONSOLE_USB diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index edba627..040ed9c 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -50,7 +50,7 @@ config DRAM_SIZE_MB config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x10009000 # Memory map for qemu vexpress-a9: diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9933459..55c1f0a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/msr.h> #include "option_table.h" #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index e5b55b5..3e27a6a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -62,7 +62,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index df7ebeb..c842a5d 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -64,7 +64,7 @@ config CBFS_HEADER_ROM_OFFSET choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -100,7 +100,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x44e09000 if CONSOLE_SERIAL_UART0 default 0x48022000 if CONSOLE_SERIAL_UART1 default 0x48024000 if CONSOLE_SERIAL_UART2 diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 551f6f0..f7a5cd9 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -117,7 +117,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) {

1 0

Patch set updated for coreboot: 0d3d323 console uart: Fill coreboot table entries
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5310 -gerrit commit 0d3d32300294a494b21d9963ee7f444f480a2ef5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 15 01:32:55 2014 +0200 console uart: Fill coreboot table entries Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 23 ++++++++--- src/cpu/samsung/exynos5250/uart.c | 21 ++++++---- src/cpu/samsung/exynos5420/uart.c | 21 ++++++---- src/cpu/ti/am335x/uart.c | 21 ++++++---- src/drivers/oxford/oxpcie/oxpcie_early.c | 12 +++++- src/drivers/uart/pl011.c | 21 ++++++---- src/drivers/uart/uart8250io.c | 22 +++++++++++ src/include/boot/coreboot_tables.h | 4 ++ src/include/console/uart.h | 1 - src/lib/coreboot_table.c | 66 +++++++++----------------------- 10 files changed, 127 insertions(+), 85 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index aea1189..d6b91e7 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -10,6 +10,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/allwinner/a10/uart.h> @@ -43,6 +44,11 @@ unsigned int uart_platform_refclk(void) return 24000000; } +unsigned int uart_platform_base(int idx) +{ + return (unsigned int)get_console_uart_base_addr(); +} + void uart_init(void) { void *uart_base = get_console_uart_base_addr(); @@ -63,14 +69,19 @@ void uart_tx_byte(unsigned char data) a10_uart_tx_blocking(get_console_uart_base_addr(), data); } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) +void uart_tx_flush(void) { - return (uint32_t) get_console_uart_base_addr(); } -#endif -void uart_tx_flush(void) +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) { -} + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 860d020..1dabc09 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -159,13 +160,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = uart_platform_baseptr(0); @@ -189,3 +183,16 @@ void uart_tx_flush(void) struct s5p_uart *uart = uart_platform_baseptr(0); exynos5_uart_tx_flush(uart); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 82b1265..290eb35 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -151,13 +152,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = uart_platform_baseptr(0); @@ -180,3 +174,16 @@ void uart_tx_flush(void) { /* Exynos5250 implements this too. */ } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 09bb96e..858926b 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,6 +20,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -156,13 +157,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct am335x_uart *uart = uart_platform_baseptr(0); @@ -186,3 +180,16 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d7f473e..7de9da6 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -24,7 +24,9 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; @@ -139,9 +141,15 @@ void oxford_remap(u32 new_base) uart1_base = new_base + 0x2000; } -uint32_t uartmem_getbaseaddr(void) +void uart_fill_lb(void *data) { - return uart_platform_base(0); + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index e4bfdc6..41e66fa 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boot/coreboot_tables.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) @@ -25,13 +26,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; -} -#endif - void uart_init(void) { } @@ -50,3 +44,16 @@ unsigned char uart_rx_byte(void) { return 0; } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e4e8b6c..1eebb18 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -23,6 +23,10 @@ #include <trace.h> #include "uart8250reg.h" +#ifndef __ROMCC__ +#include <boot/coreboot_tables.h> +#endif + /* Should support 8250, 16450, 16550, 16550A type UARTs */ /* Nominal values only, good for the range of choices Kconfig offers for @@ -102,6 +106,11 @@ static void uart8250_init(unsigned base_port, unsigned divisor) */ static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; +unsigned int uart_platform_base(int idx) +{ + return bases[idx]; +} + void uart_init(void) { unsigned int div; @@ -129,3 +138,16 @@ void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); +} +#endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index c4ad572..08a89bc 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -340,4 +340,8 @@ unsigned long write_coreboot_table( void fill_lb_gpios(struct lb_gpios *gpios); +void uart_fill_lb(void *data); +void lb_add_serial(struct lb_serial *serial, void *data); +void lb_add_console(uint16_t consoletype, void *data); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index e28b8f6..5650618 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -46,7 +46,6 @@ unsigned char uart_rx_byte(void); int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -uint32_t uartmem_getbaseaddr(void); static inline void *uart_platform_baseptr(int idx) { diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9bfe34f..e4554d7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -102,43 +102,22 @@ static struct lb_memory *lb_memory(struct lb_header *header) return mem; } -static struct lb_serial *lb_serial(struct lb_header *header) +void lb_add_serial(struct lb_serial *new_serial, void *data) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; + struct lb_header *header = (struct lb_header *)data; struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; + + serial = (struct lb_serial *)lb_new_record(header); serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif + serial->type = new_serial->type; + serial->baseaddr = new_serial->baseaddr; + serial->baud = new_serial->baud; } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_SERIAL_UART || CONFIG_CONSOLE_USB -static void add_console(struct lb_header *header, u16 consoletype) +void lb_add_console(uint16_t consoletype, void *data) { + struct lb_header *header = (struct lb_header *)data; struct lb_console *console; console = (struct lb_console *)lb_new_record(header); @@ -146,20 +125,6 @@ static void add_console(struct lb_header *header, u16 consoletype) console->size = sizeof(*console); console->type = consoletype; } -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_USB - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} static void lb_framebuffer(struct lb_header *header) { @@ -423,10 +388,15 @@ unsigned long write_coreboot_table( /* Record our motherboard */ lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); + + /* Record the serial ports and consoles */ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + uart_fill_lb(head); +#endif +#if CONFIG_CONSOLE_USB + lb_add_console(LB_TAG_CONSOLE_EHCI, head); +#endif + /* Record our various random string information */ lb_strings(head); /* Record our framebuffer */

1 0

Patch set updated for coreboot: d5d79d9 console: Drop driver list in ramstage
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5337 -gerrit commit d5d79d97e2a35726de370839ed6a2dbebcf187ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 3 17:04:22 2014 +0200 console: Drop driver list in ramstage This framework was only available in ramstage. So we had to define console output functions separately for bootblock, romstage and SMM. Follow-up patches will re-enable all the consoles removed here, in a more flexible fashion, and with less lines-of-code and copy-paste. Also the driver list is not in a well-defined order and some of the loops could exit without visiting all drivers. NOTE: This build has no console in ramstage. Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/coreboot_ram.ld | 4 --- src/arch/x86/coreboot_ram.ld | 4 --- src/console/Makefile.inc | 8 ----- src/console/cbmem_console.c | 36 -------------------- src/console/console.c | 65 +++++-------------------------------- src/console/ne2k_console.c | 37 --------------------- src/console/qemu_debugcon_console.c | 37 --------------------- src/console/spkmodem_console.c | 46 -------------------------- src/console/uart_console.c | 59 --------------------------------- src/console/usbdebug_console.c | 56 -------------------------------- src/drivers/uart/uart8250io.c | 5 --- src/drivers/uart/uart8250mem.c | 8 ----- src/include/console/console.h | 18 ---------- src/include/console/uart.h | 1 - src/lib/rmodule.ld | 4 --- 15 files changed, 9 insertions(+), 379 deletions(-) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 38eaca3..452d2d7 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -56,10 +56,6 @@ SECTIONS .rodata : { _rodata = .; . = ALIGN(4); - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ; diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld index ea32837..1d1143c 100644 --- a/src/arch/x86/coreboot_ram.ld +++ b/src/arch/x86/coreboot_ram.ld @@ -54,10 +54,6 @@ SECTIONS /* If any changes are made to the driver start/symbols or the * section names the equivalent changes need to made to * rmodule.ld. */ - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ; diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index ef917da..d59e44e 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -15,14 +15,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c -ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c -ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c -ramstage-$(CONFIG_CONSOLE_USB) += usbdebug_console.c -ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c -ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c -ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c - - $(obj)/console/init.ramstage.o : $(obj)/build.h $(obj)/console/init.romstage.o : $(obj)/build.h $(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c deleted file mode 100644 index 870ce2f..0000000 --- a/src/console/cbmem_console.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> - -static void cbmemc_init_(void) -{ - cbmemc_init(); -} - -static void cbmemc_tx_byte_(unsigned char data) -{ - cbmemc_tx_byte(data); -} - -static const struct console_driver cbmem_console __console = { - .init = cbmemc_init_, - .tx_byte = cbmemc_tx_byte_, -}; diff --git a/src/console/console.c b/src/console/console.c index d5aadf6..2f4eb5c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,62 +24,6 @@ #include <console/ne2k.h> #include <console/spkmodem.h> -#ifndef __PRE_RAM__ - -/* initialize the console */ -void console_hw_init(void) -{ - struct console_driver *driver; - - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->init) - continue; - driver->init(); - } -} - -void console_tx_flush(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->tx_flush) - continue; - driver->tx_flush(); - } -} - -void console_tx_byte(unsigned char byte) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - driver->tx_byte(byte); - } -} - -unsigned char console_rx_byte(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (driver->tst_byte) - break; - } - if (driver == econsole_drivers) - return 0; - while (!driver->tst_byte()); - return driver->rx_byte(); -} - -int console_tst_byte(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) - if (driver->tst_byte) - return driver->tst_byte(); - return 0; -} - -#else // __PRE_RAM__ ^^^ NOT defined vvv defined - void console_hw_init(void) { #if CONFIG_CONSOLE_SERIAL @@ -98,4 +42,13 @@ void console_hw_init(void) usbdebug_init(); #endif } + +#ifndef __PRE_RAM__ +void console_tx_byte(unsigned char byte) +{ +} + +void console_tx_flush(void) +{ +} #endif diff --git a/src/console/ne2k_console.c b/src/console/ne2k_console.c deleted file mode 100644 index ffbf0c6..0000000 --- a/src/console/ne2k_console.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/ne2k.h> - -static void ne2k_tx_byte(unsigned char data) -{ - ne2k_append_data(&data, 1, CONFIG_CONSOLE_NE2K_IO_PORT); -} - -static void ne2k_tx_flush(void) -{ - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -} - -static const struct console_driver ne2k_console __console = { - .tx_byte = ne2k_tx_byte, - .tx_flush = ne2k_tx_flush, -}; diff --git a/src/console/qemu_debugcon_console.c b/src/console/qemu_debugcon_console.c deleted file mode 100644 index d7a53a2..0000000 --- a/src/console/qemu_debugcon_console.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Red Hat Inc. - * Written by Gerd Hoffmann <kraxel(a)redhat.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/qemu_debugcon.h> - -static void debugcon_init(void) -{ - qemu_debugcon_init(); -} - -static void debugcon_tx_byte(unsigned char data) -{ - qemu_debugcon_tx_byte(data); -} - -static const struct console_driver debugcon_console __console = { - .init = debugcon_init, - .tx_byte = debugcon_tx_byte, -}; diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c deleted file mode 100644 index 814a1ac..0000000 --- a/src/console/spkmodem_console.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/spkmodem.h> - -static void spkmodem_tx_flush(void) -{ -} - -static unsigned char spkmodem_rx_byte(void) -{ - return 0; -} - -static int spkmodem_tst_byte(void) -{ - return 0; -} - - -static const struct console_driver spkmodem_console __console = { - .init = spkmodem_init, - .tx_byte = spkmodem_tx_byte, - .tx_flush = spkmodem_tx_flush, - .rx_byte = spkmodem_rx_byte, - .tst_byte = spkmodem_tst_byte, -}; - diff --git a/src/console/uart_console.c b/src/console/uart_console.c deleted file mode 100644 index f5535d7..0000000 --- a/src/console/uart_console.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void uartmem_init(void) -{ - uart_init(); -} - -static void uartmem_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void uartmem_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char uartmem_rx_byte(void) -{ - return uart_rx_byte(); -} - -/* This only relevant with x86 with GDB_STUB enabled.*/ -static int uartmem_tst_byte(void) -{ -#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM - return uart_can_rx_byte(); -#else - return 0; -#endif -} - -static const struct console_driver uart_console __console = { - .init = uartmem_init, - .tx_byte = uartmem_tx_byte, - .tx_flush = uartmem_tx_flush, - .rx_byte = uartmem_rx_byte, - .tst_byte = uartmem_tst_byte, -}; diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c deleted file mode 100644 index 8331473..0000000 --- a/src/console/usbdebug_console.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <string.h> -#include <console/console.h> -#include <console/usb.h> - -static void dbgp_init(void) -{ - usbdebug_init(); -} - -static void dbgp_tx_byte(unsigned char data) -{ - usb_tx_byte(0, data); -} - -static unsigned char dbgp_rx_byte(void) -{ - return usb_rx_byte(0); -} - -static void dbgp_tx_flush(void) -{ - usb_tx_flush(0); -} - -static int dbgp_tst_byte(void) -{ - return usb_can_rx_byte(0); -} - -static const struct console_driver usbdebug_direct_console __console = { - .init = dbgp_init, - .tx_byte = dbgp_tx_byte, - .tx_flush = dbgp_tx_flush, - .rx_byte = dbgp_rx_byte, - .tst_byte = dbgp_tst_byte, -}; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 1eebb18..e1fb39b 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -129,11 +129,6 @@ unsigned char uart_rx_byte(void) return uart8250_rx_byte(bases[0]); } -int uart_can_rx_byte(void) -{ - return uart8250_can_rx_byte(bases[0]); -} - void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 74929f5..5a186f0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -116,14 +116,6 @@ unsigned char uart_rx_byte(void) return uart8250_mem_rx_byte(base); } -int uart_can_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0; - return uart8250_mem_can_rx_byte(base); -} - void uart_tx_flush(void) { u32 base = uart_platform_base(0); diff --git a/src/include/console/console.h b/src/include/console/console.h index c184f83..0ebd1b7 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,24 +24,6 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#ifndef __PRE_RAM__ -unsigned char console_rx_byte(void); -int console_tst_byte(void); -struct console_driver { - void (*init)(void); - void (*tx_byte)(unsigned char byte); - void (*tx_flush)(void); - unsigned char (*rx_byte)(void); - int (*tst_byte)(void); -}; - -#define __console __attribute__((used, __section__ (".rodata.console_drivers"))) - -/* Defined by the linker... */ -extern struct console_driver console_drivers[]; -extern struct console_driver econsole_drivers[]; -#endif - #ifndef __ROMCC__ int console_log_level(int msg_level); void console_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8987d94..05cc432 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -43,7 +43,6 @@ void uart_init(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); unsigned char uart_rx_byte(void); -int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 9222f3b..63b99b3 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -35,10 +35,6 @@ SECTIONS /* The driver sections are to allow linking coreboot's * ramstage with the rmodule linker. Any changes made in * coreboot_ram.ld should be made here as well. */ - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ;

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Patch set updated for coreboot: 784b6b3 OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit 784b6b38d4fa2fa15f924aea4a7bbe96e3e5bbe7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 12 +++- src/device/Kconfig | 29 +++++++++ src/device/Makefile.inc | 1 + src/device/pci_early.c | 104 +++++++++++++++++++++++++++++++ src/drivers/oxford/oxpcie/Kconfig | 64 +------------------ src/drivers/oxford/oxpcie/oxpcie_early.c | 89 ++++++-------------------- src/include/console/uart.h | 1 - src/include/device/pci.h | 2 + src/mainboard/samsung/lumpy/Kconfig | 16 +++++ 9 files changed, 183 insertions(+), 135 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 9e9e4e2..348264d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -28,6 +28,11 @@ #include <arch/hlt.h> #include <arch/io.h> +#if CONFIG_EARLY_PCI_BRIDGE +/* FIXME: ROMCC chokes on PCI headers. */ +#include <device/pci.h> +#endif + #ifndef __PRE_RAM__ #include <string.h> #include <types.h> @@ -40,6 +45,9 @@ void console_init(void) if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); +#endif for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -101,8 +109,8 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_DRIVERS_OXFORD_OXPCIE - oxford_init(); +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); #endif #if CONFIG_CONSOLE_SERIAL uart_init(); diff --git a/src/device/Kconfig b/src/device/Kconfig index eaa0c04..932b4de 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -237,6 +237,35 @@ config PCIEXP_ASPM config PCI_BUS_SEGN_BITS int default 0 + +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +endif # EARLY_PCI_BRIDGE + endmenu menu "VGA BIOS" diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index ce412b7..bd41b12 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -11,6 +11,7 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c romstage-y += device_romstage.c diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..e31287e 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,9 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <delay.h> + +#ifdef __PRE_RAM__ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) { @@ -66,3 +73,100 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } +#endif + + +#if CONFIG_EARLY_PCI_BRIDGE + +static void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +{ + u16 reg16; + + /* Disable MMIO window behind the bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); + + if (!size) + return; + + /* Enable MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); + + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} + +void pci_early_bridge_init(void) +{ + int timeout, ret = -1; + + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + /* Secondary bus number is mostly irrelevant as we disable + * configuration transactions right after the probe. + */ + u8 secondary = 15; + u8 dev = 0; + u32 mmio_base = CONFIG_EARLY_PCI_MMIO_BASE; + + /* Enable configuration and MMIO over bridge. */ + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, secondary); + pci_bridge_set_mmio(p2p_bridge, mmio_base, 0x4000); + + for (timeout = 20000; timeout; timeout--) { + u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); + if (id != 0 && id != 0xffffffff && id != 0xffff0001) + break; + udelay(10); + } + + if (timeout != 0) + ret = pci_early_device_probe(secondary, dev, mmio_base); + + /* Disable MMIO window if we found no suitable device. */ + if (ret) + pci_bridge_set_mmio(p2p_bridge, 0, 0); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Thus early device cannot reliably use config + * transactions from here on, so we may as well disable them. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} +#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 5ad42aa..c2ea7b6 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 7de9da6..b81fa89 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -23,101 +23,53 @@ #include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> -#include <delay.h> #include <boot/coreboot_tables.h> #include <console/uart.h> #include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -157,8 +109,3 @@ unsigned int uart_platform_refclk(void) { return 62500000; } - -void oxford_init(void) -{ - oxpcie_init_bridge(); -} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 5650618..8987d94 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -52,7 +52,6 @@ static inline void *uart_platform_baseptr(int idx) return (void *)uart_platform_base(idx); } -void oxford_init(void); void oxford_remap(unsigned int new_base); #endif /* CONSOLE_UART_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..f729c27 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -102,6 +102,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); +void pci_early_bridge_init(void); +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); #endif /* CONFIG_PCI */ diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 032b4b5..500427a 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -46,4 +46,20 @@ config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +endif + endif # BOARD_SAMSUNG_LUMPY

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Patch set updated for coreboot: 0e38787 build rules: Identify build stage with simple variables
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5410 -gerrit commit 0e387874aef9a0475f4380f0b0a7f50720bb2362 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 26 15:19:04 2014 +0200 build rules: Identify build stage with simple variables Provide simple environment variables telling which stage of boot is being built. Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/rules.h | 23 +++++++++++++++++++++++ src/arch/x86/Makefile.inc | 4 ++-- src/arch/x86/include/arch/rules.h | 29 +++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h index a790365..de68f04 100644 --- a/src/arch/armv7/include/arch/rules.h +++ b/src/arch/armv7/include/arch/rules.h @@ -19,6 +19,29 @@ #ifndef _ARCH_RULES_H #define _ARCH_RULES_H +/* Useful helpers to tell whether the code is executing in bootblock, + * romstage, ramstage or SMM. + */ + +#if defined(__BOOT_BLOCK__) +#define ENV_BOOTBLOCK 1 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 + +#elif defined(__PRE_RAM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 1 +#define ENV_RAMSTAGE 0 + +#else +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 1 +#endif + +/* SMM not implemented on ARM. */ +#define ENV_SMM 0 + /* For romstage and ramstage always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. * diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3b17ce3..a0adf5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -368,9 +368,9 @@ endif bootblock_inc += $(objgenerated)/bootblock.inc bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S -bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ +bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ +bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ endif $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h index 4b84677..1ed1f1f 100644 --- a/src/arch/x86/include/arch/rules.h +++ b/src/arch/x86/include/arch/rules.h @@ -19,6 +19,35 @@ #ifndef _ARCH_RULES_H #define _ARCH_RULES_H +/* Useful helpers to tell whether the code is executing in bootblock, + * romstage, ramstage or SMM. + */ + +#if defined(__BOOT_BLOCK__) +#define ENV_BOOTBLOCK 1 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 + +#elif defined(__PRE_RAM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 1 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 + +#elif defined(__SMM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 1 +#else + +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 1 +#define ENV_SMM 0 +#endif + /* For romstage and ramstage always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. *

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Patch set updated for coreboot: 7c84d41 uart: Support multiple ports
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5342 -gerrit commit 7c84d417c68cd15baadf7355bbc870c8e68ea07a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 14 22:28:29 2014 +0200 uart: Support multiple ports The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 38 +++++------------- src/cpu/allwinner/a10/Kconfig | 49 ++---------------------- src/cpu/allwinner/a10/uart_console.c | 48 +++++++---------------- src/cpu/samsung/exynos5250/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5250/uart.c | 23 ++++++----- src/cpu/samsung/exynos5420/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5420/uart.c | 21 +++++----- src/cpu/ti/am335x/uart.c | 24 +++++++----- src/drivers/uart/oxpcie_early.c | 2 +- src/drivers/uart/pl011.c | 10 ++--- src/drivers/uart/uart8250io.c | 18 ++++----- src/drivers/uart/uart8250mem.c | 16 ++++---- src/include/console/uart.h | 14 +++---- src/mainboard/emulation/qemu-armv7/Kconfig | 5 --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 ++ src/mainboard/ti/beaglebone/Kconfig | 51 ++----------------------- 16 files changed, 110 insertions(+), 291 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 65fc1aa..703e5c7 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -48,39 +48,21 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL -choice - prompt "Serial port for 8250" - default CONSOLE_SERIAL_COM1 - depends on DRIVERS_UART_8250IO - -config CONSOLE_SERIAL_COM1 - bool "COM1/ttyS0, I/O port 0x3f8" - help - Serial console on COM1/ttyS0 at I/O port 0x3f8. -config CONSOLE_SERIAL_COM2 - bool "COM2/ttyS1, I/O port 0x2f8" - help - Serial console on COM2/ttyS1 at I/O port 0x2f8. -config CONSOLE_SERIAL_COM3 - bool "COM3/ttyS2, I/O port 0x3e8" - help - Serial console on COM3/ttyS2 at I/O port 0x3e8. -config CONSOLE_SERIAL_COM4 - bool "COM4/ttyS3, I/O port 0x2e8" - help - Serial console on COM4/ttyS3 at I/O port 0x2e8. - -endchoice +config UART_FOR_CONSOLE + prompt "Index for UART port to use for console" + default 0 +# FIXME: Early programming in romstage is incorrect as we should +# program different LDN to actually change the physical port. config TTYS0_BASE hex depends on DRIVERS_UART_8250IO - default 0x3f8 if CONSOLE_SERIAL_COM1 - default 0x2f8 if CONSOLE_SERIAL_COM2 - default 0x3e8 if CONSOLE_SERIAL_COM3 - default 0x2e8 if CONSOLE_SERIAL_COM4 + default 0x3f8 if UART_FOR_CONSOLE = 0 + default 0x2f8 if UART_FOR_CONSOLE = 1 + default 0x3e8 if UART_FOR_CONSOLE = 2 + default 0x2e8 if UART_FOR_CONSOLE = 3 help - Map the COM port names to the respective I/O port. + Map the COM port number to the respective I/O port. choice prompt "Baud rate" diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 8512c38..3d12acd 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -73,51 +73,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -config CONSOLE_SERIAL_UART6 - bool "UART6" - help - Serial console on UART6 - -config CONSOLE_SERIAL_UART7 - bool "UART7" - help - Serial console on UART7 - -endchoice +config UART_FOR_CONSOLE + int + default 0 endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index d6b91e7..bb5f41c 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -14,28 +14,13 @@ #include <cpu/allwinner/a10/uart.h> -static void *get_console_uart_base_addr(void) +unsigned int uart_platform_base(int idx) { - /* This big block gets compiled to a constant, not a function call */ - if (CONFIG_CONSOLE_SERIAL_UART0) - return (void *)A1X_UART0_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART1) - return (void *)A1X_UART1_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART2) - return (void *)A1X_UART2_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART3) - return (void *)A1X_UART3_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART4) - return (void *)A1X_UART4_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART5) - return (void *)A1X_UART5_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART6) - return (void *)A1X_UART6_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART7) - return (void *)A1X_UART7_BASE; - - /* If selection is invalid, default to UART0 */ - return (void *)A1X_UART0_BASE; + /* UART blocks are mapped 0x400 bytes apart */ + if (idx < 8) + return A1X_UART0_BASE + 0x400 * idx; + else + return 0; } /* FIXME: We assume clock is 24MHz, which may not be the case. */ @@ -44,14 +29,9 @@ unsigned int uart_platform_refclk(void) return 24000000; } -unsigned int uart_platform_base(int idx) -{ - return (unsigned int)get_console_uart_base_addr(); -} - -void uart_init(void) +void uart_init(int idx) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = uart_platform_baseptr(idx); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -59,17 +39,17 @@ void uart_init(void) a10_uart_enable_fifos(uart_base); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -78,7 +58,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 9320184..2fda9b3 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,41 +88,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 1dabc09..a73a01a 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -157,30 +157,33 @@ static void exynos5_uart_tx_flush(struct s5p_uart *uart) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); } @@ -189,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 5f78cc5..e46d889 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -90,41 +90,8 @@ config SYS_SDRAM_BASE hex default 0x20000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 290eb35..8fd4dea 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -149,28 +149,31 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { /* Exynos5250 implements this too. */ } @@ -180,7 +183,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 858926b..371e352 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -154,30 +154,36 @@ unsigned int uart_platform_refclk(void) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x44e09000, 0x48022000, 0x48024000, + 0x481a6000, 0x481a8000, 0x481aa000 + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -186,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b81fa89..fd37806 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -97,7 +97,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 41e66fa..d7430b1 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -26,17 +26,17 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -void uart_init(void) +void uart_init(int idx) { } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - unsigned int *uart_base = uart_platform_baseptr(0); + unsigned int *uart_base = uart_platform_baseptr(idx); pl011_uart_tx_byte(uart_base, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -50,7 +50,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e1fb39b..f008e1f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -111,27 +111,27 @@ unsigned int uart_platform_base(int idx) return bases[idx]; } -void uart_init(void) +void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, BAUDRATE_OVERSAMPLE); - uart8250_init(bases[0], div); + uart8250_init(uart_platform_base(idx), div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - uart8250_tx_byte(bases[0], data); + uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return uart8250_rx_byte(bases[0]); + return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - uart8250_tx_flush(bases[0]); + uart8250_tx_flush(uart_platform_base(idx)); } #ifndef __PRE_RAM__ @@ -139,7 +139,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5a186f0..976bcb6 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -89,9 +89,9 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -void uart_init(void) +void uart_init(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; @@ -100,25 +100,25 @@ void uart_init(void) uart8250_mem_init(base, div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_flush(base); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 5e778f0..5a9cce3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -40,10 +40,10 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); -void uart_init(void); -void uart_tx_byte(unsigned char data); -void uart_tx_flush(void); -unsigned char uart_rx_byte(void); +void uart_init(int idx); +void uart_tx_byte(int idx, unsigned char data); +void uart_tx_flush(int idx); +unsigned char uart_rx_byte(int idx); unsigned int uart_platform_base(int idx); @@ -58,9 +58,9 @@ void oxford_remap(unsigned int new_base); (ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_SERIAL_ENABLE__ -static inline void __uart_init(void) { uart_init(); } -static inline void __uart_tx_byte(u8 data) { uart_tx_byte(data); } -static inline void __uart_tx_flush(void) { uart_tx_flush(); } +static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } +static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 040ed9c..6d04216 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -48,11 +48,6 @@ config DRAM_SIZE_MB int default 1024 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x10009000 - # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d15495f..27461bb 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,3 +21,7 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c + +bootblock-y += iomap.c +romstage-y += iomap.c +ramstage-y += iomap.c diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index c842a5d..a24fcde 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -61,54 +61,9 @@ config CBFS_HEADER_ROM_OFFSET hex default 0x10 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x44e09000 if CONSOLE_SERIAL_UART0 - default 0x48022000 if CONSOLE_SERIAL_UART1 - default 0x48024000 if CONSOLE_SERIAL_UART2 - default 0x481a6000 if CONSOLE_SERIAL_UART3 - default 0x481a8000 if CONSOLE_SERIAL_UART4 - default 0x481aa000 if CONSOLE_SERIAL_UART5 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 0 ################################################################# # stuff from smdk5250.h #

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Patch set updated for coreboot: 944db97 console: Add console for GDB
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5343 -gerrit commit 944db975f29a25b8b19dd717a032c6c839e7b4b3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 15:05:28 2014 +0300 console: Add console for GDB Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/c_start.S | 1 + src/arch/x86/lib/exception.c | 13 +++++++++++-- src/console/console.c | 24 ++++++++++++++++++++++++ src/include/console/streams.h | 6 ++++++ src/include/console/uart.h | 8 ++++++++ src/include/console/usb.h | 15 +++++++++++++-- 6 files changed, 63 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index faea22d..675a09c 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -86,6 +86,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT + call gdb_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..f64b2e7 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <console/streams.h> #include <string.h> #if CONFIG_GDB_STUB @@ -217,12 +218,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - console_tx_byte(ch); + gdb_tx_byte(ch); +} + +static inline void stub_flush(void) +{ + gdb_tx_flush(); } static inline int stub_getc(void) { - return console_rx_byte(); + return gdb_rx_byte(); } static int hex(char ch) @@ -322,9 +328,11 @@ static int get_packet(char *buffer) if (checksum != xmitcsum) { stub_putc('-'); /* failed checksum */ + stub_flush(); } else { stub_putc('+'); /* successful transfer */ + stub_flush(); } } } while(checksum != xmitcsum); @@ -353,6 +361,7 @@ static void put_packet(char *buffer) stub_putc('#'); stub_putc(hexchars[checksum >> 4]); stub_putc(hexchars[checksum % 16]); + stub_flush(); } while ((stub_getc() & 0x7f) != '+'); diff --git a/src/console/console.c b/src/console/console.c index cd72596..396ca07 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -54,6 +54,30 @@ void console_tx_flush(void) __usb_tx_flush(); } + +#if CONFIG_GDB_STUB && !defined(__SMM__) +void gdb_hw_init(void) +{ + __gdb_hw_init(); +} + +void gdb_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void gdb_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char gdb_rx_byte(void) +{ + return __gdb_rx_byte(); +} +#endif + + void console_tx_nibble(unsigned nibble) { unsigned char digit; diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 9d4d3fc..fb168da 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,6 +22,12 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* For remote GDB debugging. */ +void gdb_hw_init(void); +void gdb_tx_byte(unsigned char byte); +void gdb_tx_flush(void); +unsigned char gdb_rx_byte(void); + /* Helpers for ROMCC console. */ void console_tx_nibble(unsigned nibble); void console_tx_hex8(unsigned char value); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 5a9cce3..db1109c 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -67,4 +67,12 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif +#if 0 && CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#define CONFIG_UART_FOR_GDB 0 +static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#endif + #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index e64e43e..42887a8 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -34,14 +34,25 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +#define USB_PIPE_FOR_CONSOLE 0 +#define USB_PIPE_FOR_GDB 0 + #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } -static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif +#if 0 && CONFIG_GDB_STUB_USB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#endif + #endif /* _CONSOLE_USB_H_ */

1 0

Patch set updated for coreboot: f3e263d console: Simplify the enable rules
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5341 -gerrit commit f3e263d360f082cf878592233e12ba47e5af8bb9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 26 15:19:04 2014 +0200 console: Simplify the enable rules Consoles on CBMEM and USB have somewhat complex rules and dependencies when they can be active. Use simple variables to test which stage of boot is being built for each console. Change-Id: I2489e7731d07ca7d5dd2ea8b6501c73f05d6edd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 62 ++++++++++--------------------------- src/include/console/cbmem_console.h | 23 +++++++++++--- src/include/console/ne2k.h | 15 +++++++++ src/include/console/qemu_debugcon.h | 11 +++++++ src/include/console/spkmodem.h | 11 +++++++ src/include/console/uart.h | 14 +++++++++ src/include/console/usb.h | 16 ++++++++++ 7 files changed, 102 insertions(+), 50 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index f66cd3f..cd72596 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -27,59 +27,31 @@ void console_hw_init(void) { -#if CONFIG_CONSOLE_SERIAL - uart_init(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_init(); -#endif -#if CONFIG_SPKMODEM - spkmodem_init(); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usbdebug_init(); -#endif -#if CONFIG_CONSOLE_QEMU_DEBUGCON - qemu_debugcon_init(); -#endif + __cbmemc_init(); + __spkmodem_init(); + __qemu_debugcon_init(); + + __uart_init(); + __ne2k_init(); + __usbdebug_init(); } void console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_tx_byte(byte); -#endif -#if CONFIG_SPKMODEM - spkmodem_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_QEMU_DEBUGCON - qemu_debugcon_tx_byte(byte); -#endif + __cbmemc_tx_byte(byte); + __spkmodem_tx_byte(byte); + __qemu_debugcon_tx_byte(byte); + + __uart_tx_byte(byte); + __ne2k_tx_byte(byte); + __usb_tx_byte(byte); } void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_flush(0); -#endif + __uart_tx_flush(); + __ne2k_tx_flush(); + __usb_tx_flush(); } void console_tx_nibble(unsigned nibble) diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 4f4a54f..a7f48c9 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -19,14 +19,27 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +#include <arch/rules.h> +#include <stdint.h> + void cbmemc_init(void); -void cbmemc_reinit(void); void cbmemc_tx_byte(unsigned char data); + +#if CONFIG_CONSOLE_CBMEM +void cbmemc_reinit(void); +#else +static inline void cbmemc_reinit(void) {} +#endif + +#define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ + ((ENV_ROMSTAGE && CONFIG_EARLY_CBMEM_INIT) || ENV_RAMSTAGE) + +#if __CBMEM_CONSOLE_ENABLE__ +static inline void __cbmemc_init(void) { cbmemc_init(); } +static inline void __cbmemc_tx_byte(u8 data) { cbmemc_tx_byte(data); } #else -#define cbmemc_init() -#define cbmemc_reinit() -#define cbmemc_tx_byte(x) +static inline void __cbmemc_init(void) {} +static inline void __cbmemc_tx_byte(u8 data) {} #endif #endif diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index cb3c1ec..508b5e5 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -19,6 +19,10 @@ #ifndef _NE2K_H__ #define _NE2K_H__ + +#include <arch/rules.h> +#include <stdint.h> + void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); @@ -26,4 +30,15 @@ void ne2k_transmit(unsigned int eth_nic_base); #ifndef __ROMCC__ #define ne2k_append_data_byte(d, base) ne2k_append_data(&d, 1, base) #endif + +#if CONFIG_CONSOLE_NE2K && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_tx_byte(u8 data) { ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_tx_flush(void) { ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); } +#else +static inline void __ne2k_init(void) {} +static inline void __ne2k_tx_byte(u8 data) {} +static inline void __ne2k_tx_flush(void) {} +#endif + #endif /* _NE2K_H */ diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 63b1455..8988e9e 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -1,7 +1,18 @@ #ifndef _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_ +#include <arch/rules.h> +#include <stdint.h> + void qemu_debugcon_init(void); void qemu_debugcon_tx_byte(unsigned char data); +#if CONFIG_CONSOLE_QEMU_DEBUGCON && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); } +static inline void __qemu_debugcon_tx_byte(u8 data) { qemu_debugcon_tx_byte(data); } +#else +static inline void __qemu_debugcon_init(void) {} +static inline void __qemu_debugcon_tx_byte(u8 data) {} +#endif + #endif diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index 450dbe8..dbc1843 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -1,7 +1,18 @@ #ifndef SPKMODEM_H #define SPKMODEM_H 1 +#include <arch/rules.h> +#include <stdint.h> + void spkmodem_init(void); void spkmodem_tx_byte(unsigned char c); +#if CONFIG_SPKMODEM && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __spkmodem_init(void) { spkmodem_init(); } +static inline void __spkmodem_tx_byte(u8 data) { spkmodem_tx_byte(data); } +#else +static inline void __spkmodem_init(void) {} +static inline void __spkmodem_tx_byte(u8 data) {} +#endif + #endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 05cc432..5e778f0 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -20,6 +20,7 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H +#include <arch/rules.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for @@ -53,4 +54,17 @@ static inline void *uart_platform_baseptr(int idx) void oxford_remap(unsigned int new_base); +#define __CONSOLE_SERIAL_ENABLE__ CONFIG_CONSOLE_SERIAL && \ + (ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + +#if __CONSOLE_SERIAL_ENABLE__ +static inline void __uart_init(void) { uart_init(); } +static inline void __uart_tx_byte(u8 data) { uart_tx_byte(data); } +static inline void __uart_tx_flush(void) { uart_tx_flush(); } +#else +static inline void __uart_init(void) {} +static inline void __uart_tx_byte(u8 data) {} +static inline void __uart_tx_flush(void) {} +#endif + #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 9591135..e64e43e 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -21,6 +21,9 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ +#include <arch/rules.h> +#include <stdint.h> + int usbdebug_init(void); void usb_tx_byte(int idx, unsigned char data); @@ -28,4 +31,17 @@ void usb_tx_flush(int idx); unsigned char usb_rx_byte(int idx); int usb_can_rx_byte(int idx); +#define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) + +#if __CONSOLE_USB_ENABLE__ +static inline void __usbdebug_init(void) { usbdebug_init(); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +#else +static inline void __usbdebug_init(void) {} +static inline void __usb_tx_byte(u8 data) {} +static inline void __usb_tx_flush(void) {} +#endif + #endif /* _CONSOLE_USB_H_ */

1 0

Patch set updated for coreboot: e5083df console: Refactor uart8250/NE2K
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5330 -gerrit commit e5083dfd1636edbebc84486256bbe0e1717e9e48 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 11:34:38 2014 +0200 console: Refactor uart8250/NE2K Do this for symmetry with romstage_console.c. Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 35 ++++++++++++++++------------------- src/arch/x86/lib/romstage_console.c | 2 +- src/include/console/ne2k.h | 4 ++++ 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index a6e8ecc..0557a52 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -41,6 +41,16 @@ static void __console_tx_byte(unsigned char byte) #endif } +static void __console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL + uart_tx_flush(); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + static void __console_tx_nibble(unsigned nibble) { unsigned char digit; @@ -54,13 +64,8 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_log_level(loglevel)) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_byte(byte); + __console_tx_flush(); } } @@ -69,10 +74,8 @@ static void __console_tx_hex8(int loglevel, unsigned char value) if (console_log_level(loglevel)) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex16(int loglevel, unsigned short value) @@ -82,10 +85,8 @@ static void __console_tx_hex16(int loglevel, unsigned short value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex32(int loglevel, unsigned int value) @@ -99,10 +100,8 @@ static void __console_tx_hex32(int loglevel, unsigned int value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_string(int loglevel, const char *str) @@ -114,9 +113,7 @@ static void __console_tx_string(int loglevel, const char *str) __console_tx_byte('\r'); __console_tx_byte(ch); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_flush(); } } diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4971f01..58742a2 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -33,7 +33,7 @@ void console_tx_byte(unsigned char byte) usb_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K - ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif #if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_tx_byte(byte); diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 62424f1..cb3c1ec 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -22,4 +22,8 @@ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); + +#ifndef __ROMCC__ +#define ne2k_append_data_byte(d, base) ne2k_append_data(&d, 1, base) +#endif #endif /* _NE2K_H */

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coreboot-gerrit April 2014