coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ad14f45 console: Hide global console_loglevel
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5333 -gerrit commit ad14f45e256cc158631ad91a7b01e00fdbd9650b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 14:37:27 2014 +0200 console: Hide global console_loglevel Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 21 +++++++-------------- src/console/init.c | 10 ++++++++-- src/console/printk.c | 3 +-- src/include/console/console.h | 10 +--------- 4 files changed, 17 insertions(+), 27 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 3f8f62f..a6e8ecc 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,18 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <console/loglevel.h> -#include <console/post_codes.h> #include <console/uart.h> #include <console/ne2k.h> -/* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL +/* While in romstage, console loglevel is built-time constant. */ +#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" @@ -60,7 +53,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif @@ -73,7 +66,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) static void __console_tx_hex8(int loglevel, unsigned char value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } @@ -84,7 +77,7 @@ static void __console_tx_hex8(int loglevel, unsigned char value) static void __console_tx_hex16(int loglevel, unsigned short value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 12U) & 0x0fU); __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); @@ -97,7 +90,7 @@ static void __console_tx_hex16(int loglevel, unsigned short value) static void __console_tx_hex32(int loglevel, unsigned int value) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { __console_tx_nibble((value >> 28U) & 0x0fU); __console_tx_nibble((value >> 24U) & 0x0fU); __console_tx_nibble((value >> 20U) & 0x0fU); @@ -114,7 +107,7 @@ static void __console_tx_hex32(int loglevel, unsigned int value) static void __console_tx_string(int loglevel, const char *str) { - if (console_loglevel >= loglevel) { + if (console_log_level(loglevel)) { unsigned char ch; while((ch = *str++) != '\0') { if (ch == '\n') diff --git a/src/console/init.c b/src/console/init.c index c6ceab5..d7c8cc3 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -29,8 +29,14 @@ #include <device/pci.h> #endif -#if !defined(__PRE_RAM__) -int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if !defined(__ROMCC__) +/* While in romstage, console loglevel is built-time constant. */ +static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + +int console_log_level(int msg_level) +{ + return (console_loglevel >= msg_level); +} #endif void console_init(void) diff --git a/src/console/printk.c b/src/console/printk.c index 7ea8c06..fb1194e 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -18,9 +18,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_list args; int i; - if (msg_level > console_loglevel) { + if (!console_log_level(msg_level)) return 0; - } #if CONFIG_SQUELCH_EARLY_SMP && defined(__PRE_RAM__) if (!boot_cpu()) diff --git a/src/include/console/console.h b/src/include/console/console.h index 6d1b01a..aa5273f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -40,18 +40,10 @@ struct console_driver { /* Defined by the linker... */ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[]; - -extern int console_loglevel; -#else -/* __PRE_RAM__ */ -/* Using a global variable can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL #endif #ifndef __ROMCC__ +int console_log_level(int msg_level); void console_init(void); void console_hw_init(void); void console_tx_byte(unsigned char byte);

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Patch set updated for coreboot: 32da062 uart: Prepare to support multiple base addresses
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5309 -gerrit commit 32da062b514d68670bf51635bbb1ce54c68f21e7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 24 20:51:30 2014 +0200 uart: Prepare to support multiple base addresses Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/samsung/exynos5250/uart.c | 50 ++++++++++++++++++--------------------- src/cpu/samsung/exynos5420/uart.c | 44 ++++++++++++++++------------------ src/cpu/ti/am335x/uart.c | 30 +++++++++++------------ src/drivers/uart/pl011.c | 13 ++++++---- src/include/console/uart.h | 7 ++++++ 5 files changed, 74 insertions(+), 70 deletions(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 14d140c..860d020 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. exynos_pinmux_uart3(); @@ -102,12 +96,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -130,14 +123,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -147,49 +138,54 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } -static void exynos5_uart_tx_flush(void) +static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - while (readl(&uart->ufstat) & 0x1ff0000); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = uart_platform_baseptr(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { - exynos5_uart_tx_flush(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index d05adcd..82b1265 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); @@ -99,12 +93,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -127,14 +120,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -144,41 +135,48 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = uart_platform_baseptr(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { + /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 27051ea..09bb96e 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -35,10 +35,8 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) { - struct am335x_uart *uart = (struct am335x_uart *) - CONFIG_CONSOLE_SERIAL_UART_ADDRESS; uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ @@ -131,11 +129,8 @@ static void am335x_uart_init(uint16_t div) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char am335x_uart_rx_byte(void) +static unsigned char am335x_uart_rx_byte(struct am335x_uart *uart) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_RXFIFOE)); return read8(&uart->rhr); @@ -144,11 +139,8 @@ static unsigned char am335x_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void am335x_uart_tx_byte(unsigned char data) +static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_TXFIFOE)); return write8(data, &uart->thr); @@ -159,28 +151,36 @@ unsigned int uart_platform_refclk(void) return 48000000; } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + return uart_platform_base(0); } #endif void uart_init(void) { + struct am335x_uart *uart = uart_platform_baseptr(0); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); + am335x_uart_init(uart, div); } unsigned char uart_rx_byte(void) { - return am335x_uart_rx_byte(); + struct am335x_uart *uart = uart_platform_baseptr(0); + return am335x_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - am335x_uart_tx_byte(data); + struct am335x_uart *uart = uart_platform_baseptr(0); + am335x_uart_tx_byte(uart, data); } void uart_tx_flush(void) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2202de7..e4bfdc6 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -15,12 +15,14 @@ #include <console/uart.h> -static void pl011_uart_tx_byte(unsigned char data) +static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + *uart_base = (unsigned int)data; +} - *uart0_address = (unsigned int)data; +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } #if !defined(__PRE_RAM__) @@ -36,7 +38,8 @@ void uart_init(void) void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + unsigned int *uart_base = uart_platform_baseptr(0); + pl011_uart_tx_byte(uart_base, data); } void uart_tx_flush(void) diff --git a/src/include/console/uart.h b/src/include/console/uart.h index f0371a2..6a1251e 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -48,6 +48,13 @@ int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +#if !defined(__ROMCC__) +static inline void *uart_platform_baseptr(int idx) +{ + return (void *)uart_platform_base(idx); +} +#endif + void oxford_init(void); void oxford_remap(unsigned int new_base);

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Patch set updated for coreboot: a25ea70 console uart: Fill coreboot table entries
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5310 -gerrit commit a25ea709b717b52edc0012a5d502f98ad314f88a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 15 01:32:55 2014 +0200 console uart: Fill coreboot table entries Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 23 ++++++++--- src/cpu/samsung/exynos5250/uart.c | 21 ++++++---- src/cpu/samsung/exynos5420/uart.c | 21 ++++++---- src/cpu/ti/am335x/uart.c | 21 ++++++---- src/drivers/oxford/oxpcie/oxpcie_early.c | 12 +++++- src/drivers/uart/pl011.c | 21 ++++++---- src/drivers/uart/uart8250io.c | 22 +++++++++++ src/include/boot/coreboot_tables.h | 4 ++ src/include/console/uart.h | 1 - src/lib/coreboot_table.c | 66 +++++++++----------------------- 10 files changed, 127 insertions(+), 85 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index aea1189..d6b91e7 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -10,6 +10,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/allwinner/a10/uart.h> @@ -43,6 +44,11 @@ unsigned int uart_platform_refclk(void) return 24000000; } +unsigned int uart_platform_base(int idx) +{ + return (unsigned int)get_console_uart_base_addr(); +} + void uart_init(void) { void *uart_base = get_console_uart_base_addr(); @@ -63,14 +69,19 @@ void uart_tx_byte(unsigned char data) a10_uart_tx_blocking(get_console_uart_base_addr(), data); } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) +void uart_tx_flush(void) { - return (uint32_t) get_console_uart_base_addr(); } -#endif -void uart_tx_flush(void) +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) { -} + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 860d020..1dabc09 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -159,13 +160,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = uart_platform_baseptr(0); @@ -189,3 +183,16 @@ void uart_tx_flush(void) struct s5p_uart *uart = uart_platform_baseptr(0); exynos5_uart_tx_flush(uart); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 82b1265..290eb35 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -151,13 +152,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = uart_platform_baseptr(0); @@ -180,3 +174,16 @@ void uart_tx_flush(void) { /* Exynos5250 implements this too. */ } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 09bb96e..858926b 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,6 +20,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -156,13 +157,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct am335x_uart *uart = uart_platform_baseptr(0); @@ -186,3 +180,16 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d7f473e..7de9da6 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -24,7 +24,9 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; @@ -139,9 +141,15 @@ void oxford_remap(u32 new_base) uart1_base = new_base + 0x2000; } -uint32_t uartmem_getbaseaddr(void) +void uart_fill_lb(void *data) { - return uart_platform_base(0); + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index e4bfdc6..41e66fa 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boot/coreboot_tables.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) @@ -25,13 +26,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; -} -#endif - void uart_init(void) { } @@ -50,3 +44,16 @@ unsigned char uart_rx_byte(void) { return 0; } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e4e8b6c..1eebb18 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -23,6 +23,10 @@ #include <trace.h> #include "uart8250reg.h" +#ifndef __ROMCC__ +#include <boot/coreboot_tables.h> +#endif + /* Should support 8250, 16450, 16550, 16550A type UARTs */ /* Nominal values only, good for the range of choices Kconfig offers for @@ -102,6 +106,11 @@ static void uart8250_init(unsigned base_port, unsigned divisor) */ static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; +unsigned int uart_platform_base(int idx) +{ + return bases[idx]; +} + void uart_init(void) { unsigned int div; @@ -129,3 +138,16 @@ void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); +} +#endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index c4ad572..08a89bc 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -340,4 +340,8 @@ unsigned long write_coreboot_table( void fill_lb_gpios(struct lb_gpios *gpios); +void uart_fill_lb(void *data); +void lb_add_serial(struct lb_serial *serial, void *data); +void lb_add_console(uint16_t consoletype, void *data); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6a1251e..ed922f1 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -46,7 +46,6 @@ unsigned char uart_rx_byte(void); int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -uint32_t uartmem_getbaseaddr(void); #if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9bfe34f..e4554d7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -102,43 +102,22 @@ static struct lb_memory *lb_memory(struct lb_header *header) return mem; } -static struct lb_serial *lb_serial(struct lb_header *header) +void lb_add_serial(struct lb_serial *new_serial, void *data) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; + struct lb_header *header = (struct lb_header *)data; struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; + + serial = (struct lb_serial *)lb_new_record(header); serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif + serial->type = new_serial->type; + serial->baseaddr = new_serial->baseaddr; + serial->baud = new_serial->baud; } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_SERIAL_UART || CONFIG_CONSOLE_USB -static void add_console(struct lb_header *header, u16 consoletype) +void lb_add_console(uint16_t consoletype, void *data) { + struct lb_header *header = (struct lb_header *)data; struct lb_console *console; console = (struct lb_console *)lb_new_record(header); @@ -146,20 +125,6 @@ static void add_console(struct lb_header *header, u16 consoletype) console->size = sizeof(*console); console->type = consoletype; } -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_USB - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} static void lb_framebuffer(struct lb_header *header) { @@ -423,10 +388,15 @@ unsigned long write_coreboot_table( /* Record our motherboard */ lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); + + /* Record the serial ports and consoles */ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + uart_fill_lb(head); +#endif +#if CONFIG_CONSOLE_USB + lb_add_console(LB_TAG_CONSOLE_EHCI, head); +#endif + /* Record our various random string information */ lb_strings(head); /* Record our framebuffer */

1 0

Patch set updated for coreboot: a391f98 uart: Redefine Kconfig options
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5311 -gerrit commit a391f98722c7051fbf3ec29027ce5300d81a2763 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 17:16:22 2014 +0200 uart: Redefine Kconfig options Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 4 +-- src/arch/x86/lib/romcc_console.c | 6 ++--- src/arch/x86/lib/romstage_console.c | 10 ++----- src/console/Kconfig | 43 +++++++++++++----------------- src/console/uart_console.c | 2 +- src/cpu/allwinner/a10/Kconfig | 2 +- src/cpu/allwinner/a10/Makefile.inc | 12 ++++----- src/cpu/samsung/exynos5250/Kconfig | 4 +-- src/cpu/samsung/exynos5250/Makefile.inc | 6 ++--- src/cpu/samsung/exynos5420/Kconfig | 4 +-- src/cpu/samsung/exynos5420/Makefile.inc | 6 ++--- src/cpu/ti/am335x/Makefile.inc | 7 +++-- src/cpu/x86/smm/smiutil.c | 10 ++----- src/drivers/Makefile.inc | 2 +- src/drivers/oxford/oxpcie/Kconfig | 2 +- src/drivers/oxford/oxpcie/Makefile.inc | 2 +- src/drivers/uart/Kconfig | 15 ++++++++--- src/drivers/uart/Makefile.inc | 13 ++++----- src/lib/coreboot_table.c | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/samsung/lumpy/romstage.c | 4 +-- src/mainboard/samsung/stumpy/romstage.c | 4 +-- src/mainboard/ti/beaglebone/Kconfig | 4 +-- src/superio/via/vt1211/vt1211.c | 2 +- 24 files changed, 79 insertions(+), 89 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 93ea38d..7614531 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -28,7 +28,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) @@ -38,7 +38,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif } diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 66c81db..4bd3ad4 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -30,7 +30,7 @@ */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" #endif @@ -40,7 +40,7 @@ static void __console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K @@ -61,7 +61,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 5e7923e..0337245 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -31,10 +31,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) @@ -53,10 +50,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/console/Kconfig b/src/console/Kconfig index d77bb9e..65fc1aa 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,37 +29,29 @@ config SQUELCH_EARLY_SMP config CONSOLE_SERIAL bool "Serial port console output" default y + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL help - Send coreboot debug output to a serial port (should be one or more of - CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) + Send coreboot debug output to a serial port. -config CONSOLE_SERIAL8250 - bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_IO_MAPPED - default y - help - Send coreboot debug output to an I/O mapped serial port console. + The type of serial port driver selected based on your configuration is + shown on the following menu line. Supporting multiple different types + of UARTs in one build is not supported. -config CONSOLE_SERIAL8250MEM - bool "Serial port console output (memory mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_MEMORY_MAPPED - help - Send coreboot debug output to a memory mapped serial port console. +if CONSOLE_SERIAL + + comment "I/O mapped, 8250-compatible" + depends on DRIVERS_UART_8250IO -config CONSOLE_SERIAL_UART - bool "Serial port console output (device-specific UART)" - depends on CONSOLE_SERIAL + comment "memory mapped, 8250-compatible" + depends on DRIVERS_UART_8250MEM + + comment "device-specific UART" depends on HAVE_UART_SPECIAL - default y - help - Send coreboot debug output to a device-specific serial port console. choice prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO config CONSOLE_SERIAL_COM1 bool "COM1/ttyS0, I/O port 0x3f8" @@ -82,7 +74,7 @@ endchoice config TTYS0_BASE hex - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO default 0x3f8 if CONSOLE_SERIAL_COM1 default 0x2f8 if CONSOLE_SERIAL_COM2 default 0x3e8 if CONSOLE_SERIAL_COM3 @@ -93,7 +85,6 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" @@ -133,7 +124,9 @@ config TTYS0_BAUD config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM + +endif # CONSOLE_SERIAL config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/console/uart_console.c b/src/console/uart_console.c index e2cd6a8..f5535d7 100644 --- a/src/console/uart_console.c +++ b/src/console/uart_console.c @@ -43,7 +43,7 @@ static unsigned char uartmem_rx_byte(void) /* This only relevant with x86 with GDB_STUB enabled.*/ static int uartmem_tst_byte(void) { -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM return uart_can_rx_byte(); #else return 0; diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 72e3630..8512c38 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -76,7 +76,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a86d719..716e463 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -4,8 +4,6 @@ bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += raminit.c bootblock-y += timer.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c romstage-y += cbmem.c @@ -13,8 +11,6 @@ romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c romstage-y += twi.c -romstage-y += uart.c -romstage-y += uart_console.c ramstage-y += bootblock_media.c ramstage-y += cbmem.c @@ -23,8 +19,12 @@ ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += uart.c -ramstage-y += uart_console.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +romstage-y += uart.c uart_console.c +ramstage-y += uart.c uart_console.c +endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 63038c3..9320184 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -91,7 +91,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -117,7 +117,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6d7ae16..3d5b5b4 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index dd35c35..5f78cc5 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -93,7 +93,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -119,7 +119,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 4169a2e..844b835 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..5b10bd8 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,16 +1,19 @@ bootblock-y += dmtimer.c bootblock-y += bootblock_media.c bootblock-y += pinmux.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c -romstage-y += uart.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +romstage-y += uart.c ramstage-y += uart.c +endif $(call add-class,omap-header) diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 3325c32..6e9822e 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,10 +32,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif } @@ -45,10 +42,7 @@ void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL8250 - uart_init(); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #endif diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..148e257 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += parade subdirs-y += realtek subdirs-y += sil subdirs-y += trident -subdirs-y += uart +subdirs-$(CONFIG_DRIVERS_UART) += uart subdirs-y += usb subdirs-y += ics subdirs-y += spi diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..5ad42aa 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n - select HAVE_UART_MEMORY_MAPPED + select DRIVERS_UART_8250MEM help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 1922425..5e3e6e5 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_CONSOLE_SERIAL),y) ramstage-y += oxpcie_early.c oxpcie.c romstage-y += oxpcie_early.c endif diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 5c9a9d1..889c69a 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,10 +1,19 @@ -# This should default to N and be set by SuperI/O drivers that have an UART -config HAVE_UART_IO_MAPPED +config DRIVERS_UART bool + default y if CONSOLE_SERIAL + default n + +config DRIVERS_UART_8250IO + bool "Serial port on SuperIO" depends on !ARCH_ARMV7 + default n if NO_UART_ON_SUPERIO default y if ARCH_X86 -config HAVE_UART_MEMORY_MAPPED +# Select this for mainboard without SuperIO serial port. +config NO_UART_ON_SUPERIO + def_bool n + +config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 415c5bb..286bff2 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,28 +1,25 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c smm-$(CONFIG_DEBUG_SMI) += util.c -endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +# Add the driver, only one can be enabled. The driver files may +# be located in the soc/ or cpu/ directories instead of here. + +ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) romstage-y += uart8250io.c ramstage-y += uart8250io.c smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_DRIVERS_UART_8250MEM),y) romstage-y += uart8250mem.c ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) - ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c ramstage-y += pl011.c endif - -endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e4554d7..8e7f85d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -390,7 +390,7 @@ unsigned long write_coreboot_table( lb_mainboard(head); /* Record the serial ports and consoles */ -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_fill_lb(head); #endif #if CONFIG_CONSOLE_USB diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index edba627..040ed9c 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -50,7 +50,7 @@ config DRAM_SIZE_MB config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x10009000 # Memory map for qemu vexpress-a9: diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9933459..55c1f0a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/msr.h> #include "option_table.h" #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index e5b55b5..3e27a6a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -62,7 +62,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index df7ebeb..c842a5d 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -64,7 +64,7 @@ config CBFS_HEADER_ROM_OFFSET choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -100,7 +100,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x44e09000 if CONSOLE_SERIAL_UART0 default 0x48022000 if CONSOLE_SERIAL_UART1 default 0x48024000 if CONSOLE_SERIAL_UART2 diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 551f6f0..f7a5cd9 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -117,7 +117,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) {

1 0

Patch set updated for coreboot: b0747db OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit b0747dbfe615d2a106c1d25ce8b26e313b476f91 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 12 +++- src/device/Kconfig | 29 +++++++++ src/device/Makefile.inc | 1 + src/device/pci_early.c | 104 +++++++++++++++++++++++++++++++ src/drivers/oxford/oxpcie/Kconfig | 64 +------------------ src/drivers/oxford/oxpcie/oxpcie_early.c | 89 ++++++-------------------- src/include/console/uart.h | 1 - src/include/device/pci.h | 2 + src/mainboard/samsung/lumpy/Kconfig | 16 +++++ 9 files changed, 183 insertions(+), 135 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 9e9e4e2..348264d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -28,6 +28,11 @@ #include <arch/hlt.h> #include <arch/io.h> +#if CONFIG_EARLY_PCI_BRIDGE +/* FIXME: ROMCC chokes on PCI headers. */ +#include <device/pci.h> +#endif + #ifndef __PRE_RAM__ #include <string.h> #include <types.h> @@ -40,6 +45,9 @@ void console_init(void) if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); +#endif for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -101,8 +109,8 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_DRIVERS_OXFORD_OXPCIE - oxford_init(); +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); #endif #if CONFIG_CONSOLE_SERIAL uart_init(); diff --git a/src/device/Kconfig b/src/device/Kconfig index eaa0c04..932b4de 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -237,6 +237,35 @@ config PCIEXP_ASPM config PCI_BUS_SEGN_BITS int default 0 + +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +endif # EARLY_PCI_BRIDGE + endmenu menu "VGA BIOS" diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index ce412b7..bd41b12 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -11,6 +11,7 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c romstage-y += device_romstage.c diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..e31287e 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,9 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <delay.h> + +#ifdef __PRE_RAM__ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) { @@ -66,3 +73,100 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } +#endif + + +#if CONFIG_EARLY_PCI_BRIDGE + +static void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +{ + u16 reg16; + + /* Disable MMIO window behind the bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); + + if (!size) + return; + + /* Enable MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); + + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} + +void pci_early_bridge_init(void) +{ + int timeout, ret = -1; + + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + /* Secondary bus number is mostly irrelevant as we disable + * configuration transactions right after the probe. + */ + u8 secondary = 15; + u8 dev = 0; + u32 mmio_base = CONFIG_EARLY_PCI_MMIO_BASE; + + /* Enable configuration and MMIO over bridge. */ + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, secondary); + pci_bridge_set_mmio(p2p_bridge, mmio_base, 0x4000); + + for (timeout = 20000; timeout; timeout--) { + u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); + if (id != 0 && id != 0xffffffff && id != 0xffff0001) + break; + udelay(10); + } + + if (timeout != 0) + ret = pci_early_device_probe(secondary, dev, mmio_base); + + /* Disable MMIO window if we found no suitable device. */ + if (ret) + pci_bridge_set_mmio(p2p_bridge, 0, 0); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Thus early device cannot reliably use config + * transactions from here on, so we may as well disable them. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} +#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 5ad42aa..c2ea7b6 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 7de9da6..b81fa89 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -23,101 +23,53 @@ #include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> -#include <delay.h> #include <boot/coreboot_tables.h> #include <console/uart.h> #include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -157,8 +109,3 @@ unsigned int uart_platform_refclk(void) { return 62500000; } - -void oxford_init(void) -{ - oxpcie_init_bridge(); -} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ed922f1..68abf6f 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -54,7 +54,6 @@ static inline void *uart_platform_baseptr(int idx) } #endif -void oxford_init(void); void oxford_remap(unsigned int new_base); #endif /* CONSOLE_UART_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..f729c27 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -102,6 +102,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); +void pci_early_bridge_init(void); +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); #endif /* CONFIG_PCI */ diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 032b4b5..500427a 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -46,4 +46,20 @@ config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +endif + endif # BOARD_SAMSUNG_LUMPY

1 0

Patch set updated for coreboot: b3e6a86 console: Split console_init()
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5331 -gerrit commit b3e6a867746687ab3ee62d3092d32baf828f05b0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 10:04:31 2014 +0200 console: Split console_init() Splitting the version prompt satisfies some requirements ROMCC sets for the order in which we include source files. Also GDB stub will need console hardware before entering main(). Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/bootblock_simple.c | 2 +- src/arch/x86/lib/Makefile.inc | 2 -- src/arch/x86/lib/romcc_console.c | 3 +-- src/console/Makefile.inc | 12 ++++----- src/console/console.c | 38 ++------------------------ src/console/init.c | 56 +++++++++++++++++++++++++++++++++++++++ src/include/console/console.h | 1 + 7 files changed, 67 insertions(+), 47 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 2c8e053..bc3ef53 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -56,7 +56,7 @@ void main(void) bootblock_mainboard_init(); } -#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if CONFIG_BOOTBLOCK_CONSOLE console_init(); #endif diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 8588c76..c173011 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -27,5 +27,3 @@ smm-y += rom_media.c rmodules-y += memset.c rmodules-y += memcpy.c rmodules-y += memmove.c - -$(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 4bd3ad4..3f8f62f 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -129,7 +129,6 @@ static void __console_tx_string(int loglevel, const char *str) /* if included by romcc, include the sources, too. romcc can't use prototypes */ #include <console/console.c> +#include <console/init.c> #include <console/post.c> #include <console/die.c> - - diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index df08e80..f8bbf22 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += printk.c -ramstage-y += console.c +ramstage-y += init.c console.c ramstage-y += vtxprintf.c ramstage-y += vsprintf.c ramstage-y += post.c @@ -9,12 +9,12 @@ smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c -romstage-y += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += init.c console.c romstage-y += post.c romstage-y += die.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c -bootblock-y += console.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c @@ -25,6 +25,6 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c -$(obj)/console/console.ramstage.o : $(obj)/build.h -$(obj)/console/console.romstage.o : $(obj)/build.h -$(obj)/console/console.bootblock.o : $(obj)/build.h +$(obj)/console/init.ramstage.o : $(obj)/build.h +$(obj)/console/init.romstage.o : $(obj)/build.h +$(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 348264d..1712877 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,30 +24,13 @@ #include <console/ne2k.h> #include <console/spkmodem.h> -#include <build.h> -#include <arch/hlt.h> -#include <arch/io.h> - -#if CONFIG_EARLY_PCI_BRIDGE -/* FIXME: ROMCC chokes on PCI headers. */ -#include <device/pci.h> -#endif - #ifndef __PRE_RAM__ -#include <string.h> -#include <types.h> -#include <option.h> /* initialize the console */ -void console_init(void) +void console_hw_init(void) { struct console_driver *driver; - if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) - console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_EARLY_PCI_BRIDGE - pci_early_bridge_init(); -#endif for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -104,14 +87,8 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -void console_init(void) +void console_hw_init(void) { -#if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ - !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE - -#if CONFIG_EARLY_PCI_BRIDGE - pci_early_bridge_init(); -#endif #if CONFIG_CONSOLE_SERIAL uart_init(); #endif @@ -127,16 +104,5 @@ void console_init(void) #if CONFIG_CONSOLE_USB && CONFIG_USBDEBUG_IN_ROMSTAGE && !defined(__BOOT_BLOCK__) usbdebug_init(); #endif - - static const char console_test[] = - "\n\ncoreboot-" - COREBOOT_VERSION - COREBOOT_EXTRA_VERSION - " " - COREBOOT_BUILD - " starting...\n"; - print_info(console_test); - -#endif /* CONFIG_EARLY_CONSOLE */ } #endif diff --git a/src/console/init.c b/src/console/init.c new file mode 100644 index 0000000..28934e7 --- /dev/null +++ b/src/console/init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <build.h> +#include <console/console.h> +#include <console/uart.h> +#include <option.h> + +#if CONFIG_EARLY_PCI_BRIDGE +/* FIXME: ROMCC chokes on PCI headers. */ +#include <device/pci.h> +#endif + +void console_init(void) +{ +#if !defined(__PRE_RAM__) + if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) + console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#endif + +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); +#endif + + console_hw_init(); + +#if defined(__PRE_RAM__) + static const char console_test[] = + "\n\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION + " " + COREBOOT_BUILD + " starting...\n"; + + print_info(console_test); +#endif +} diff --git a/src/include/console/console.h b/src/include/console/console.h index a089729..6d1b01a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -53,6 +53,7 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); +void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); void post_code(u8 value);

1 0

Patch set updated for coreboot: 3ad0b67 OxPCIe uart: Move under drivers/uart
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5329 -gerrit commit 3ad0b67d71fa1de8b554920bd0fe238655a2dc48 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 15:15:12 2014 +0200 OxPCIe uart: Move under drivers/uart This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/Kconfig | 1 - src/drivers/Makefile.inc | 1 - src/drivers/oxford/Kconfig | 1 - src/drivers/oxford/Makefile.inc | 1 - src/drivers/oxford/oxpcie/Kconfig | 10 --- src/drivers/oxford/oxpcie/Makefile.inc | 4 -- src/drivers/oxford/oxpcie/oxpcie.c | 73 -------------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 111 ------------------------------- src/drivers/uart/Kconfig | 11 +++ src/drivers/uart/Makefile.inc | 5 ++ src/drivers/uart/oxpcie.c | 73 ++++++++++++++++++++ src/drivers/uart/oxpcie_early.c | 111 +++++++++++++++++++++++++++++++ 12 files changed, 200 insertions(+), 202 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..1a5f8ff 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -27,7 +27,6 @@ source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig source src/drivers/ipmi/Kconfig source src/drivers/maxim/Kconfig -source src/drivers/oxford/Kconfig source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 148e257..f11e4b8 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -25,7 +25,6 @@ subdirs-y += i2c subdirs-y += intel subdirs-y += maxim subdirs-y += net -subdirs-y += oxford subdirs-y += parade subdirs-y += realtek subdirs-y += sil diff --git a/src/drivers/oxford/Kconfig b/src/drivers/oxford/Kconfig deleted file mode 100644 index cd7c27c..0000000 --- a/src/drivers/oxford/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/oxford/oxpcie/Kconfig diff --git a/src/drivers/oxford/Makefile.inc b/src/drivers/oxford/Makefile.inc deleted file mode 100644 index 732face..0000000 --- a/src/drivers/oxford/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig deleted file mode 100644 index c2ea7b6..0000000 --- a/src/drivers/oxford/oxpcie/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config DRIVERS_OXFORD_OXPCIE - bool "Oxford OXPCIe952" - default n - depends on PCI - select DRIVERS_UART_8250MEM - select EARLY_PCI_BRIDGE - help - Support for Oxford OXPCIe952 serial port PCIe cards. - Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc deleted file mode 100644 index 5e3e6e5..0000000 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) -ramstage-y += oxpcie_early.c oxpcie.c -romstage-y += oxpcie_early.c -endif diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c deleted file mode 100644 index 76119d2..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include <console/uart.h> -#include <arch/io.h> - -static void oxford_oxpcie_enable(device_t dev) -{ - printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - - struct resource *res = find_resource(dev, 0x10); - if (!res) { - printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); - return; - } - - printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); - printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); - printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); -} - - -static void oxford_oxpcie_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); - - /* Re-initialize OXPCIe base address after set_resources */ - u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - oxford_remap(mmio_base & ~0xf); -} - -static struct device_operations oxford_oxpcie_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = oxford_oxpcie_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = oxford_oxpcie_enable, - .scan_bus = 0, -}; - -static const struct pci_driver oxford_oxpcie_driver __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc158, -}; - -static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc11b, -}; diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c deleted file mode 100644 index b81fa89..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <stddef.h> -#include <arch/io.h> -#include <arch/early_variables.h> -#include <boot/coreboot_tables.h> -#include <console/uart.h> -#include <device/pci.h> -#include <device/pci_def.h> - -static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; - -int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) -{ - pci_devfn_t device = PCI_DEV(bus, dev, 0); - - u32 id = pci_read_config32(device, PCI_VENDOR_ID); - switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ - /* On this device function 0 is the parallel port, and - * function 3 is the serial port. So let's go look for - * the UART. - */ - device = PCI_DEV(bus, dev, 3); - id = pci_read_config32(device, PCI_VENDOR_ID); - if (id != 0xc11b1415) - return -1; - break; - case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ - case 0xc1581415: /* e.g. Startech MPEX2S952 */ - break; - default: - /* No UART here. */ - return -1; - } - - /* Sanity-check, we assume fixed location. */ - if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) - return -1; - - /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable memory on device */ - u16 reg16 = pci_read_config16(device, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(device, PCI_COMMAND, reg16); - - car_set_var(oxpcie_present, 1); - return 0; -} - -static int oxpcie_uart_active(void) -{ - return (car_get_var(oxpcie_present)); -} - -unsigned int uart_platform_base(int idx) -{ - if (idx == 0 && oxpcie_uart_active()) - return uart0_base; - if (idx == 1 && oxpcie_uart_active()) - return uart1_base; - return 0; -} - -#ifndef __PRE_RAM__ -void oxford_remap(u32 new_base) -{ - uart0_base = new_base + 0x1000; - uart1_base = new_base + 0x2000; -} - -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); - serial.baud = default_baudrate(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif - -unsigned int uart_platform_refclk(void) -{ - return 62500000; -} diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 889c69a..a979437 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -21,6 +21,17 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_OXPCIE + bool "Oxford OXPCIe952" + default n + depends on PCI + select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE + help + Support for Oxford OXPCIe952 serial port PCIe cards. + Currently only devices with the vendor ID 0x1415 and device ID + 0xc158 or 0xc11b will work. + config DRIVERS_UART_PL011 bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 286bff2..5164282 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -18,6 +18,11 @@ ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif +ifeq ($(CONFIG_DRIVERS_UART_OXPCIE),y) +ramstage-y += oxpcie_early.c oxpcie.c +romstage-y += oxpcie_early.c +endif + ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c new file mode 100644 index 0000000..76119d2 --- /dev/null +++ b/src/drivers/uart/oxpcie.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <console/uart.h> +#include <arch/io.h> + +static void oxford_oxpcie_enable(device_t dev) +{ + printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); + + struct resource *res = find_resource(dev, 0x10); + if (!res) { + printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", + (read32(res->base) >> 8), (read32(res->base) & 0xff)); + printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", + (read32(res->base + 4) & 3)); + printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); +} + + +static void oxford_oxpcie_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + /* Re-initialize OXPCIe base address after set_resources */ + u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); +} + +static struct device_operations oxford_oxpcie_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = oxford_oxpcie_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = oxford_oxpcie_enable, + .scan_bus = 0, +}; + +static const struct pci_driver oxford_oxpcie_driver __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc158, +}; + +static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc11b, +}; diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c new file mode 100644 index 0000000..b81fa89 --- /dev/null +++ b/src/drivers/uart/oxpcie_early.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <stddef.h> +#include <arch/io.h> +#include <arch/early_variables.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> + +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t device = PCI_DEV(bus, dev, 0); + + u32 id = pci_read_config32(device, PCI_VENDOR_ID); + switch (id) { + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ + /* On this device function 0 is the parallel port, and + * function 3 is the serial port. So let's go look for + * the UART. + */ + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); + if (id != 0xc11b1415) + return -1; + break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ + case 0xc1581415: /* e.g. Startech MPEX2S952 */ + break; + default: + /* No UART here. */ + return -1; + } + + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + + /* Setup base address on device */ + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable memory on device */ + u16 reg16 = pci_read_config16(device, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(device, PCI_COMMAND, reg16); + + car_set_var(oxpcie_present, 1); + return 0; +} + +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); +} + +unsigned int uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} + +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 62500000; +}

1 0

Patch set updated for coreboot: 13515d1 util/cbfstool: Make cbfs_image_delete() NULL-tolerant.
by Edward O'Callaghan 07 Apr '14

07 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5353 -gerrit commit 13515d15ba2842f33948b312e87e7ae292287951 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 00:05:18 2014 +1100 util/cbfstool: Make cbfs_image_delete() NULL-tolerant. This fixes a double free crash that occurs when a call to cbfs_image_from_file() fails in cbfs_extract() and falls though to cbfs_image_delete() with a NULL-pointer. To reproduce the crash pass the following arguments where the files passed, in fact, do not exist. As follows: ./cbfstool build/coreboot.rom extract -n config -f /tmp/config.txt Change-Id: I2213ff175d0703705a0ec10271b30bb26b6f8d0a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/cbfstool/cbfs_image.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index b9d5f28..12bc2fe 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -300,6 +300,9 @@ int cbfs_image_write_file(struct cbfs_image *image, const char *filename) int cbfs_image_delete(struct cbfs_image *image) { + if (image == NULL) + return 0; + buffer_delete(&image->buffer); image->header = NULL; return 0;

1 0

New patch to review for coreboot: f8f5565 jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
by Edward O'Callaghan 07 Apr '14

07 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5472 -gerrit commit f8f5565061ef06c6b76c2200a26dcb89c2dbc347 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 7 14:59:42 2014 +1000 jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio() Follow same reasoning as: C-Id: I4f24820606900e16f0d159df019f4560f1592489 NOTFORMERGE Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 59 ++++++++++-------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 2 +- 2 files changed, 25 insertions(+), 36 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index e6633f3..a09b405 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -26,9 +26,12 @@ #include "BiosCallOuts.h" #include "PlatformGnbPcieComplex.h" +#define __SIMPLE_DEVICE__ + #include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <stdint.h> #include <string.h> @@ -74,53 +77,39 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *------------------------------------------------------------------------------ */ -UINT32 -agesawrapper_amdinitcpuio ( - VOID - ) +uinit32_t agesawrapper_amdinitcpuio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + pci_devfn_t dev; + msr_t msr; + uint32_t reg32; + + dev = PCI_DEV(0, 0x18, 1); /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0xf4, 1); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. + * Last address before processor local APIC at FEE00000 */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); + + /* Lowest NP address is HPET at FED00000 */ + pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x8C, 0x00fecf00); + + msr = rdmsr(0xc001001a); + reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ + pci_io_write_config32(dev, 0x88, reg32); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + pci_io_write_config32(dev, 0xc4, 0x0000f000); + pci_io_write_config32(dev, 0xc0, 0x00000003); + + return AGESA_SUCCESS; } UINT32 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index 6544d25..6af5e5f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -82,7 +82,7 @@ UINT32 agesawrapper_amdinitmid (void); UINT32 agesawrapper_amdreadeventlog (void); -UINT32 agesawrapper_amdinitcpuio (void); +uint32_t agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdinitresume (void); UINT32 agesawrapper_amdS3Save (void);

1 0

Patch set updated for coreboot: 9f43ecd util/cbfstool: Make cbfs_image_delete() NULL-tolerant.
by Edward O'Callaghan 07 Apr '14

07 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5353 -gerrit commit 9f43ecd0367ec6b27c0926e9bcdf673c819fce81 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 00:05:18 2014 +1100 util/cbfstool: Make cbfs_image_delete() NULL-tolerant. This fixes a double free crash that occurs when a call to cbfs_image_from_file() fails in cbfs_extract() and falls though to cbfs_image_delete() with a NULL-pointer. To reproduce the crash pass the following arguments where the files passed, in fact, do not exist. As follows: ./cbfstool build/coreboot.rom extract -n config -f /tmp/config.txt Change-Id: I2213ff175d0703705a0ec10271b30bb26b6f8d0a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/cbfstool/cbfs_image.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index b9d5f28..12bc2fe 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -300,6 +300,9 @@ int cbfs_image_write_file(struct cbfs_image *image, const char *filename) int cbfs_image_delete(struct cbfs_image *image) { + if (image == NULL) + return 0; + buffer_delete(&image->buffer); image->header = NULL; return 0;

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coreboot-gerrit April 2014