coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 3f20f29 hp/pavilion_m6_1035dx: Add basic EC initialization
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5471 -gerrit commit 3f20f2951295d662343476b65416b20ce75b2791 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:57:57 2014 -0500 hp/pavilion_m6_1035dx: Add basic EC initialization The EC is now set to ACPI mode, and properly generates SCIs on external events. This fixes the issue where battery notifications were not working. Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 1 + src/mainboard/hp/pavilion_m6_1035dx/ec.c | 27 ++++++++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/ec.h | 6 ++++++ src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 4 ++++ 4 files changed, 38 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 3103f70..07ea765 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -26,3 +26,4 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ramstage-y += ec.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c new file mode 100644 index 0000000..d6d7229 --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "ec.h" +#include <ec/compal/ene932/ec.h> + +static void set_us_keyboard_layout(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); +} + +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */ +static void enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +void pavilion_m6_1035dx_ec_init(void) +{ + set_us_keyboard_layout(); + /* This could also be done in an SMI, should we decide to use SMM */ + enter_acpi_mode(); +} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h new file mode 100644 index 0000000..672141d --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +void pavilion_m6_1035dx_ec_init(void); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 5ac478f..2e2b72b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -19,6 +19,7 @@ #include "agesawrapper.h" #include "BiosCallOuts.h" +#include "ec.h" #include <arch/acpi.h> #include <arch/io.h> @@ -35,6 +36,9 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + pavilion_m6_1035dx_ec_init(); + /* * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions.

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New patch to review for coreboot: fda161c ec/compal/ene932/ec.h: Include stdint.h (TRIVIAL)
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5470 -gerrit commit fda161c2f78fb83bc068b30534b16865312654d6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:48:44 2014 -0500 ec/compal/ene932/ec.h: Include stdint.h (TRIVIAL) It's needed for definitions of 'u8'. Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/ec.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index 879925f..a1f4544 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -24,6 +24,8 @@ #ifndef _EC_COMPAL_ENE932_EC_H #define _EC_COMPAL_ENE932_EC_H +#include <stdint.h> + #define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */ #define EC_IO_HIGH EC_IO + 1 #define EC_IO_LOW EC_IO + 2

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Patch set updated for coreboot: 21a394c hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit 21a394c1782019c5f2d75152703a967d70e48505 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 14 ++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..e0d92fa --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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Patch set updated for coreboot: acc5815 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5463 -gerrit commit acc5815fa151c1e15dbea04459ee73d8aaa678d5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:02:28 2014 -0500 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 0ddb038..5c8fc67 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -47,6 +47,17 @@ USBS, 1, } + /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ + OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) + Field (GPIO, ByteAcc, NoLock, Preserve) { + Offset (0x39), + , 6, + GP57, 1, /* out: WLAN control (rf-kill) */ + Offset (0x76), + , 7, + GE22, 1, /* General event 22 - connected to lid switch */ + } + /* * Used by EC code on certain events *

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Patch set updated for coreboot: be249f7 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5462 -gerrit commit be249f71d5de2542b36a456381fe5f585d0c8360 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 18:51:33 2014 -0500 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 108 ++---------------------- 1 file changed, 6 insertions(+), 102 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3a80e01..2b47baa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -368,72 +368,14 @@ GPIO_CONTROL parmer_gpio[] = { */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -447,44 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);

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Patch set updated for coreboot: 7c08ca3 hp/pavilion_m6_1035dx: Add ACPI support for lid switch
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5464 -gerrit commit 7c08ca307a6cf8aeafc850acf16bd2dcf73f0fb9 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:26:56 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for lid switch This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 5c8fc67..47d7872 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -71,3 +71,15 @@ Store("Received PNOT call (probably from EC)", Debug) /* TODO: Implement this */ } + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (GE22, \LIDS) + Return (\LIDS) + } + } +}

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New patch to review for coreboot: e3785a6 allwinner/a10: Hide SoC specific UART functions
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5469 -gerrit commit e3785a6a8436de4d88568a232c6663139a6225b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 20:32:59 2014 +0300 allwinner/a10: Hide SoC specific UART functions If platform has a component coreboot has to communicate with using one of the UARTs, that device would not be part of the SoC and must not use functions specific to a10 UART. Also, a10 UART suppor should be changed to generic uart8250mem support for ARM. Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 40 ++++++++++++++++++++++++++---------- src/cpu/allwinner/a10/uart.h | 7 ------- src/cpu/allwinner/a10/uart_console.c | 28 +------------------------ 3 files changed, 30 insertions(+), 45 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 1885ace..feccc82 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -13,12 +13,11 @@ /** * \brief Configure line control settings for UART */ -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, +static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, enum uart_parity parity, u8 stop_bits) { u32 reg32; u16 div; - struct a10_uart *uart = uart_base; div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); @@ -44,10 +43,8 @@ void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, write32(reg32, &uart->lcr); } -void a10_uart_enable_fifos(void *uart_base) +static void a10_uart_enable_fifos(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - write32(UART_FCR_FIFO_EN, &uart->fcr); } @@ -70,10 +67,8 @@ static int rx_fifo_empty(struct a10_uart *uart) * * Blocks until at least a byte is available. */ -u8 a10_uart_rx_blocking(void *uart_base) +static u8 a10_uart_rx_blocking(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - while (rx_fifo_empty(uart)) ; return read32(&uart->rbr); @@ -84,11 +79,34 @@ u8 a10_uart_rx_blocking(void *uart_base) * * Blocks until there is space in the FIFO. */ -void a10_uart_tx_blocking(void *uart_base, u8 data) +static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { - struct a10_uart *uart = uart_base; - while (tx_fifo_full(uart)) ; return write32(data, &uart->thr); } + + +void uart_init(int idx) +{ + struct a10_uart *uart_base = uart_platform_baseptr(idx); + + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, default_baudrate(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +unsigned char uart_rx_byte(int idx) +{ + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); +} + +void uart_tx_flush(int idx) +{ +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h index 86ab487..aa94362 100644 --- a/src/cpu/allwinner/a10/uart.h +++ b/src/cpu/allwinner/a10/uart.h @@ -13,7 +13,6 @@ #ifndef CPU_ALLWINNER_A10_UART_H #define CPU_ALLWINNER_A10_UART_H -#include "memmap.h" #include <types.h> struct a10_uart { @@ -68,10 +67,4 @@ enum uart_parity { UART_PARITY_ODD, }; -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, - enum uart_parity parity, u8 stop_bits); -void a10_uart_enable_fifos(void *uart_base); -u8 a10_uart_rx_blocking(void *uart_base); -void a10_uart_tx_blocking(void *uart_base, u8 data); - #endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index bb5f41c..b787961 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -6,13 +6,11 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#include <config.h> #include <types.h> #include <console/uart.h> -#include <arch/io.h> #include <boot/coreboot_tables.h> -#include <cpu/allwinner/a10/uart.h> +#include "memmap.h" unsigned int uart_platform_base(int idx) { @@ -29,30 +27,6 @@ unsigned int uart_platform_refclk(void) return 24000000; } -void uart_init(int idx) -{ - void *uart_base = uart_platform_baseptr(idx); - - /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, default_baudrate(), - 8, UART_PARITY_NONE, 1); - a10_uart_enable_fifos(uart_base); -} - -unsigned char uart_rx_byte(int idx) -{ - return a10_uart_rx_blocking(uart_platform_baseptr(idx)); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - a10_uart_tx_blocking(uart_platform_baseptr(idx), data); -} - -void uart_tx_flush(int idx) -{ -} - #ifndef __PRE_RAM__ void uart_fill_lb(void *data) {

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Patch set updated for coreboot: 47f7691 console: Use romstage code for ramstage and SMM
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5338 -gerrit commit 47f76914b25f07c03d5ca97561b3f75cc92c157e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 27 19:30:18 2014 +0200 console: Use romstage code for ramstage and SMM Console is arch-agnostic and there is no need for separate implementations for romstage and ramstage. For SMM there is console only if DEBUG_SMI is selected. Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/Makefile.inc | 2 -- src/arch/armv7/early_console.c | 40 -------------------------- src/arch/x86/lib/Makefile.inc | 1 - src/arch/x86/lib/romcc_console.c | 26 +++-------------- src/arch/x86/lib/romstage_console.c | 57 ------------------------------------- src/console/Makefile.inc | 3 +- src/console/console.c | 39 +++++++++++++++++++++---- src/console/init.c | 3 +- src/console/printk.c | 1 + src/cpu/x86/smm/Makefile.inc | 2 -- src/cpu/x86/smm/smiutil.c | 47 ------------------------------ src/include/console/console.h | 6 ++-- src/include/console/streams.h | 25 ++++++++++++++++ 13 files changed, 70 insertions(+), 182 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index dfd5164..f0adc0a 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -163,12 +163,10 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD ramstage-y += exception.c ramstage-y += exception_asm.S -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c bootblock-y += cache.c romstage-y += cache.c romstage-y += div0.c -romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c #ramstage-y += interrupts.c diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c deleted file mode 100644 index 599cbc7..0000000 --- a/src/arch/armv7/early_console.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> -#include <console/uart.h> - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) - cbmemc_tx_byte(byte); -#endif -} - -void console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -} diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index c173011..8b7418b 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -12,7 +12,6 @@ ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S -romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0557a52..454e0bc 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,8 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/uart.h> -#include <console/ne2k.h> +#include <console/streams.h> /* While in romstage, console loglevel is built-time constant. */ #define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) @@ -31,25 +30,9 @@ #include "drivers/net/ne2k.c" #endif -static void __console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -} - -static void __console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -} +#include <console/console.c> +#define __console_tx_byte console_tx_byte +#define __console_tx_flush console_tx_flush static void __console_tx_nibble(unsigned nibble) { @@ -118,7 +101,6 @@ static void __console_tx_string(int loglevel, const char *str) } /* if included by romcc, include the sources, too. romcc can't use prototypes */ -#include <console/console.c> #include <console/init.c> #include <console/post.c> #include <console/die.c> diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c deleted file mode 100644 index 58742a2..0000000 --- a/src/arch/x86/lib/romstage_console.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> -#include <console/uart.h> -#include <console/usb.h> -#include <console/ne2k.h> -#include <console/spkmodem.h> - -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_tx_byte(byte); -#endif -#if CONFIG_SPKMODEM - spkmodem_tx_byte(byte); -#endif -} - -void console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_flush(0); -#endif -} diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d59e44e..e3b3780 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c -smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c +smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c printk.c @@ -15,6 +15,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c +$(obj)/console/init.smm.o : $(obj)/build.h $(obj)/console/init.ramstage.o : $(obj)/build.h $(obj)/console/init.romstage.o : $(obj)/build.h $(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 2f4eb5c..e0e505c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -17,12 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <console/streams.h> #include <console/cbmem_console.h> #include <console/uart.h> #include <console/usb.h> #include <console/ne2k.h> #include <console/spkmodem.h> +#include <console/qemu_debugcon.h> void console_hw_init(void) { @@ -32,23 +33,51 @@ void console_hw_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_init(); #endif #if CONFIG_SPKMODEM spkmodem_init(); #endif -#if CONFIG_CONSOLE_USB && CONFIG_USBDEBUG_IN_ROMSTAGE && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usbdebug_init(); #endif +#if CONFIG_CONSOLE_QEMU_DEBUGCON + qemu_debugcon_init(); +#endif } -#ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte) { +#if CONFIG_CONSOLE_SERIAL + uart_tx_byte(byte); +#endif +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) + usb_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) + cbmemc_tx_byte(byte); +#endif +#if CONFIG_SPKMODEM + spkmodem_tx_byte(byte); +#endif +#if CONFIG_CONSOLE_QEMU_DEBUGCON + qemu_debugcon_tx_byte(byte); +#endif } void console_tx_flush(void) { -} +#if CONFIG_CONSOLE_SERIAL + uart_tx_flush(); #endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) + usb_tx_flush(0); +#endif +} diff --git a/src/console/init.c b/src/console/init.c index d7c8cc3..8bdb2cc 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -22,6 +22,7 @@ #include <build.h> #include <console/console.h> #include <console/uart.h> +#include <console/streams.h> #include <option.h> #if CONFIG_EARLY_PCI_BRIDGE @@ -46,7 +47,7 @@ void console_init(void) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; #endif -#if CONFIG_EARLY_PCI_BRIDGE +#if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) pci_early_bridge_init(); #endif diff --git a/src/console/printk.c b/src/console/printk.c index 2fa160b..40ea404 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,6 +10,7 @@ #include <smp/spinlock.h> #include <console/vtxprintf.h> #include <console/console.h> +#include <console/streams.h> #include <trace.h> DECLARE_SPIN_LOCK(console_lock) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index bb9c11d..9720630 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_BACKUP_DEFAULT_SMM_REGION) += backup_default_smm.c ifeq ($(CONFIG_SMM_MODULES),y) smmstub-y += smm_stub.S -smm-y += smiutil.c smm-y += smm_module_handler.c ramstage-y += smm_module_loader.c @@ -79,7 +78,6 @@ SMM_LDSCRIPT := smm.ld endif smm-y += smihandler.c -smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c deleted file mode 100644 index 644cab7..0000000 --- a/src/cpu/x86/smm/smiutil.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -#if CONFIG_DEBUG_SMI -void console_tx_flush(void) -{ -} - -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -} -#endif - -void console_init(void) -{ -#if CONFIG_DEBUG_SMI - console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL - uart_init(); -#endif -#endif -} - diff --git a/src/include/console/console.h b/src/include/console/console.h index 0ebd1b7..54e4545 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,10 +26,6 @@ #ifndef __ROMCC__ int console_log_level(int msg_level); -void console_init(void); -void console_hw_init(void); -void console_tx_byte(unsigned char byte); -void console_tx_flush(void); void post_code(u8 value); #if CONFIG_CMOS_POST_EXTRA void post_log_extra(u32 value); @@ -52,9 +48,11 @@ void __attribute__ ((noreturn)) die(const char *msg); /* Do nothing. */ static inline void printk(int LEVEL, const char *fmt, ...) {} static inline void do_putchar(unsigned char byte) {} +static inline void console_init(void) {} #else +void console_init(void); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); diff --git a/src/include/console/streams.h b/src/include/console/streams.h new file mode 100644 index 0000000..288fade --- /dev/null +++ b/src/include/console/streams.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CONSOLE_STREAMS_H_ +#define _CONSOLE_STREAMS_H_ + +void console_hw_init(void); +void console_tx_byte(unsigned char byte); +void console_tx_flush(void); + +#endif /* _CONSOLE_STREAMS_H_ */

1 0

Patch set updated for coreboot: 3a2eccb uart: Prepare to support multiple base addresses
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5309 -gerrit commit 3a2eccb3778d3511107fa3d01e06b3bd0e8c9bf0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 24 20:51:30 2014 +0200 uart: Prepare to support multiple base addresses Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/samsung/exynos5250/uart.c | 50 ++++++++++++++++++--------------------- src/cpu/samsung/exynos5420/uart.c | 44 ++++++++++++++++------------------ src/cpu/ti/am335x/uart.c | 30 +++++++++++------------ src/drivers/uart/pl011.c | 13 ++++++---- src/include/console/uart.h | 5 ++++ 5 files changed, 72 insertions(+), 70 deletions(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 14d140c..860d020 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. exynos_pinmux_uart3(); @@ -102,12 +96,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -130,14 +123,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -147,49 +138,54 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } -static void exynos5_uart_tx_flush(void) +static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - while (readl(&uart->ufstat) & 0x1ff0000); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = uart_platform_baseptr(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { - exynos5_uart_tx_flush(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index d05adcd..82b1265 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); @@ -99,12 +93,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -127,14 +120,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -144,41 +135,48 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = uart_platform_baseptr(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = uart_platform_baseptr(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { + /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 27051ea..09bb96e 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -35,10 +35,8 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) { - struct am335x_uart *uart = (struct am335x_uart *) - CONFIG_CONSOLE_SERIAL_UART_ADDRESS; uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ @@ -131,11 +129,8 @@ static void am335x_uart_init(uint16_t div) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char am335x_uart_rx_byte(void) +static unsigned char am335x_uart_rx_byte(struct am335x_uart *uart) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_RXFIFOE)); return read8(&uart->rhr); @@ -144,11 +139,8 @@ static unsigned char am335x_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void am335x_uart_tx_byte(unsigned char data) +static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_TXFIFOE)); return write8(data, &uart->thr); @@ -159,28 +151,36 @@ unsigned int uart_platform_refclk(void) return 48000000; } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + return uart_platform_base(0); } #endif void uart_init(void) { + struct am335x_uart *uart = uart_platform_baseptr(0); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); + am335x_uart_init(uart, div); } unsigned char uart_rx_byte(void) { - return am335x_uart_rx_byte(); + struct am335x_uart *uart = uart_platform_baseptr(0); + return am335x_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - am335x_uart_tx_byte(data); + struct am335x_uart *uart = uart_platform_baseptr(0); + am335x_uart_tx_byte(uart, data); } void uart_tx_flush(void) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2202de7..e4bfdc6 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -15,12 +15,14 @@ #include <console/uart.h> -static void pl011_uart_tx_byte(unsigned char data) +static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + *uart_base = (unsigned int)data; +} - *uart0_address = (unsigned int)data; +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } #if !defined(__PRE_RAM__) @@ -36,7 +38,8 @@ void uart_init(void) void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + unsigned int *uart_base = uart_platform_baseptr(0); + pl011_uart_tx_byte(uart_base, data); } void uart_tx_flush(void) diff --git a/src/include/console/uart.h b/src/include/console/uart.h index f0371a2..e28b8f6 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -48,6 +48,11 @@ int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +static inline void *uart_platform_baseptr(int idx) +{ + return (void *)uart_platform_base(idx); +} + void oxford_init(void); void oxford_remap(unsigned int new_base);

1 0

Patch set updated for coreboot: c4bb41a console: Split ROMCC helpers
by Kyösti Mälkki 07 Apr '14

07 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5339 -gerrit commit c4bb41a31d5691c61bcb688258510af4e95114e1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 3 10:40:38 2014 +0200 console: Split ROMCC helpers These are potentially useful with GDB or SerialICE too. Also it reduces the amount of actual code we put in romcc_console. Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 76 +------------------ src/console/console.c | 46 ++++++++++++ src/include/console/console.h | 108 ++------------------------- src/include/console/early_print.h | 149 ++++++++++++++++++++++++++++++++++++++ src/include/console/streams.h | 7 ++ 5 files changed, 209 insertions(+), 177 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 454e0bc..0fa633a 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,11 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/streams.h> - -/* While in romstage, console loglevel is built-time constant. */ -#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) +#include <console/early_print.h> +/* Include the sources. */ #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" @@ -31,76 +29,6 @@ #endif #include <console/console.c> -#define __console_tx_byte console_tx_byte -#define __console_tx_flush console_tx_flush - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (console_log_level(loglevel)) { - __console_tx_byte(byte); - __console_tx_flush(); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (console_log_level(loglevel)) { - unsigned char ch; - while((ch = *str++) != '\0') { - if (ch == '\n') - __console_tx_byte('\r'); - __console_tx_byte(ch); - } - __console_tx_flush(); - } -} - -/* if included by romcc, include the sources, too. romcc can't use prototypes */ #include <console/init.c> #include <console/post.c> #include <console/die.c> diff --git a/src/console/console.c b/src/console/console.c index e0e505c..f66cd3f 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -81,3 +81,49 @@ void console_tx_flush(void) usb_tx_flush(0); #endif } + +void console_tx_nibble(unsigned nibble) +{ + unsigned char digit; + digit = nibble + '0'; + if (digit > '9') { + digit += 39; + } + console_tx_byte(digit); +} + +void console_tx_hex8(unsigned char value) +{ + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_hex16(unsigned short value) +{ + console_tx_nibble((value >> 12U) & 0x0fU); + console_tx_nibble((value >> 8U) & 0x0fU); + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_hex32(unsigned int value) +{ + console_tx_nibble((value >> 28U) & 0x0fU); + console_tx_nibble((value >> 24U) & 0x0fU); + console_tx_nibble((value >> 20U) & 0x0fU); + console_tx_nibble((value >> 16U) & 0x0fU); + console_tx_nibble((value >> 12U) & 0x0fU); + console_tx_nibble((value >> 8U) & 0x0fU); + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_string(const char *str) +{ + unsigned char ch; + while((ch = *str++) != '\0') { + if (ch == '\n') + console_tx_byte('\r'); + console_tx_byte(ch); + } +} diff --git a/src/include/console/console.h b/src/include/console/console.h index 54e4545..a15f608 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -21,7 +21,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <console/loglevel.h> #include <console/post_codes.h> #ifndef __ROMCC__ @@ -73,109 +72,12 @@ static inline void do_vtxprintf(const char *fmt, va_list args) {}; #endif #endif -#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) -#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) -#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) -#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) -#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) -#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) -#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) -#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) -#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) - -#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) -#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) -#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) -#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) -#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) -#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) -#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) -#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) -#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) - -#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) -#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) -#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) -#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) -#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) -#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) -#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) -#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) -#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) - -#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) -#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) -#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) -#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) -#define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) -#define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) -#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) -#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) -#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) - -#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) -#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) -#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) -#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) -#define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) -#define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) -#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) -#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) -#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) - -#else - -/* __ROMCC__ */ - -#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) -#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) -#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) -#define print_err(STR) __console_tx_string(BIOS_ERR, STR) -#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) -#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) -#define print_info(STR) __console_tx_string(BIOS_INFO, STR) -#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) -#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) - -#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) -#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) -#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) -#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) -#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) -#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) -#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) -#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) -#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) - -#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) -#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) -#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) -#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) -#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) -#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) -#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) -#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) -#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) - -#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) -#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) -#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) -#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) -#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) -#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) -#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) -#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) -#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) +/* A lot of code still uses print_debug() et al. while use of printk() + * would be preferred. + */ +#include <console/early_print.h> -#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) -#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) -#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) -#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) -#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) -#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) -#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) -#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) -#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) +#else /* __ROMCC__ */ #include "arch/x86/lib/romcc_console.c" diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h new file mode 100644 index 0000000..8bc1489 --- /dev/null +++ b/src/include/console/early_print.h @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CONSOLE_EARLY_PRINT_H_ +#define __CONSOLE_EARLY_PRINT_H_ + +#include <console/console.h> +#include <console/streams.h> +#include <console/loglevel.h> + +#if defined(__ROMCC__) +/* While in romstage, console loglevel is built-time constant. + * With ROMCC we inline this test with help from preprocessor. + */ +#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) + +#define CALL_CONSOLE_TX(loglevel, tx_func, x) \ + do { \ + if (console_log_level(loglevel)) { \ + tx_func(x); \ + console_tx_flush(); \ + } \ + } while (0) + +#define __console_tx_char(level, x) CALL_CONSOLE_TX(level, console_tx_byte, x) +#define __console_tx_hex8(level, x) CALL_CONSOLE_TX(level, console_tx_hex8, x) +#define __console_tx_hex16(level, x) CALL_CONSOLE_TX(level, console_tx_hex16, x) +#define __console_tx_hex32(level, x) CALL_CONSOLE_TX(level, console_tx_hex32, x) +#define __console_tx_string(level, x) CALL_CONSOLE_TX(level, console_tx_string, x) + +#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) +#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) +#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) +#define print_err(STR) __console_tx_string(BIOS_ERR, STR) +#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) +#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) +#define print_info(STR) __console_tx_string(BIOS_INFO, STR) +#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) +#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) + +#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) +#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) +#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) +#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) +#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) +#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) +#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) +#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) +#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) + +#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) +#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) +#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) +#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) +#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) +#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) +#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) +#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) +#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) + +#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) +#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) +#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) +#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) +#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) +#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) +#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) +#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) +#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) + +#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) +#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) +#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) +#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) +#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) +#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) +#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) +#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) +#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) + +#else + +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) + +#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) +#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) +#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) +#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) +#define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) +#define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) +#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) +#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) +#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) + +#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) +#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) +#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) +#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) +#define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) +#define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) +#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) +#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) +#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) + +#endif + +#endif /* __CONSOLE_EARLY_PRINT_H_ */ diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 288fade..9d4d3fc 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,4 +22,11 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* Helpers for ROMCC console. */ +void console_tx_nibble(unsigned nibble); +void console_tx_hex8(unsigned char value); +void console_tx_hex16(unsigned short value); +void console_tx_hex32(unsigned int value); +void console_tx_string(const char *str); + #endif /* _CONSOLE_STREAMS_H_ */

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coreboot-gerrit April 2014