coreboot-gerrit April 2014

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Patch set updated for coreboot: 745813e ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444 -gerrit commit 745813ed297b2608bdf2ee3a70a85a1317b2e4f1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Apr 1 16:02:08 2014 -0500 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Also, document the ACPI interface for the EC. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/ec/compal/ene932/documentation.txt | 24 ++++++++++++++++++++++++ src/mainboard/google/parrot/acpi/ec.asl | 3 +++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..a042d75 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -273,7 +273,7 @@ Device (EC0) Store (ADPT, \PWRS) // Initialize LID switch state - Store (GP15, \LIDS) + Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS) // Force a read of CPU temperature Store (CTML, Local0) diff --git a/src/ec/compal/ene932/documentation.txt b/src/ec/compal/ene932/documentation.txt new file mode 100644 index 0000000..9b29415 --- /dev/null +++ b/src/ec/compal/ene932/documentation.txt @@ -0,0 +1,24 @@ + +Accessing the EC space +====================== + +The ACPI implementation uses the standard I/O ports 0x62 and 0x66 to access the +EC functionality. Accesses to these ports must be directed to the LPC bus to +which the EC is connected. + + +Interfacing with the ASL files +============================== + +The mainboard code must define several variables for the ASL files. + +* EC_SMI + Defines the General Purpose Event (GPE) corresponding to the embedded + controller's SCI line. +* EC_ACPI_LID_SWITCH_OBJECT + Defines the APCI object which reads the state of the lid, with 0 = open, and + 1 = closed. This is usually the bit which reads the GPIO input coresponding to + the lid switch. +* PNOT() + The mainboard must define a PNOT method to handle power state notifications + and Notify CPU device objects to re-evaluate their _PPC and _CST tables. diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 522a0b9..a0ee9d5 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -21,5 +21,8 @@ #include "../ec.h" #define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI +/* GP15 is defined in the southbridge's ASL */ +#define EC_ACPI_LID_SWITCH_OBJECT GP15 + /* ACPI code for EC functions */ #include "../../../../ec/compal/ene932/acpi/ec.asl"

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Patch set updated for coreboot: a984aae hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5445 -gerrit commit a984aae9acb4d94b7bf8373cf4f2682564c9c337 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Mar 31 16:17:54 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 14 ++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 ------ .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 4 ++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl new file mode 100644 index 0000000..e0d92fa --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* + * EC bits specific to the mainboard + */ +#define EC_SCI 3 +/* TODO: We do not yet know how the LID is connected to the platform */ +#define EC_ACPI_LID_SWITCH_OBJECT Zero + +/* ACPI code for EC functions */ +#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 40a19d4..a240308 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -19,12 +19,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 040f069..0ddb038 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -35,9 +35,28 @@ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + /* Variables used by EC */ + /* TODO: These may belong in global non-volatile storage */ + Name(PWRS, Zero) + Name(LIDS, Zero) + /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } + + /* + * Used by EC code on certain events + * + * From ec/compal/ene932/acpi/ec.asl: + * The mainboard must define a PNOT method to handle power state + * notifications and Notify CPU device objects to re-evaluate their + * _PPC and _CST tables. + */ + Method (PNOT) + { + Store("Received PNOT call (probably from EC)", Debug) + /* TODO: Implement this */ + } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index ef2ae6f..c1f1933 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -69,6 +69,10 @@ DefinitionBlock ( } /* End Scope(_SB) */ + Scope(\_SB.PCI0.LIBR) { + #include "acpi/ec.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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Patch set updated for coreboot: 2ac3f39 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5463 -gerrit commit 2ac3f3969dd75f5d26a1dd5ce737a75cef08b428 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:02:28 2014 -0500 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 0ddb038..5c8fc67 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -47,6 +47,17 @@ USBS, 1, } + /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ + OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) + Field (GPIO, ByteAcc, NoLock, Preserve) { + Offset (0x39), + , 6, + GP57, 1, /* out: WLAN control (rf-kill) */ + Offset (0x76), + , 7, + GE22, 1, /* General event 22 - connected to lid switch */ + } + /* * Used by EC code on certain events *

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Patch set updated for coreboot: c0654cb hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5462 -gerrit commit c0654cb1851b6d02f10276541a52a87d0b78e130 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 18:51:33 2014 -0500 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 108 ++---------------------- 1 file changed, 6 insertions(+), 102 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3a80e01..2b47baa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -368,72 +368,14 @@ GPIO_CONTROL parmer_gpio[] = { */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -447,44 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Customer table UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);

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Patch set updated for coreboot: 89bc913 hp/pavilion_m6_1035dx: Add ACPI support for lid switch
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5464 -gerrit commit 89bc913b6b1d378a60fd1aed6eb6880064a081ea Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 19:26:56 2014 -0500 hp/pavilion_m6_1035dx: Add ACPI support for lid switch This is sufficient to at least allow linux to recognize the lid switch and read its state correctly. Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 5c8fc67..47d7872 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -71,3 +71,15 @@ Store("Received PNOT call (probably from EC)", Debug) /* TODO: Implement this */ } + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (GE22, \LIDS) + Return (\LIDS) + } + } +}

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Patch set updated for coreboot: f869625 hp/pavilion_m6_1035dx: Add basic EC initialization
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5471 -gerrit commit f869625fdd342e523e361b99c0acfac93207c9c6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:57:57 2014 -0500 hp/pavilion_m6_1035dx: Add basic EC initialization The EC is now set to ACPI mode, and properly generates SCIs on external events. This fixes the issue where battery notifications were not working. Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 1 + src/mainboard/hp/pavilion_m6_1035dx/ec.c | 27 ++++++++++++++++++++++++ src/mainboard/hp/pavilion_m6_1035dx/ec.h | 11 ++++++++++ src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 4 ++++ 4 files changed, 43 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 3103f70..07ea765 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -26,3 +26,4 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ramstage-y += ec.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c new file mode 100644 index 0000000..d6d7229 --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "ec.h" +#include <ec/compal/ene932/ec.h> + +static void set_us_keyboard_layout(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); +} + +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */ +static void enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +void pavilion_m6_1035dx_ec_init(void) +{ + set_us_keyboard_layout(); + /* This could also be done in an SMI, should we decide to use SMM */ + enter_acpi_mode(); +} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h new file mode 100644 index 0000000..0c00d7a --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H +#define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H + +void pavilion_m6_1035dx_ec_init(void); + +#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 5ac478f..2e2b72b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -19,6 +19,7 @@ #include "agesawrapper.h" #include "BiosCallOuts.h" +#include "ec.h" #include <arch/acpi.h> #include <arch/io.h> @@ -35,6 +36,9 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + pavilion_m6_1035dx_ec_init(); + /* * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions.

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Patch set updated for coreboot: f568362 ec/compal/ene932/ec.h: Include stdint.h (TRIVIAL)
by Alexandru Gagniuc 07 Apr '14

07 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5470 -gerrit commit f568362b1d1f18550612c08686d768ea6c25df03 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:48:44 2014 -0500 ec/compal/ene932/ec.h: Include stdint.h (TRIVIAL) It's needed for definitions of 'u8'. Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/ec.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index 879925f..a1f4544 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -24,6 +24,8 @@ #ifndef _EC_COMPAL_ENE932_EC_H #define _EC_COMPAL_ENE932_EC_H +#include <stdint.h> + #define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */ #define EC_IO_HIGH EC_IO + 1 #define EC_IO_LOW EC_IO + 2

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Patch merged into coreboot/master: 13515d1 util/cbfstool: Make cbfs_image_delete() NULL-tolerant.
by gerrit＠coreboot.org 07 Apr '14

07 Apr '14

the following patch was just integrated into master: commit 13515d15ba2842f33948b312e87e7ae292287951 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 00:05:18 2014 +1100 util/cbfstool: Make cbfs_image_delete() NULL-tolerant. This fixes a double free crash that occurs when a call to cbfs_image_from_file() fails in cbfs_extract() and falls though to cbfs_image_delete() with a NULL-pointer. To reproduce the crash pass the following arguments where the files passed, in fact, do not exist. As follows: ./cbfstool build/coreboot.rom extract -n config -f /tmp/config.txt Change-Id: I2213ff175d0703705a0ec10271b30bb26b6f8d0a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5353 for details. -gerrit

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New patch to review for coreboot: 222d9b9 Supermicro H8QGI: Change default interrupt model to PIC, according ACPI specification
by Aladyshev Konstantin 07 Apr '14

07 Apr '14

Aladyshev Konstantin (aladyshev22(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5473 -gerrit commit 222d9b917a5b31cfaacb9b26db59baca563a49b4 Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Sat Jul 12 02:36:32 2014 +0400 Supermicro H8QGI: Change default interrupt model to PIC, according ACPI specification According ACPI specification: """ The \_PIC optional method is used to report to the BIOS the current interrupt model used by the OS. The argument passed into the method signifies the interrupt model OSPM has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the method is never called, the BIOS must assume PIC mode. Arguments: (1) Arg0 – An Integer containing a code for the current interrupt model: 0 –PIC mode 1 –APIC mode 2 –SAPIC mode """ In current configuration with default value of interrupt model PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option. Kernel never call _PIC method and PMOD stays equal 1, indicatind that APIC routing objects should be evaluated. This mix of PIC and APIC leads to boot fail. Change default value of interrupt model PMOD to 1, for correct "noapic" boot. Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> --- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index c854067..b829584 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -57,7 +57,7 @@ DefinitionBlock ( /* Some global data */ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ + Name(PMOD, 0) /* Default interrupt model is PIC */ /* * Processor Object

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Patch set updated for coreboot: 974b8a8 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
by Idwer Vollering 07 Apr '14

07 Apr '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit 974b8a894cb1790eb416bc4a985585013ccab771 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index fe7dc9b..a45d072 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -605,7 +605,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

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coreboot-gerrit April 2014