coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 726f583 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
by Alexandru Gagniuc 09 Apr '14

09 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5444 -gerrit commit 726f583867c38417b49dce5779b5ead9b99c0d60 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Apr 1 16:02:08 2014 -0500 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Also, document the ACPI interface for the EC. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/ec/compal/ene932/documentation.txt | 23 +++++++++++++++++++++++ src/mainboard/google/parrot/acpi/ec.asl | 3 +++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..a042d75 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -273,7 +273,7 @@ Device (EC0) Store (ADPT, \PWRS) // Initialize LID switch state - Store (GP15, \LIDS) + Store (EC_ACPI_LID_SWITCH_OBJECT, \LIDS) // Force a read of CPU temperature Store (CTML, Local0) diff --git a/src/ec/compal/ene932/documentation.txt b/src/ec/compal/ene932/documentation.txt new file mode 100644 index 0000000..eeb801a --- /dev/null +++ b/src/ec/compal/ene932/documentation.txt @@ -0,0 +1,23 @@ + +Accessing the EC space +====================== + +The ACPI implementation uses the standard I/O ports 0x62 and 0x66 to access the +EC functionality. Accesses to these ports must be directed to the LPC bus to +which the EC is connected. + + +Interfacing with the ASL files +============================== + +The mainboard code must define several variables for the ASL files. + +* EC_SCI + Defines the General Purpose Event (GPE) corresponding to the EC's SCI line. +* EC_ACPI_LID_SWITCH_OBJECT + Defines the APCI object which reads the state of the lid, with 0 = open, and + 1 = closed. This is usually the bit which reads the GPIO input corresponding + to the lid switch. +* PNOT() + The mainboard must define a PNOT method to handle power state notifications + and Notify CPU device objects to re-evaluate their _PPC and _CST tables. diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 522a0b9..a0ee9d5 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -21,5 +21,8 @@ #include "../ec.h" #define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI +/* GP15 is defined in the southbridge's ASL */ +#define EC_ACPI_LID_SWITCH_OBJECT GP15 + /* ACPI code for EC functions */ #include "../../../../ec/compal/ene932/acpi/ec.asl"

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Patch set updated for coreboot: 8db4510 ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8'
by Alexandru Gagniuc 09 Apr '14

09 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5470 -gerrit commit 8db451084ab50530a81efba8169901dc1da10225 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:48:44 2014 -0500 ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8' Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/ec/compal/ene932/ec.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index 879925f..a1f4544 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -24,6 +24,8 @@ #ifndef _EC_COMPAL_ENE932_EC_H #define _EC_COMPAL_ENE932_EC_H +#include <stdint.h> + #define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */ #define EC_IO_HIGH EC_IO + 1 #define EC_IO_LOW EC_IO + 2

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Patch merged into coreboot/master: c0654cb hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
by gerrit＠coreboot.org 09 Apr '14

09 Apr '14

the following patch was just integrated into master: commit c0654cb1851b6d02f10276541a52a87d0b78e130 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 18:51:33 2014 -0500 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5462 for details. -gerrit

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Patch set updated for coreboot: 6c71bcf jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
by Edward O'Callaghan 09 Apr '14

09 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5472 -gerrit commit 6c71bcf02e929b70c992ee084cbb452c9a1a23f2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 7 14:59:42 2014 +1000 jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio() Follow same reasoning as: 12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio() Use coreboot variants for PCI and MSR access over AGESA's. Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 59 ++++++++++-------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 2 +- 2 files changed, 25 insertions(+), 36 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index e6633f3..1627f25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -26,9 +26,12 @@ #include "BiosCallOuts.h" #include "PlatformGnbPcieComplex.h" +#define __SIMPLE_DEVICE__ + #include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <stdint.h> #include <string.h> @@ -74,53 +77,39 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *------------------------------------------------------------------------------ */ -UINT32 -agesawrapper_amdinitcpuio ( - VOID - ) +uint32_t agesawrapper_amdinitcpuio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + pci_devfn_t dev; + msr_t msr; + uint32_t reg32; + + dev = PCI_DEV(0, 0x18, 1); /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0xf4, 1); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. + * Last address before processor local APIC at FEE00000 */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); + + /* Lowest NP address is HPET at FED00000 */ + pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x8C, 0x00fecf00); + + msr = rdmsr(0xc001001a); + reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ + pci_io_write_config32(dev, 0x88, reg32); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + pci_io_write_config32(dev, 0xc4, 0x0000f000); + pci_io_write_config32(dev, 0xc0, 0x00000003); + + return AGESA_SUCCESS; } UINT32 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index 6544d25..6af5e5f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -82,7 +82,7 @@ UINT32 agesawrapper_amdinitmid (void); UINT32 agesawrapper_amdreadeventlog (void); -UINT32 agesawrapper_amdinitcpuio (void); +uint32_t agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdinitresume (void); UINT32 agesawrapper_amdS3Save (void);

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Patch merged into coreboot/master: 1e5525c supermicro/h8qgi/dsdt: Move _PIC method to root scope
by gerrit＠coreboot.org 09 Apr '14

09 Apr '14

the following patch was just integrated into master: commit 1e5525ca72642677f85512d1b4c885deb784b56f Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Sat Jul 12 09:17:24 2014 +0400 supermicro/h8qgi/dsdt: Move _PIC method to root scope _PIC method should be declared under root scope (\_PIC), otherwise Linux kernel doesn't use it. Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> See http://review.coreboot.org/5478 for details. -gerrit

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Patch merged into coreboot/master: 2dff4a7 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
by gerrit＠coreboot.org 09 Apr '14

09 Apr '14

the following patch was just integrated into master: commit 2dff4a7f1f2e8dfc1999c9ad0bbf5cbaf100f23f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 17:10:31 2014 -0500 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio() TRIVIAL. Rather than using the AGESA functions for PCI and MSR access, use the coreboot variants, which are cleaner and more readable. Change-Id: I4f24820606900e16f0d159df019f4560f1592489 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5468 for details. -gerrit

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New patch to review for coreboot: 3a345be inteltool: Add partial support for H87/C220 chipsets
by Roland A. Lugasi 09 Apr '14

09 Apr '14

Roland A. Lugasi (gaugedev(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5479 -gerrit commit 3a345be23154ed465a774b4e3f6e494d11fbad2e Author: Roland A. Lugasi <gaugedev(a)gmail.com> Date: Wed Apr 9 01:42:20 2014 +0300 inteltool: Add partial support for H87/C220 chipsets inteltool now can dump GPIO, RCBA and PMBASE info from H87 chipsets Change-Id: I28386dddfb59c83c108aced9a12c6095deafcade Signed-off-by: Roland A. Lugasi <gaugedev(a)gmail.com> --- util/inteltool/gpio.c | 8 ++++++++ util/inteltool/inteltool.c | 2 ++ util/inteltool/inteltool.h | 2 ++ util/inteltool/powermgt.c | 5 +++++ util/inteltool/rootcmplx.c | 6 ++++++ 5 files changed, 23 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 42e7272..e49494c 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -459,6 +459,14 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpio_defaults = pp_pch_mobile_defaults; defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; + case PCI_DEVICE_ID_INTEL_C220: + case PCI_DEVICE_ID_INTEL_H87: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = pp_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults); + break; case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich10_gpio_registers; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 219d84e..bbf3092 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -150,6 +150,8 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87, "H87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C220, "C220" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 88008e4..5183fe0 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -108,6 +108,8 @@ #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_C220 0x8c58 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 3bc4efc..200353a 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -689,6 +689,11 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pm_registers = pch_pm_registers; size = ARRAY_SIZE(pch_pm_registers); break; + case PCI_DEVICE_ID_INTEL_H87: + pmbase = pci_read_word(sb, 0x40) & 0xff80; + pm_registers = pch_pm_registers; + size = ARRAY_SIZE(pch_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index f1e902d..850f7c3 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -86,6 +86,8 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_B75: case PCI_DEVICE_ID_INTEL_H77: case PCI_DEVICE_ID_INTEL_C216: + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + break; case PCI_DEVICE_ID_INTEL_QM77: case PCI_DEVICE_ID_INTEL_QS77: case PCI_DEVICE_ID_INTEL_HM77: @@ -95,6 +97,10 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_HM70: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_C220: + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH2:

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New patch to review for coreboot: 1e5525c supermicro/h8qgi/dsdt: Move _PIC method to root scope
by Aladyshev Konstantin 08 Apr '14

08 Apr '14

Aladyshev Konstantin (aladyshev22(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5478 -gerrit commit 1e5525ca72642677f85512d1b4c885deb784b56f Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Sat Jul 12 09:17:24 2014 +0400 supermicro/h8qgi/dsdt: Move _PIC method to root scope _PIC method should be declared under root scope (\_PIC), otherwise Linux kernel doesn't use it. Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> --- src/mainboard/supermicro/h8qgi/dsdt.asl | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index c854067..feb7697 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -448,6 +448,15 @@ DefinitionBlock ( #include "acpi/routing.asl" + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Scope(\_SB) { Method(CkOT, 0){ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ @@ -468,14 +477,6 @@ DefinitionBlock ( Return(OSTP) } - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } Method(CIRQ, 0x00, NotSerialized){ Store(0, PINA) Store(0, PINB)

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Patch set updated for coreboot: cff127b supermicro/h8qgi/dsdt: Use PIC as default interrupt model
by Aladyshev Konstantin 08 Apr '14

08 Apr '14

Aladyshev Konstantin (aladyshev22(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5473 -gerrit commit cff127bef23f7825467583cec9640bf0aba53ec7 Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Sat Jul 12 02:36:32 2014 +0400 supermicro/h8qgi/dsdt: Use PIC as default interrupt model According ACPI specification: """ The \_PIC optional method is used to report to the BIOS the current interrupt model used by the OS. The argument passed into the method signifies the interrupt model OSPM has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the method is never called, the BIOS must assume PIC mode. Arguments: (1) Arg0 – An Integer containing a code for the current interrupt model: 0 –PIC mode 1 –APIC mode 2 –SAPIC mode """ In current configuration with default value of interrupt model PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option. Kernel never call _PIC method and PMOD stays equal 1, indicatind that APIC routing objects should be evaluated. This mix of PIC and APIC leads to boot fail. Change default value of interrupt model PMOD to 0, for correct "noapic" boot. Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> --- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index c854067..b829584 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -57,7 +57,7 @@ DefinitionBlock ( /* Some global data */ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ + Name(PMOD, 0) /* Default interrupt model is PIC */ /* * Processor Object

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New patch to review for coreboot: 7f785a5 superio/ite/it8712f: Make CLKIN prescale a argument
by Edward O'Callaghan 08 Apr '14

08 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5477 -gerrit commit 7f785a57b593ff16d9479bbd5d144a19d710d157 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 8 23:24:17 2014 +1000 superio/ite/it8712f: Make CLKIN prescale a argument Having a argument to a general function instead of a hardcoded function for setting the clockin prescale is slightly more flexable. Change-Id: I2dd7e0c4937bc913313c151daca237d6d1b980e1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/superio/ite/it8712f/early_serial.c | 7 ++++--- src/superio/ite/it8712f/it8712f.h | 6 +++++- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index a1e6590..9ccf384 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - it8712f_24mhz_clkin(CLKIN_DEV); + it8712f_configure_uart_clk(CLKIN_DEV, IT8712F_UART_CLK_PREDIVIDE_24); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 6ba8307..449faa1 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -253,7 +253,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_24mhz_clkin(CLKIN_DEV); + it8712f_configure_uart_clk(CLKIN_DEV, IT8712F_UART_CLK_PREDIVIDE_24); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(WATCHDOG_DEV); console_init(); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 8f5626d..ba17c15 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -38,7 +38,7 @@ void main(unsigned long bist) { - it8712f_24mhz_clkin(CLKIN_DEV); + it8712f_configure_uart_clk(CLKIN_DEV, IT8712F_UART_CLK_PREDIVIDE_24); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 7a7a4b2..2a46235 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -47,17 +47,18 @@ static void pnp_exit_conf_state(device_t dev) pnp_write_config(dev, IT8712F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz is the default). */ /* * in romstage.c * #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) * and pass: CLKIN_DEV + * IT8712F_UART_CLK_PREDIVIDE_24 + * IT8712F_UART_CLK_PREDIVIDE_48 (default) */ -void it8712f_24mhz_clkin(device_t dev) +void it8712f_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - pnp_write_config(dev, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); + pnp_write_config(dev, IT8712F_CONFIG_REG_CLOCKSEL, (predivide << 2) | 1); pnp_exit_conf_state(dev); } diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 06d409d..3cddfd1 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,9 +35,13 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ +/* bit 0 in index 0x23 sets CLKIN Frequency */ +#define IT8712F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8712F_UART_CLK_PREDIVIDE_24 0x01 + void it8712f_kill_watchdog(device_t); void it8712f_enable_serial(device_t dev, u16 iobase); -void it8712f_24mhz_clkin(device_t); +void it8712f_configure_uart_clk(device_t, u8); void it8712f_enable_3vsbsw(device_t); #endif /* SUPERIO_ITE_IT8712F_IT8712F_H */

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coreboot-gerrit April 2014