Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5401
-gerrit
commit e91432c994603f7113d73fd7dcc4da00983a938b
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Mar 23 20:42:02 2014 +1100
mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 7160f33..433336e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -96,7 +96,7 @@ chip northbridge/amd/agesa/family14/root_complex
# $ sudo isadump 0x4e 0x4f 0x7
# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
device pnp 2e.07 off end # BSEL
- device pnp 2e.0a off end # PME
+ device pnp 2e.0a on end # PME
end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5385
-gerrit
commit 7cfd422020db54bd0cc1d130f552d2eb4412b2ab
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Fri Mar 14 01:06:22 2014 +1100
drivers/hwm: Add a generic hwm driver.
Make generic, testing with Fintek Super I/O....
currently wired in to fintek superio, need to move arary of
values to mainboard.c??
Change-Id: Ic7bdea55907e379aad9e74b87b514e8038ef9fd0
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/drivers/Kconfig | 1 +
src/drivers/Makefile.inc | 1 +
src/drivers/hwm/Kconfig | 6 ++
src/drivers/hwm/Makefile.inc | 20 +++++
src/drivers/hwm/superio_hwm.c | 120 ++++++++++++++++++++++++++++++
src/include/hwm/superio_hwm.h | 32 ++++++++
src/mainboard/jetway/nf81-t56n-lf/Kconfig | 4 +
src/superio/fintek/f71869ad/chip.h | 1 +
src/superio/fintek/f71869ad/superio.c | 5 +-
9 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 5267ff8..c09e57f 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig
source src/drivers/elog/Kconfig
source src/drivers/emulation/Kconfig
source src/drivers/generic/Kconfig
+source src/drivers/hwm/Kconfig
source src/drivers/i2c/Kconfig
source src/drivers/ics/Kconfig
source src/drivers/intel/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 197a900..4b944cb 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -39,3 +39,4 @@ subdirs-y += ipmi
subdirs-y += elog
subdirs-y += xpowers
subdirs-$(CONFIG_ARCH_X86) += pc80
+subdirs-$(CONFIG_ARCH_X86) += hwm
diff --git a/src/drivers/hwm/Kconfig b/src/drivers/hwm/Kconfig
new file mode 100644
index 0000000..dc60fd7
--- /dev/null
+++ b/src/drivers/hwm/Kconfig
@@ -0,0 +1,6 @@
+config DRIVERS_SUPERIO_HWM
+ bool "Super I/O HWM"
+ default n
+ help
+ Just enough of a driver to make coreboot control system fans.
+ No configuration is necessary for the OS to pick up the device.
diff --git a/src/drivers/hwm/Makefile.inc b/src/drivers/hwm/Makefile.inc
new file mode 100644
index 0000000..ccb6de0
--- /dev/null
+++ b/src/drivers/hwm/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_DRIVERS_SUPERIO_HWM) += superio_hwm.c
diff --git a/src/drivers/hwm/superio_hwm.c b/src/drivers/hwm/superio_hwm.c
new file mode 100644
index 0000000..fa46a0c
--- /dev/null
+++ b/src/drivers/hwm/superio_hwm.c
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <hwm/superio_hwm.h>
+
+/* Helper functions */
+static void write_index(u16 port, u8 reg, u8 value)
+{
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static u8 read_index(u16 port, u8 reg)
+{
+ outb(reg, port);
+ return inb(port + 1);
+}
+/* .. */
+
+static void init_registers(u16 base, u8 * hwm_reg_values, int size)
+{
+ u8 reg, value;
+ int i;
+
+ for (i = 0; i < size; i += 3) {
+ reg = hwm_reg_values[i];
+ value = read_index(base, reg);
+ value &= 0xff & hwm_reg_values[i + 1];
+ value |= 0xff & hwm_reg_values[i + 2];
+ printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, "
+ "value = 0x%02x\n", base, reg, value);
+ write_index(base, reg, value);
+#if 0
+ value = read_index(base, reg);
+ printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, "
+ "value = 0x%02x\n", base, reg, value);
+#endif
+ }
+}
+
+/* entry point */
+/* Initialize F71869AD hardware monitor registers, which are at 0x225. */
+/* FIXME: make configurable.. i.e. hwm_reg_values passed from mainboard.c somehow?? */
+void superio_enable_hwm(device_t dev)
+{
+ /* return if hwm is disabled in devicetree.cb */
+ struct drivers_superio_hwm_config *config = dev->chip_info;
+ if (!dev->enabled || !config)
+ return;
+
+ u32 hwm_base = config->base;
+
+ printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n"
+ , hwm_base);
+
+ struct resource *res = find_resource(dev, PNP_IDX_IO0);
+ if (!res) {
+ printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base);
+ printk(BIOS_WARNING, "Super I/O HWM: Configuring registers...\n");
+
+ /* Fintek F71869AD AMD mode HWM (ordered) programming sequence. */
+ u8 hwm_reg_values[] = {
+ /* reg mask data */
+ 0x08, 0x00, 0x98, /* SMBus Address p.53 */
+ 0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
+ /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
+ 0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
+ 0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */
+ 0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */
+ 0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
+ 0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */
+ 0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */
+ /* .. */
+ 0x02, 0x00, 0x30, /* OVT_MODE p.52 */
+ 0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */
+ 0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */
+ 0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */
+ 0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */
+ 0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */
+ 0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */
+ 0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */
+ 0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */
+ 0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */
+ 0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */
+ 0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */
+ 0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */
+ /* .. */
+ 0xee, 0x00, 0x01, /* SMB_Status p.83 */
+ 0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */
+ 0xef, 0x00, 0x82, /* SMB_Protocal p.83 */
+ };
+
+ init_registers(res->base, hwm_reg_values, ARRAY_SIZE(hwm_reg_values));
+}
diff --git a/src/include/hwm/superio_hwm.h b/src/include/hwm/superio_hwm.h
new file mode 100644
index 0000000..b5753b2
--- /dev/null
+++ b/src/include/hwm/superio_hwm.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef DRIVERS_SUPERIO_HWM_H
+#define DRIVERS_SUPERIO_HWM_H
+
+#include <device/device.h>
+
+/* Initialization parameters?? */
+typedef struct drivers_superio_hwm_config {
+ u32 base;
+} hwm_config_t;
+
+void superio_enable_hwm(device_t dev);
+
+#endif /* DRIVERS_SUPERIO_HWM_H */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index 6fbd75c..49a76f9 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -113,4 +113,8 @@ config DRIVERS_PS2_KEYBOARD
bool
default y
+config DRIVERS_SUPERIO_HWM
+ bool
+ default y
+
endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h
index 5b18c33..fe5be17 100644
--- a/src/superio/fintek/f71869ad/chip.h
+++ b/src/superio/fintek/f71869ad/chip.h
@@ -21,6 +21,7 @@
#ifndef SUPERIO_FINTEK_F71869AD_CHIP_H
#define SUPERIO_FINTEK_F71869AD_CHIP_H
+#include <hwm/superio_hwm.h>
#include <pc80/keyboard.h>
#include <device/device.h>
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
index 2c1b9b2..65a73ca 100644
--- a/src/superio/fintek/f71869ad/superio.c
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -92,6 +92,9 @@ static void f71869ad_init(device_t dev)
switch(dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
+ case F71869AD_HWM:
+ superio_enable_hwm(dev);
+ break;
case F71869AD_KBC:
pc_keyboard_init(&conf->keyboard);
break;
@@ -164,7 +167,7 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
- { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+ { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_WDT, PNP_IO0, {0x07f8, 0}, },
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5403
-gerrit
commit bacc48762d8cedb5ed028379e9d86931c79515cc
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Mon Mar 24 00:42:36 2014 +0100
libpayload/libc/hexdump.c: Take `const void *memory` as argument
`*memory` is not changed in `hexdump()` and just read so make it
`const`.
Change-Id: I9504d25ab5c785f05c39c9a4f48c21f68659a829
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
payloads/libpayload/include/libpayload.h | 2 +-
payloads/libpayload/libc/hexdump.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 8a0d915..e77c2af 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -294,7 +294,7 @@ long int labs(long int j);
long long int llabs(long long int j);
u8 bin2hex(u8 b);
u8 hex2bin(u8 h);
-void hexdump(void *memory, size_t length);
+void hexdump(const void *memory, size_t length);
void fatal(const char *msg) __attribute__ ((noreturn));
/** @} */
diff --git a/payloads/libpayload/libc/hexdump.c b/payloads/libpayload/libc/hexdump.c
index e33a306..d2953a5 100644
--- a/payloads/libpayload/libc/hexdump.c
+++ b/payloads/libpayload/libc/hexdump.c
@@ -29,7 +29,7 @@
#include <libpayload.h>
-void hexdump(void *memory, size_t length)
+void hexdump(const void *memory, size_t length)
{
int i;
uint8_t *m;
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5402
-gerrit
commit b6a081b0238e59c3e3ed51eed5f0d86a18234d9a
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Mar 23 23:35:40 2014 +0100
NOTFORMERGE: Build boards without selecting Chrome OS
Change-Id: I4212d3fe6c5c84e58315d455332ede6cc46fe978
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/vendorcode/google/chromeos/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index ed358f8..176ec3f 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -24,7 +24,7 @@ menu "ChromeOS"
config CHROMEOS
bool "Build for ChromeOS"
- default y
+ default n
select TPM
help
Enable ChromeOS specific features like the GPIO sub table in
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5398
-gerrit
commit df5ab133b7e692650bb936c2f9d2b8f1f4f82e85
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Mar 23 00:09:32 2014 +0100
mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
When not selecting the Kconfig option CHROMEOS, compilation of the board
SAMSUNG Lumpy fails as the included header file uses `chromeos_acpi_t`,
which is not known to the compiler when not building with support for
Chrome OS.
In file included from src/mainboard/samsung/lumpy/ec.c:21:0:
src/vendorcode/google/chromeos/chromeos.h:65:43: error: unknown type name 'chromeos_acpi_t'
Luckily, nothing from the header `chromeos.h` is used in `ec.c`, which
was probably the case for the board the file was copied from, so do
not include it at all.
Looking further the header is included since commit
6651da3b Add support for Intel Emerald Lake 2 CRB
and is not needed there either and was copied over from then on. So
remove it for all boards using the following command.
$ find src/mainboard/ -name 'ec.c' | xargs sed -i '/chromeos.h/d'
Revert the change for Google Stout as `get_recovery_mode_switch()` is
declared in `chromeos/chromeos.h`.
Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
Reported-by: Idwer Vollering <vidwer(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/google/bolt/ec.c | 1 -
src/mainboard/google/falco/ec.c | 1 -
src/mainboard/google/link/ec.c | 1 -
src/mainboard/google/parrot/ec.c | 1 -
src/mainboard/google/peppy/ec.c | 1 -
src/mainboard/google/rambi/ec.c | 1 -
src/mainboard/google/slippy/ec.c | 1 -
src/mainboard/intel/emeraldlake2/ec.c | 1 -
src/mainboard/samsung/lumpy/ec.c | 1 -
9 files changed, 9 deletions(-)
diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c
index 0919f0f..04a9931 100644
--- a/src/mainboard/google/bolt/ec.c
+++ b/src/mainboard/google/bolt/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c
index 0919f0f..04a9931 100644
--- a/src/mainboard/google/falco/ec.c
+++ b/src/mainboard/google/falco/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c
index 07da080..7dfadeb 100644
--- a/src/mainboard/google/link/ec.c
+++ b/src/mainboard/google/link/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c
index e6d2d38..56f7d80 100644
--- a/src/mainboard/google/parrot/ec.c
+++ b/src/mainboard/google/parrot/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c
index 0919f0f..04a9931 100644
--- a/src/mainboard/google/peppy/ec.c
+++ b/src/mainboard/google/peppy/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c
index 0919f0f..04a9931 100644
--- a/src/mainboard/google/rambi/ec.c
+++ b/src/mainboard/google/rambi/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c
index 0919f0f..04a9931 100644
--- a/src/mainboard/google/slippy/ec.c
+++ b/src/mainboard/google/slippy/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c
index ac37b0b..b50ab65 100644
--- a/src/mainboard/intel/emeraldlake2/ec.c
+++ b/src/mainboard/intel/emeraldlake2/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/smsc/mec1308/ec.h>
diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c
index 40d8319..2406012 100644
--- a/src/mainboard/samsung/lumpy/ec.c
+++ b/src/mainboard/samsung/lumpy/ec.c
@@ -18,7 +18,6 @@
*/
#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/smsc/mec1308/ec.h>
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5395
-gerrit
commit 21e639ff4d60e20a90e12387b19aee076cfe405d
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Tue Mar 18 14:55:00 2014 +1100
mainboard/jetway/nf81-t56n-lf: Turn on SB800 superio hwm chit-chat.
Hidden away inside amd/sb800 there is some support for talking to
the Super I/O's HWM. Be sure to set it up with the correct HWM BAR.
Change-Id: I9e229686f939b5609e79f1eb363f985fdcef0eb1
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 +
src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index 6fbd75c..2d0272f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
+ select SB_SUPERIO_HWM
select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index ce08bee..35769df 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -257,4 +257,9 @@ static const CODECTBLLIST codec_tablelist[] =
*/
#define FADT_PM_PROFILE 1
+/**
+ * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
+ */
+#define SIO_HWM_BASE_ADDRESS 0x225
+
#endif /* _PLATFORM_CFG_H_ */
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5401
-gerrit
commit eaecdd523930577c6f89696b1e4bfbe5ba3831ef
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Mar 23 20:42:02 2014 +1100
mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 7160f33..433336e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -96,7 +96,7 @@ chip northbridge/amd/agesa/family14/root_complex
# $ sudo isadump 0x4e 0x4f 0x7
# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
device pnp 2e.07 off end # BSEL
- device pnp 2e.0a off end # PME
+ device pnp 2e.0a on end # PME
end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}