coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

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584 discussions

Patch set updated for coreboot: 3b85eca superio/fintek/f71869ad: Setup SMBus correctly.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5400 -gerrit commit 3b85eca4abe95536900f938036962aebc143970b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 23 20:37:09 2014 +1100 superio/fintek/f71869ad: Setup SMBus correctly. Fintek Super I/O has "mutli-function selection registers" that need tweaking before the Super I/O will talk to SB. Change-Id: I28489c183d9d2c379a0488ec5709bbf184ba6853 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71869ad/superio.c | 57 ++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 9325bac..2c1b9b2 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -28,6 +28,61 @@ #include "chip.h" #include "f71869ad.h" +static void toggle_clk_tune_en(device_t dev, int state) +{ + u8 reg8; + + reg8 = pnp_read_config(dev, 0x26); + + switch(state) { + case 1: + reg8 ^= 0x08; /* CLK_TUNE_EN=1 */ + break; + case 0: + reg8 &= 0xF7; /* CLK_TUNE_EN=0 */ + break; + } + + pnp_write_config(dev, 0x26, reg8); +} + +static void enable_hwm_smbus(device_t dev) +{ + pnp_write_config(dev, 0x25, 0x09); // powerdown FDC & PP + pnp_write_config(dev, 0x27, 0xa1); // debug+timing_gpio + pnp_write_config(dev, 0x28, 0x01); // multi-func select reg1 + + /* CLK_TUNE_EN switch index 0x29 ~ 0x2C to WDT fine tune registers */ + toggle_clk_tune_en(dev, 1); /* CLK_TUNE_EN=1 */ + pnp_write_config(dev, 0x29, 0x6f); // WDT clock divisor high byte (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2a, 0x24); // WDT clock divisor low byte (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2b, 0x00); // WDT clock fine tune count (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2b, 0x60); // WDT clock fine tune count (CLK_TUNE_EN=1) + /* CLK_TUNE_EN switch index 0x29 ~ 0x2C from WDT fine tune registers */ + toggle_clk_tune_en(dev, 0); /* CLK_TUNE_EN=0 */ + + pnp_write_config(dev, 0x29, 0x6f); // multi-func select reg2 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2a, 0x24); // multi-func select reg3 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2b, 0x00); // multi-func select reg4 (CLK_TUNE_EN=0) + /* multi-func sel reg5 - Configure pins 57/58 as SCL/SDA (AMD TSI bus). */ + pnp_write_config(dev, 0x2c, 0x60); // multi-func select reg5 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2f, 0x2f); // wakeup control register +} + +static void f71869ad_pnp_enable_resources(device_t dev) +{ + pnp_enable_resources(dev); + + pnp_enter_conf_mode(dev); + switch(dev->path.pnp.device) { + case F71869AD_HWM: + printk(BIOS_DEBUG, "F71869AD HWM SMBus enabled\n"); + enable_hwm_smbus(dev); + break; + } + pnp_exit_conf_mode(dev); +} + static void f71869ad_init(device_t dev) { struct superio_fintek_f71869ad_config *conf = dev->chip_info; @@ -46,7 +101,7 @@ static void f71869ad_init(device_t dev) static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, + .enable_resources = f71869ad_pnp_enable_resources, .enable = pnp_alt_enable, .init = f71869ad_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa,

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Patch set updated for coreboot: 1bcbe04 drivers/hwm: Add a generic hwm driver.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5385 -gerrit commit 1bcbe04dcfabb63a84ca34dd791149c558cd3783 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Mar 14 01:06:22 2014 +1100 drivers/hwm: Add a generic hwm driver. Make generic, testing with Fintek Super I/O.... currently wired in to fintek superio, need to move arary of values to mainboard.c?? Change-Id: Ic7bdea55907e379aad9e74b87b514e8038ef9fd0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/hwm/Kconfig | 6 ++ src/drivers/hwm/Makefile.inc | 20 +++++ src/drivers/hwm/superio_hwm.c | 145 ++++++++++++++++++++++++++++++ src/include/hwm/superio_hwm.h | 32 +++++++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 4 + src/superio/fintek/f71869ad/chip.h | 1 + src/superio/fintek/f71869ad/superio.c | 5 +- 9 files changed, 214 insertions(+), 1 deletion(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..c09e57f 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig source src/drivers/elog/Kconfig source src/drivers/emulation/Kconfig source src/drivers/generic/Kconfig +source src/drivers/hwm/Kconfig source src/drivers/i2c/Kconfig source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..4b944cb 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -39,3 +39,4 @@ subdirs-y += ipmi subdirs-y += elog subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 +subdirs-$(CONFIG_ARCH_X86) += hwm diff --git a/src/drivers/hwm/Kconfig b/src/drivers/hwm/Kconfig new file mode 100644 index 0000000..dc60fd7 --- /dev/null +++ b/src/drivers/hwm/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_SUPERIO_HWM + bool "Super I/O HWM" + default n + help + Just enough of a driver to make coreboot control system fans. + No configuration is necessary for the OS to pick up the device. diff --git a/src/drivers/hwm/Makefile.inc b/src/drivers/hwm/Makefile.inc new file mode 100644 index 0000000..ccb6de0 --- /dev/null +++ b/src/drivers/hwm/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_DRIVERS_SUPERIO_HWM) += superio_hwm.c diff --git a/src/drivers/hwm/superio_hwm.c b/src/drivers/hwm/superio_hwm.c new file mode 100644 index 0000000..720ac5e --- /dev/null +++ b/src/drivers/hwm/superio_hwm.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all Fintek Super I/O HWM's. */ +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <hwm/superio_hwm.h> + +/* Helper functions */ +static void write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +static u8 read_index(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} +/* .. */ + +/* Initialize F71869AD hardware monitor registers, which are at 0x225. */ +/* XXX: make configurable.. */ +static void init_registers(u16 base) +{ + u8 reg, value; + int i; + + /* XXX: work out correct values??? */ + u8 hwm_reg_values[] = { + /* reg mask data */ + 0x08, 0x00, 0x98, /* SMBus Address p.53 */ + 0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + 0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + 0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */ + 0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + 0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + 0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ + 0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */ + /* .. */ + 0x02, 0x00, 0x30, /* OVT_MODE p.52 */ + 0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */ + 0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */ + 0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */ + 0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */ + 0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */ + 0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */ + 0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */ + 0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */ + 0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */ + 0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */ + 0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */ + 0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */ + /* ..? */ + 0xee, 0x00, 0x01, /* SMB_Status p.83 */ + 0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */ + 0xef, 0x00, 0x82, /* SMB_Protocal p.83 */ + }; + + for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { + reg = hwm_reg_values[i]; + value = read_index(base, reg); + value &= 0xff & hwm_reg_values[i + 1]; + value |= 0xff & hwm_reg_values[i + 2]; + printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + write_index(base, reg, value); + value = read_index(base, reg); + printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + } +} +/* .. */ + +/* Main driver */ +void hwm_init(device_t dev) +{ + if (!CONFIG_DRIVERS_SUPERIO_HWM) + return; + + /* return if hwm is disabled in devicetree.cb */ + struct drivers_superio_hwm_config *config = dev->chip_info; + if (!dev->enabled || !config) + return; + + u32 hwm_base = config->base; + + printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n" + , hwm_base); + + struct resource *res = find_resource(dev, PNP_IDX_IO0); + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base); + printk(BIOS_WARNING, "Super I/O HWM: Configuring registers...\n"); + init_registers(res->base); +} + +/* +static void hwm_noop(device_t dummy) +{ +} + +static struct device_operations hwm_ops = { + .read_resources = hwm_noop, + .set_resources = hwm_noop, + .enable_resources = hwm_noop, + .init = hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &hwm_ops; +} + +struct chip_operations hwm_fintek_ops = { + CHIP_NAME("Super I/O Hardware Monitor.") + .enable_dev = enable_dev +}; +*/ diff --git a/src/include/hwm/superio_hwm.h b/src/include/hwm/superio_hwm.h new file mode 100644 index 0000000..49e431c --- /dev/null +++ b/src/include/hwm/superio_hwm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DRIVERS_SUPERIO_HWM_H +#define DRIVERS_SUPERIO_HWM_H + +#include <device/device.h> + +/* Initialization parameters?? */ +typedef struct drivers_superio_hwm_config { + u32 base; +} hwm_config_t; + +void hwm_init(device_t dev); + +#endif /* DRIVERS_SUPERIO_HWM_H */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 2d0272f..dd0b528 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -114,4 +114,8 @@ config DRIVERS_PS2_KEYBOARD bool default y +config DRIVERS_SUPERIO_HWM + bool + default y + endif # BOARD_JETWAY_NF81_T56N_LF diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..fe5be17 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -21,6 +21,7 @@ #ifndef SUPERIO_FINTEK_F71869AD_CHIP_H #define SUPERIO_FINTEK_F71869AD_CHIP_H +#include <hwm/superio_hwm.h> #include <pc80/keyboard.h> #include <device/device.h> diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 2c1b9b2..750ba82 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -92,6 +92,9 @@ static void f71869ad_init(device_t dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ + case F71869AD_HWM: + hwm_init(dev); + break; case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; @@ -164,7 +167,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_WDT, PNP_IO0, {0x07f8, 0}, },

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New patch to review for coreboot: ca986c8 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5401 -gerrit commit ca986c8c0d9b0e8cfbb54cc615bc83de5628ca58 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 23 20:42:02 2014 +1100 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 7160f33..433336e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -96,7 +96,7 @@ chip northbridge/amd/agesa/family14/root_complex # $ sudo isadump 0x4e 0x4f 0x7 # which select logical device (LDN) 7. Then read that we have in 0x27, bit1 device pnp 2e.07 off end # BSEL - device pnp 2e.0a off end # PME + device pnp 2e.0a on end # PME end # f71869ad end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}

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New patch to review for coreboot: ecd1c55 superio/fintek/f71869ad: Setup SMBus correctly.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5400 -gerrit commit ecd1c558558fb08633fb4654313d891da9ee4df7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 23 20:37:09 2014 +1100 superio/fintek/f71869ad: Setup SMBus correctly. Fintek superio has "mutli-function selection registers" that need weaking before the Super I/O will talk to SB. Change-Id: I28489c183d9d2c379a0488ec5709bbf184ba6853 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71869ad/superio.c | 57 ++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index c71298c..750ba82 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -28,6 +28,61 @@ #include "chip.h" #include "f71869ad.h" +static void toggle_clk_tune_en(device_t dev, int state) +{ + u8 reg8; + + reg8 = pnp_read_config(dev, 0x26); + + switch(state) { + case 1: + reg8 ^= 0x08; /* CLK_TUNE_EN=1 */ + break; + case 0: + reg8 &= 0xF7; /* CLK_TUNE_EN=0 */ + break; + } + + pnp_write_config(dev, 0x26, reg8); +} + +static void enable_hwm_smbus(device_t dev) +{ + pnp_write_config(dev, 0x25, 0x09); // powerdown FDC & PP + pnp_write_config(dev, 0x27, 0xa1); // debug+timing_gpio + pnp_write_config(dev, 0x28, 0x01); // multi-func select reg1 + + /* CLK_TUNE_EN switch index 0x29 ~ 0x2C to WDT fine tune registers */ + toggle_clk_tune_en(dev, 1); /* CLK_TUNE_EN=1 */ + pnp_write_config(dev, 0x29, 0x6f); // WDT clock divisor high byte (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2a, 0x24); // WDT clock divisor low byte (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2b, 0x00); // WDT clock fine tune count (CLK_TUNE_EN=1) + pnp_write_config(dev, 0x2b, 0x60); // WDT clock fine tune count (CLK_TUNE_EN=1) + /* CLK_TUNE_EN switch index 0x29 ~ 0x2C from WDT fine tune registers */ + toggle_clk_tune_en(dev, 0); /* CLK_TUNE_EN=0 */ + + pnp_write_config(dev, 0x29, 0x6f); // multi-func select reg2 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2a, 0x24); // multi-func select reg3 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2b, 0x00); // multi-func select reg4 (CLK_TUNE_EN=0) + /* multi-func sel reg5 - Configure pins 57/58 as SCL/SDA (AMD TSI bus). */ + pnp_write_config(dev, 0x2c, 0x60); // multi-func select reg5 (CLK_TUNE_EN=0) + pnp_write_config(dev, 0x2f, 0x2f); // wakeup control register +} + +static void f71869ad_pnp_enable_resources(device_t dev) +{ + pnp_enable_resources(dev); + + pnp_enter_conf_mode(dev); + switch(dev->path.pnp.device) { + case F71869AD_HWM: + printk(BIOS_DEBUG, "F71869AD HWM SMBus enabled\n"); + enable_hwm_smbus(dev); + break; + } + pnp_exit_conf_mode(dev); +} + static void f71869ad_init(device_t dev) { struct superio_fintek_f71869ad_config *conf = dev->chip_info; @@ -49,7 +104,7 @@ static void f71869ad_init(device_t dev) static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, + .enable_resources = f71869ad_pnp_enable_resources, .enable = pnp_alt_enable, .init = f71869ad_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa,

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New patch to review for coreboot: beed7eb superio/fintek/f71869ad: Fix WDT miss-naming.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5399 -gerrit commit beed7eb5c53585148109d9a78bbc9e3318085764 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 23 04:39:40 2014 +1100 superio/fintek/f71869ad: Fix WDT miss-naming. NOTFORMERGE yet. Change-Id: Ibe20515a5b348a32dc3e956b319aa34a398b67b4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71869ad/f71869ad.h | 2 +- src/superio/fintek/f71869ad/superio.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index abc0260..5947b32 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -29,7 +29,7 @@ #define F71869AD_HWM 0x04 /* Hardware monitor */ #define F71869AD_KBC 0x05 /* PS/2 keyboard and mouse */ #define F71869AD_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71869AD_BSEL 0x07 /* BSEL */ +#define F71869AD_WDT 0x07 /* WDT */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ void f71869ad_enable_serial(device_t dev, u16 iobase); diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 3c2a303..c71298c 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -102,7 +102,7 @@ static struct device_operations ops = { * irq 0x72 = 12 # Mouse IRQ * end * device pnp 4e.06 off end # GPIO - * device pnp 4e.07 on end # BSEL + * device pnp 4e.07 on end # WDT * device pnp 4e.0a off end # PME * end # f71869ad * @@ -115,7 +115,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, }, + { &ops, F71869AD_WDT, PNP_IO0, {0x07f8, 0}, }, { &ops, F71869AD_PME, }, };

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Patch set updated for coreboot: 08e690b mainboard/jetway/nf81-t56n-lf: Turn on SB800 superio hwm chit-chat.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5395 -gerrit commit 08e690b41b2de7f4a357287ae4a1657d48cab032 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Mar 18 14:55:00 2014 +1100 mainboard/jetway/nf81-t56n-lf: Turn on SB800 superio hwm chit-chat. Hidden away inside amd/sb800 there is some support for talking to the Super I/O's HWM. Be sure to set it up with the correct HWM BAR. Change-Id: I9e229686f939b5609e79f1eb363f985fdcef0eb1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 + src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 6fbd75c..2d0272f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 + select SB_SUPERIO_HWM select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index ce08bee..35769df 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -257,4 +257,9 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1 +/** + * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + */ +#define SIO_HWM_BASE_ADDRESS 0x225 + #endif /* _PLATFORM_CFG_H_ */

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Patch set updated for coreboot: 21ba706 jetway/nf81-t56n-lf: fix GPIO's
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5389 -gerrit commit 21ba7068a451646df1305e54fec07c360c303edf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 16:30:59 2014 +1100 jetway/nf81-t56n-lf: fix GPIO's NOTFORMERGE. Change-Id: I2173c0e454ddc0a30e023976bdf4764d951ea5f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 ++++- src/superio/fintek/f71869ad/superio.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 5f49b41..7160f33 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -88,7 +88,10 @@ chip northbridge/amd/agesa/family14/root_complex irq 0x70 = 1 # Keyboard IRQ irq 0x72 = 12 # Mouse IRQ end - device pnp 2e.06 off end # GPIO + device pnp 2e.06 on # GPIO + io 0x60 = 0xa00 + irq 0x70 = 0 + end # TODO: Verify BSEL register content with vendor BIOS using # $ sudo isadump 0x4e 0x4f 0x7 # which select logical device (LDN) 7. Then read that we have in 0x27, bit1 diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..dbcb812 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -111,7 +111,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, - { &ops, F71869AD_GPIO, }, + { &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, }, { &ops, F71869AD_PME, }, };

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Patch set updated for coreboot: 8eb26e4 drivers/hwm: Add a generic hwm driver.
by Edward O'Callaghan 23 Mar '14

23 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5385 -gerrit commit 8eb26e466f95631d09a2bf1aa10e9113dd081fe0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Mar 14 01:06:22 2014 +1100 drivers/hwm: Add a generic hwm driver. Make generic, testing with Fintek Super I/O.... currently wired in to fintek superio, need to move arary of values to mainboard.c?? Change-Id: Ic7bdea55907e379aad9e74b87b514e8038ef9fd0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/hwm/Kconfig | 6 ++ src/drivers/hwm/Makefile.inc | 20 +++++ src/drivers/hwm/superio_hwm.c | 145 ++++++++++++++++++++++++++++++ src/include/hwm/superio_hwm.h | 32 +++++++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 4 + src/superio/fintek/f71869ad/chip.h | 1 + src/superio/fintek/f71869ad/superio.c | 5 +- 9 files changed, 214 insertions(+), 1 deletion(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..c09e57f 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig source src/drivers/elog/Kconfig source src/drivers/emulation/Kconfig source src/drivers/generic/Kconfig +source src/drivers/hwm/Kconfig source src/drivers/i2c/Kconfig source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..4b944cb 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -39,3 +39,4 @@ subdirs-y += ipmi subdirs-y += elog subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 +subdirs-$(CONFIG_ARCH_X86) += hwm diff --git a/src/drivers/hwm/Kconfig b/src/drivers/hwm/Kconfig new file mode 100644 index 0000000..dc60fd7 --- /dev/null +++ b/src/drivers/hwm/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_SUPERIO_HWM + bool "Super I/O HWM" + default n + help + Just enough of a driver to make coreboot control system fans. + No configuration is necessary for the OS to pick up the device. diff --git a/src/drivers/hwm/Makefile.inc b/src/drivers/hwm/Makefile.inc new file mode 100644 index 0000000..ccb6de0 --- /dev/null +++ b/src/drivers/hwm/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_DRIVERS_SUPERIO_HWM) += superio_hwm.c diff --git a/src/drivers/hwm/superio_hwm.c b/src/drivers/hwm/superio_hwm.c new file mode 100644 index 0000000..720ac5e --- /dev/null +++ b/src/drivers/hwm/superio_hwm.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all Fintek Super I/O HWM's. */ +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <hwm/superio_hwm.h> + +/* Helper functions */ +static void write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +static u8 read_index(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} +/* .. */ + +/* Initialize F71869AD hardware monitor registers, which are at 0x225. */ +/* XXX: make configurable.. */ +static void init_registers(u16 base) +{ + u8 reg, value; + int i; + + /* XXX: work out correct values??? */ + u8 hwm_reg_values[] = { + /* reg mask data */ + 0x08, 0x00, 0x98, /* SMBus Address p.53 */ + 0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + 0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + 0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */ + 0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + 0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + 0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ + 0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */ + /* .. */ + 0x02, 0x00, 0x30, /* OVT_MODE p.52 */ + 0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */ + 0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */ + 0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */ + 0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */ + 0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */ + 0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */ + 0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */ + 0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */ + 0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */ + 0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */ + 0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */ + 0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */ + /* ..? */ + 0xee, 0x00, 0x01, /* SMB_Status p.83 */ + 0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */ + 0xef, 0x00, 0x82, /* SMB_Protocal p.83 */ + }; + + for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { + reg = hwm_reg_values[i]; + value = read_index(base, reg); + value &= 0xff & hwm_reg_values[i + 1]; + value |= 0xff & hwm_reg_values[i + 2]; + printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + write_index(base, reg, value); + value = read_index(base, reg); + printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + } +} +/* .. */ + +/* Main driver */ +void hwm_init(device_t dev) +{ + if (!CONFIG_DRIVERS_SUPERIO_HWM) + return; + + /* return if hwm is disabled in devicetree.cb */ + struct drivers_superio_hwm_config *config = dev->chip_info; + if (!dev->enabled || !config) + return; + + u32 hwm_base = config->base; + + printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n" + , hwm_base); + + struct resource *res = find_resource(dev, PNP_IDX_IO0); + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base); + printk(BIOS_WARNING, "Super I/O HWM: Configuring registers...\n"); + init_registers(res->base); +} + +/* +static void hwm_noop(device_t dummy) +{ +} + +static struct device_operations hwm_ops = { + .read_resources = hwm_noop, + .set_resources = hwm_noop, + .enable_resources = hwm_noop, + .init = hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &hwm_ops; +} + +struct chip_operations hwm_fintek_ops = { + CHIP_NAME("Super I/O Hardware Monitor.") + .enable_dev = enable_dev +}; +*/ diff --git a/src/include/hwm/superio_hwm.h b/src/include/hwm/superio_hwm.h new file mode 100644 index 0000000..49e431c --- /dev/null +++ b/src/include/hwm/superio_hwm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DRIVERS_SUPERIO_HWM_H +#define DRIVERS_SUPERIO_HWM_H + +#include <device/device.h> + +/* Initialization parameters?? */ +typedef struct drivers_superio_hwm_config { + u32 base; +} hwm_config_t; + +void hwm_init(device_t dev); + +#endif /* DRIVERS_SUPERIO_HWM_H */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 2d0272f..dd0b528 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -114,4 +114,8 @@ config DRIVERS_PS2_KEYBOARD bool default y +config DRIVERS_SUPERIO_HWM + bool + default y + endif # BOARD_JETWAY_NF81_T56N_LF diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..fe5be17 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -21,6 +21,7 @@ #ifndef SUPERIO_FINTEK_F71869AD_CHIP_H #define SUPERIO_FINTEK_F71869AD_CHIP_H +#include <hwm/superio_hwm.h> #include <pc80/keyboard.h> #include <device/device.h> diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index dbcb812..3c2a303 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -37,6 +37,9 @@ static void f71869ad_init(device_t dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ + case F71869AD_HWM: + hwm_init(dev); + break; case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; @@ -109,7 +112,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, },

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Patch set updated for coreboot: 201c486 mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
by Paul Menzel 23 Mar '14

23 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5398 -gerrit commit 201c48658bf692298c549488f74550b4f7c426a1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 23 00:09:32 2014 +0100 mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h` When not selecting the Kconfig option CHROMEOS, compilation of the board SAMSUNG Lumpy fails as the included header file uses `chromeos_acpi_t`, which is not known to the compiler when not building with support for Chrome OS. In file included from src/mainboard/samsung/lumpy/ec.c:21:0: src/vendorcode/google/chromeos/chromeos.h:65:43: error: unknown type name 'chromeos_acpi_t' Luckily, nothing from the header `chromeos.h` is used in `ec.c`, which was probably the case for the board the file was copied from, so do not include it at all. Looking further the header is included since commit 6651da3b Add support for Intel Emerald Lake 2 CRB and is not needed there either and was copied over from then on. So remove it for all boards using the following command. $ find src/mainboard/ -name 'ec.c' | xargs sed -i '/chromeos.h/d' Revert the change for Google Stout as `get_recovery_mode_switch()` is declared `chromeos/chromeos.h`. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/bolt/ec.c | 1 - src/mainboard/google/falco/ec.c | 1 - src/mainboard/google/link/ec.c | 1 - src/mainboard/google/parrot/ec.c | 1 - src/mainboard/google/peppy/ec.c | 1 - src/mainboard/google/rambi/ec.c | 1 - src/mainboard/google/slippy/ec.c | 1 - src/mainboard/google/stout/ec.c | 1 - src/mainboard/intel/emeraldlake2/ec.c | 1 - src/mainboard/samsung/lumpy/ec.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/bolt/ec.c +++ b/src/mainboard/google/bolt/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/falco/ec.c +++ b/src/mainboard/google/falco/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 07da080..7dfadeb 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index e6d2d38..56f7d80 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/peppy/ec.c +++ b/src/mainboard/google/peppy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..91e139c 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/quanta/it8518/ec.h> diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index ac37b0b..b50ab65 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 40d8319..2406012 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h>

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Patch set updated for coreboot: 73c49dd mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
by Paul Menzel 23 Mar '14

23 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5398 -gerrit commit 73c49ddfe9110339b9c5622bea52a2a1ef3fc3cb Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 23 00:09:32 2014 +0100 mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h` When not selecting the Kconfig option CHROMEOS, compilation of the board SAMSUNG Lumpy fails as the included header file uses `chromeos_acpi_t`, which is not known to the compiler when not building with support for Chrome OS. In file included from src/mainboard/samsung/lumpy/ec.c:21:0: src/vendorcode/google/chromeos/chromeos.h:65:43: error: unknown type name 'chromeos_acpi_t' Luckily, nothing from the header `chromeos.h` is used in `ec.c`, which was probably the case for the board the file was copied from, so do not include it at all. Looking further the header is included since commit 6651da3b Add support for Intel Emerald Lake 2 CRB and is not needed there either and was copied over from then on. So remove it for all boards using the following command. $ find src/mainboard/ -name 'ec.c' | xargs sed -i '/chromeos.h/d' Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/bolt/ec.c | 1 - src/mainboard/google/falco/ec.c | 1 - src/mainboard/google/link/ec.c | 1 - src/mainboard/google/parrot/ec.c | 1 - src/mainboard/google/peppy/ec.c | 1 - src/mainboard/google/rambi/ec.c | 1 - src/mainboard/google/slippy/ec.c | 1 - src/mainboard/google/stout/ec.c | 1 - src/mainboard/intel/emeraldlake2/ec.c | 1 - src/mainboard/samsung/lumpy/ec.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/bolt/ec.c +++ b/src/mainboard/google/bolt/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/falco/ec.c +++ b/src/mainboard/google/falco/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 07da080..7dfadeb 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index e6d2d38..56f7d80 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/peppy/ec.c +++ b/src/mainboard/google/peppy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..91e139c 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/quanta/it8518/ec.h> diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index ac37b0b..b50ab65 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 40d8319..2406012 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h>

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coreboot-gerrit March 2014