coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

1 participants
584 discussions

New patch to review for coreboot: fc8dca2 samsung/lumpy/ec.c: Do not include `chromeos/chromeos.h`
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5398 -gerrit commit fc8dca201c65d30c3786f973d470035e6b29ac74 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 23 00:09:32 2014 +0100 samsung/lumpy/ec.c: Do not include `chromeos/chromeos.h` When not selecting the Kconfig option CHROMEOS, compilation of the board SAMSUNG Lumpy fails as the included header file uses `chromeos_acpi_t`, which is not known to the compiler when not building with support for Chrome OS. In file included from src/mainboard/samsung/lumpy/ec.c:21:0: src/vendorcode/google/chromeos/chromeos.h:65:43: error: unknown type name 'chromeos_acpi_t' Luckily, nothing from the header `chromeos.h` is used in `ec.c`, which was probably the case for the board the file was copied from, so do not include it at all. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/samsung/lumpy/ec.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 40d8319..2406012 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h>

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Patch set updated for coreboot: ad715be asrock/e350m1/mainboard.c: Disable GPP CLK4 through SLT_GFX_CLK
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397 -gerrit commit ad715be5ccbadb5636a8005d118e10848498081e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 22 23:22:29 2014 +0100 asrock/e350m1/mainboard.c: Disable GPP CLK4 through SLT_GFX_CLK According to Edward this might fix the problems with the Ethernet device not showing up sometimes, when the PSU is not turned off during restarts or shut down and start. According to the SB800 Register Reference Guide [1] the clock pins are powered on (0xFF) by default. Powering off the clock pins for GPP4 to GPP8 and the Gfx PCIe device, hopefully sets the Ethernet device up correctly, so it is always detected during start up. Similar to the one applied to AMD Persimmon in [2]. [1] AMD SB800-Series Southbridges Register Reference Guide Publication: #45482 Revision: 3.04 [2] http://review.coreboot.org/1876 Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..56f3696 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,8 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/cimx/cimx_util.h> +#include <agesawrapper.h> +#include "SBPLATFORM.h" //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); @@ -54,6 +56,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + *(misc_mem_clk_cntrl + 0) = 0xFF; + *(misc_mem_clk_cntrl + 1) = 0xFF; + *(misc_mem_clk_cntrl + 2) = 0x00; + *(misc_mem_clk_cntrl + 3) = 0x00; + *(misc_mem_clk_cntrl + 4) = 0x00; + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The

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Patch set updated for coreboot: 39bf208 asrock/e350m1/mainboard.c: Disable GPP CLK0 through SLT_GFX_CLK
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397 -gerrit commit 39bf208b388b10a51ad96067126667584e88db20 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 22 23:22:29 2014 +0100 asrock/e350m1/mainboard.c: Disable GPP CLK0 through SLT_GFX_CLK According to Edward this might fix the problems with the Ethernet device not showing up sometimes, when the PSU is not turned off during restarts or shut down and start. According to the SB800 Register Reference Guide [1] the clock pins are powered on (0xFF) by default. Powering off the clock pins for GPP4 to GPP8 and the Gfx PCIe device, hopefully sets the Ethernet device up correctly, so it is always detected during start up. Similar to the one applied to AMD Persimmon in [2]. [1] AMD SB800-Series Southbridges Register Reference Guide Publication: #45482 Revision: 3.04 [2] http://review.coreboot.org/1876 Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..56f3696 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,8 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/cimx/cimx_util.h> +#include <agesawrapper.h> +#include "SBPLATFORM.h" //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); @@ -54,6 +56,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + *(misc_mem_clk_cntrl + 0) = 0xFF; + *(misc_mem_clk_cntrl + 1) = 0xFF; + *(misc_mem_clk_cntrl + 2) = 0x00; + *(misc_mem_clk_cntrl + 3) = 0x00; + *(misc_mem_clk_cntrl + 4) = 0x00; + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The

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Patch set updated for coreboot: 4a0d57d asrock/e350m1/mainboard.c: Disable GPP CLK0 through SLT_GFX_CLK
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397 -gerrit commit 4a0d57d74d3e887c8c0adc310520c601c809bb53 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 22 23:22:29 2014 +0100 asrock/e350m1/mainboard.c: Disable GPP CLK0 through SLT_GFX_CLK According to Edward this might fix the problems with the Ethernet device not showing up sometimes, when the PSU is not turned off during restarts or shut down and start. According to the SB800 Register Reference Guide [1] the clock pins are powered on (0xFF) by default. Powering off the clock pins for GPP4 to GPP8 and the Gfx PCIe device, hopefully sets the Ethernet device up correctly, so it is always detected during start up. [1] AMD SB800-Series Southbridges Register Reference Guide Publication: #45482 Revision: 3.04 Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..e04bb92 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -54,6 +54,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + *(misc_mem_clk_cntrl + 0) = 0xFF; + *(misc_mem_clk_cntrl + 1) = 0xFF; + *(misc_mem_clk_cntrl + 2) = 0x00; + *(misc_mem_clk_cntrl + 3) = 0x00; + *(misc_mem_clk_cntrl + 4) = 0x00; + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The

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New patch to review for coreboot: 261113b asrock/e350m1/mainboard.c: GPP CLK
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397 -gerrit commit 261113bbe11c2776ae90a97bec52819f60e33aee Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 22 23:22:29 2014 +0100 asrock/e350m1/mainboard.c: GPP CLK According to Edward this might fix the problems with the Ethernet device not showing up sometimes. Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..e04bb92 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -54,6 +54,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + *(misc_mem_clk_cntrl + 0) = 0xFF; + *(misc_mem_clk_cntrl + 1) = 0xFF; + *(misc_mem_clk_cntrl + 2) = 0x00; + *(misc_mem_clk_cntrl + 3) = 0x00; + *(misc_mem_clk_cntrl + 4) = 0x00; + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The

1 0

New patch to review for coreboot: 2bdcdb6 x230: Deploy VBT
by Vladimir Serbinenko 22 Mar '14

22 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5396 -gerrit commit 2bdcdb6ab7377161d803680963edef1f1530f351 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:13:56 2014 +0100 x230: Deploy VBT Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/Makefile.inc | 1 + src/mainboard/lenovo/x230/gma.c | 297 ++++++++++++++++++++++++++++++++ src/northbridge/intel/sandybridge/gma.c | 30 ++++ src/northbridge/intel/sandybridge/gma.h | 2 + 4 files changed, 330 insertions(+) diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index d514d4b..4ce3d61 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -18,3 +18,4 @@ ## smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +ramstage-y += gma.c diff --git a/src/mainboard/lenovo/x230/gma.c b/src/mainboard/lenovo/x230/gma.c new file mode 100644 index 0000000..20a461b --- /dev/null +++ b/src/mainboard/lenovo/x230/gma.c @@ -0,0 +1,297 @@ +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +#include "northbridge/intel/sandybridge/sandybridge.h" + +/* This array contains the information on flat panel. When using native + graphics init coreboot copies it to where VGA Option ROM would be so + that OS can find it and able to use internal display. This contains no + executable code and is just information on the panel. + */ + +unsigned char fake_vbt[8192] = +{ +0x24, 0x56, 0x42, 0x54, 0x20, 0x53, 0x4e, 0x42, 0x2f, 0x49, 0x56, 0x42, 0x2d, 0x4d, 0x4f, 0x42, +0x49, 0x4c, 0x45, 0x20, 0x64, 0x00, 0x30, 0x00, 0x6b, 0x11, 0xc6, 0x00, 0x30, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x42, 0x49, 0x4f, 0x53, 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f, 0x42, 0x4c, 0x4f, 0x43, 0x4b, 0x20, +0xa8, 0x00, 0x16, 0x00, 0x3b, 0x11, 0xfe, 0xea, 0x00, 0x00, 0x64, 0x01, 0x01, 0x14, 0x0d, 0x32, +0x31, 0x36, 0x31, 0x49, 0x6e, 0x74, 0x65, 0x6c, 0x28, 0x52, 0x29, 0x20, 0x53, 0x61, 0x6e, 0x64, +0x79, 0x62, 0x72, 0x69, 0x64, 0x67, 0x65, 0x2f, 0x49, 0x76, 0x79, 0x62, 0x72, 0x69, 0x64, 0x67, +0x65, 0x20, 0x50, 0x43, 0x49, 0x20, 0x41, 0x63, 0x63, 0x65, 0x6c, 0x65, 0x72, 0x61, 0x74, 0x65, +0x64, 0x20, 0x53, 0x56, 0x47, 0x41, 0x20, 0x42, 0x49, 0x4f, 0x53, 0x0d, 0x0a, 0x42, 0x75, 0x69, +0x6c, 0x64, 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0x00, +0x64, 0x00, 0x2c, 0x01, 0x96, 0x00, 0xe8, 0x03, 0x2e, 0xb0, 0x00, 0x00, 0x88, 0x88, 0x88, 0x88, +0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, +0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, +0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, +0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, +0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, +0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, +0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, +0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, +0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, +0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, +0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00 +}; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index d049a80..9d40640 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <delay.h> +#include <string.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -651,6 +652,35 @@ static void gma_func0_init(struct device *dev) i915lightup(conf, physbase, iobase, mmiobase, graphics_base); #endif + + /* Linux relies on VBT for panel info. */ + if (read16(0xc0000) != 0xaa55) { + optionrom_header_t *oh = (void *)0xc0000; + optionrom_pcir_t *pcir; + int sz; + + memset(oh->reserved, 0, 8192); + + sz = (0x80 + sizeof(fake_vbt) + 511) / 512; + oh->signature = 0xaa55; + oh->size = sz; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)0xc0040; + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->imagelength = sz; + pcir->indicator = 0x80; + + memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt)); + } } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index f128412..0248473 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -166,6 +166,8 @@ typedef struct { #define VBT_SIGNATURE 0x54425624 +extern u8 fake_vbt[8192]; + struct northbridge_intel_sandybridge_config; void i915lightup(const struct northbridge_intel_sandybridge_config *info,

1 0

Patch set updated for coreboot: 245a324 lenovo: Make version look like something thinkpad_acpi would accept
by Vladimir Serbinenko 22 Mar '14

22 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650 -gerrit commit 245a324cf3e77ffdaed45bc1df88cde20e9a04de Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jun 7 02:11:41 2013 +0200 lenovo: Make version look like something thinkpad_acpi would accept thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. Not cleaned up as the idea of this patch seems to be met with resistance. Can make it Thinkpad-specific if the idea is accepted. Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/smbios.c | 13 +++++++++---- src/include/smbios.h | 1 + src/mainboard/lenovo/t60/mainboard.c | 12 ++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 11 +++++++++++ src/mainboard/lenovo/x230/mainboard.c | 10 ++++++++++ src/mainboard/lenovo/x60/mainboard.c | 11 +++++++++++ 6 files changed, 54 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..4dfc255 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -118,6 +118,14 @@ static int smbios_processor_name(char *start) return smbios_add_string(start, tmp); } +const char *__attribute__((weak)) smbios_mainboard_bios_version(void) +{ + if (strlen(CONFIG_LOCALVERSION)) + return CONFIG_LOCALVERSION; + else + return COREBOOT_VERSION; +} + static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -132,10 +140,7 @@ static int smbios_write_type0(unsigned long *current, int handle) #if !CONFIG_CHROMEOS t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); - if (strlen(CONFIG_LOCALVERSION)) - t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION); - else - t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); + t->bios_version = smbios_add_string(t->eos, smbios_mainboard_bios_version()); #else #define SPACES \ " " diff --git a/src/include/smbios.h b/src/include/smbios.h index 42c5d2d..b08459f 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_product_name(void); const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); +const char *smbios_mainboard_bios_version(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index bfdbef6..9d72eee 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> +#include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/io.h> @@ -33,6 +34,8 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <build.h> static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, @@ -46,6 +49,15 @@ int get_cst_entries(acpi_cstate_t **entries) return ARRAY_SIZE(cst_entries); } +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + static void mainboard_enable(device_t dev) { struct southbridge_intel_i82801gx_config *config; diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index cf42a9b..bc59059 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -25,6 +25,7 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> +#include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> @@ -47,6 +48,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <smbios.h> +#include <build.h> static acpi_cstate_t cst_entries[] = { {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}}, @@ -88,6 +90,15 @@ static int int15_handler(void) } #endif +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + const char *smbios_mainboard_version(void) { return "Lenovo X201"; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 2e4bc4a..e53553a 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -39,6 +39,7 @@ #include <device/pci.h> #include <cbfs.h> #include <pc80/keyboard.h> +#include <build.h> void mainboard_suspend_resume(void) { @@ -131,6 +132,15 @@ static int int15_handler(void) } #endif +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + const char *smbios_mainboard_version(void) { return "ThinkPad X230"; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d1fcb7b..8143ece 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> +#include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> @@ -37,6 +38,7 @@ #include "dock.h" #include <arch/x86/include/arch/acpigen.h> #include <smbios.h> +#include <build.h> #include <x86emu/x86emu.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -148,6 +150,15 @@ static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *curre return len; } +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init;

1 0

Patch set updated for coreboot: ea7d4bf intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit`
by Paul Menzel 22 Mar '14

22 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352 -gerrit commit ea7d4bfbdcae4e9a1fb4ad2cdfef5fc539ddca3c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 12:39:30 2014 +0100 intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit` Enabling CBMEM console for the Cougar Canyon 2 makes the build fail as there is no prototype for `cbmemc_reinit()`. The reason is that since commit 1d7541fe console: Fix includes `console/cbmem_console.h` is not included anymore through `console/console.h`. Since commit cbf5bdfe6 CBMEM: Always select CAR_MIGRATION calling `cbmemc_reinit()` in the board’s romstage is not needed anymore, so remove it. According to Martin Roth, CBMEM console does not work on the board Cougar Canyon 2 as CAR_MIGRATION is not supported due to shortcomings of the currently used FSP version. Therefore this patch just addresses the compile failure, so CBMEM console can be enabled by default for all boards. Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/intel/cougar_canyon2/romstage.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index afd7e25..76a2689 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif /* * FSP returns to this function instead of main, so we can't return back

1 0

Patch set updated for coreboot: 294c6df util/superiotool: Add initial support for Fintek F71869ED.
by W. Duijvenvoorde 22 Mar '14

22 Mar '14

W. Duijvenvoorde (w.a.n.duijvenvoorde(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5380 -gerrit commit 294c6dfb36ae0682de830d8fb5e0f55088c57aca Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> Date: Wed Mar 12 11:19:31 2014 +0100 util/superiotool: Add initial support for Fintek F71869ED. Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf Practically the same as F71869AD, just another ID (0x1408). Tested on actual hardware, Jetway NC9C-550-LF. Update: Fixed F71869AD/ED based on the proper datasheets: http://www.alldatasheet.com/datasheet-pdf/pdf/459074/FINTEK/F71869AD.html http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> --- util/superiotool/README | 1 + util/superiotool/fintek.c | 83 +++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 71 insertions(+), 13 deletions(-) diff --git a/util/superiotool/README b/util/superiotool/README index a7eb3db..7ff6138 100644 --- a/util/superiotool/README +++ b/util/superiotool/README @@ -114,3 +114,4 @@ Ulf Jordan <jordan(a)chalmers.se> Urja Rannikko <urjaman(a)gmail.com> Uwe Hermann <uwe(a)hermann-uwe.de> Ward Vandewege <ward(a)gnu.org> +Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index aba0353..fd118b7 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -4,6 +4,7 @@ * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -77,13 +78,13 @@ static const struct superio_registers reg_table[] = { {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, {EOT}}}, - {0x0710, "F71869AD", { + {0x0710, "F71869A/AD", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x25,0x26,0x27,0x28,0x29,0x2a, - 0x2b,0x2c,0x2d,EOT}, - {0x00,0x00,0x08,0x14,0x00,0x00,MISC,0x38,0x6f,0x07, - 0x0f,0x00,0x28,EOT}}, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x29,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,EOT}, + {0x00,0x00,0x10,0x07,0x19,0x34,0x00,0x00,NANA,0x38, + 0x6f,0x03,0x0f,0xe7,0x0f,NANA,0x00,NANA,0x28,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, @@ -105,18 +106,74 @@ static const struct superio_registers reg_table[] = { {0x6, "GPIO", {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xa0, + 0xa1,0xa2,0xa4,0xa5,0xa6,0xa9,0xab,0xac,0xad,0xae, + 0xaf,0x90,0x91,0x92,0x80,0x81,0x82,0x83,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x00,0x00,0x00, + 0x1f,NANA,0x00,0x00,0x00,0x00,0x00,0xe0,0x00,0x00, + 0x40,0x00,0xff,NANA,0x00,0xff,NANA,0x00,EOT}}, + {0x7, "WDT", + {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0x8, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, + 0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI, and ERP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xf9,0xfa,0xfc,0xfe,EOT}, + {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, + 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x1c, + 0x1f,0x86,0x00,0x00,0x00,0x07,0x00,EOT}}, + {EOT}}}, + {0x1408, "F71869E/ED", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2d,EOT}, + {0x00,0x00,0x08,0x14,0x19,0x34,0x00,NANA,0x38,0x6f, + 0x07,0x0f,0x28,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x01, "UART1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x02, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x03, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x04, "Hardware Monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3, 0x90,0x91,0x92,0x93,EOT}, {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00, 0x00,0x3f,NANA,0x00,EOT}}, - {0x7, "BSEL", - {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, - {0x00,0x00,0x00,0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, - {0xa, "PME, ACPI", - {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfe,0xff,EOT}, - {0x00,0x00,0x00,NANA,NANA,0x06,0x1c,0x1f,0x86,0x00,0x00,0x00,0x00,EOT}}, + {0x07, "WDT", + {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0x0a, "PME, ACPI, and EUP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfe,EOT}, + {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, + 0x00,0x00,0x00,0x00,0x00,NANA,0x06,0x1c,0x1f,0x86, + 0x00,0x00,0x00,EOT}}, {EOT}}}, {0x2307, "F71889", { /* We assume reserved bits are read as 0. */ @@ -395,7 +452,7 @@ void probe_idregs_fintek(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, did), vid, did, port); chip_found = 1; dump_superio("Fintek", reg_table, port, did, LDN_SEL); @@ -426,7 +483,7 @@ void probe_idregs_fintek_alternative(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, did), vid, did, port); chip_found = 1; dump_superio("Fintek", reg_table, port, did, LDN_SEL);

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Patch set updated for coreboot: d750842 util/superiotool: Add initial support for Fintek F71869ED.
by W. Duijvenvoorde 21 Mar '14

21 Mar '14

W. Duijvenvoorde (w.a.n.duijvenvoorde(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5380 -gerrit commit d750842510c753642f71ba5436c212384d2ec553 Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> Date: Wed Mar 12 11:19:31 2014 +0100 util/superiotool: Add initial support for Fintek F71869ED. Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf Practically the same as F71869AD, just another ID (0x1408). Tested on actual hardware, Jetway NC9C-550-LF. Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> --- util/superiotool/README | 1 + util/superiotool/fintek.c | 19 +++++++++++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/util/superiotool/README b/util/superiotool/README index a7eb3db..7ff6138 100644 --- a/util/superiotool/README +++ b/util/superiotool/README @@ -114,3 +114,4 @@ Ulf Jordan <jordan(a)chalmers.se> Urja Rannikko <urjaman(a)gmail.com> Uwe Hermann <uwe(a)hermann-uwe.de> Ward Vandewege <ward(a)gnu.org> +Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index aba0353..f3a5616 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -4,6 +4,7 @@ * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -77,7 +78,7 @@ static const struct superio_registers reg_table[] = { {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, {EOT}}}, - {0x0710, "F71869AD", { + {0x0710, "F71869AD/ED", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL, {0x02,0x07,0x20,0x21,0x25,0x26,0x27,0x28,0x29,0x2a, @@ -375,7 +376,7 @@ static const struct superio_registers reg_table[] = { void probe_idregs_fintek(uint16_t port) { - uint16_t vid, did; + uint16_t vid, did, magic; probing_for("Fintek", "", port); @@ -387,7 +388,13 @@ void probe_idregs_fintek(uint16_t port) vid = regval(port, VENDOR_ID_BYTE1_REG); vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); - if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { + /* F71869AD/ED are the same but have a different ID. */ + if (did == 0x1408) + magic = 0x0710; + else + magic = did; + + if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, magic)) { if (verbose) printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); exit_conf_mode_winbond_fintek_ite_8787(port); @@ -395,10 +402,10 @@ void probe_idregs_fintek(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, magic), vid, did, port); chip_found = 1; - dump_superio("Fintek", reg_table, port, did, LDN_SEL); + dump_superio("Fintek", reg_table, port, magic, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); } @@ -426,7 +433,7 @@ void probe_idregs_fintek_alternative(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, did), vid, did, port); chip_found = 1; dump_superio("Fintek", reg_table, port, did, LDN_SEL);

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coreboot-gerrit March 2014