coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

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584 discussions

Patch set updated for coreboot: f5863d2 baytrail: Fix XHCI problems and re-enable
by Aaron Durbin 26 Mar '14

26 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4933 -gerrit commit f5863d2072c167e52ac9b3db795255962b8d599b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 4 11:22:27 2013 -0800 baytrail: Fix XHCI problems and re-enable - a few clock gating bits were set improperly and were preventing the system from transitioning out of S0 state. - the XHCC registers were not getting the top byte set properly which includes things like DMA write request size and request boundary crossing control. This was causing memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot kernel from USB on rambi with XHCI driver Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175558 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 4 ++-- src/soc/intel/baytrail/xhci.c | 11 +++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index af115a6..a5fe37e 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -5,8 +5,8 @@ chip soc/intel/baytrail register "sata_ahci" = "0x1" register "ide_legacy_combined" = "0x0" - # Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS - register "usb_route_to_xhci" = "0" + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" # USB Port Disable Mask register "usb2_port_disable_mask" = "0x0" diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 244a4dc..30e6098 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -83,11 +83,11 @@ const struct reg_script xhci_init_script[] = { /* BAR + 0x0010[10,9,5]=110b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), /* BAR + 0x8058[20,16,8]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000010, 0x00110000), + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), /* BAR + 0x8060[25]=1b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), - /* BAR + 0x80e0[19,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010020, 0x01000040), + /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), /* BAR + 0x80e0 toggle bit 24=0 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), /* BAR + 0x80f0[20]=0b */ @@ -113,7 +113,7 @@ const struct reg_script xhci_init_script[] = { const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ - REG_PCI_RMW16(0x40, ~0x0300, 0x0010), + REG_PCI_RMW16(0x40, ~0x0600, 0x0100), REG_PCI_RMW8(0x42, ~0x38, 0x04), /* D20:F0:44[5:3]=001b */ REG_PCI_RMW16(0x44, ~0x0030, 0x0008), @@ -187,6 +187,9 @@ static void xhci_init(device_t dev) REG_SCRIPT_NEXT(xhci_init_script), /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), + /* Finalize XHCC1 and XHCC2 */ + REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), + REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */

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Patch set updated for coreboot: 4f506a3 baytrail: Add reserved MMIO regions to ACPI
by Aaron Durbin 26 Mar '14

26 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4934 -gerrit commit 4f506a347316b614f95e67e4c5c9fe49f080f3c2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 4 17:00:22 2013 -0800 baytrail: Add reserved MMIO regions to ACPI Add a length define for all the reserved MMIO regions and use them in the ACPI code to reserve the regions there. Add a region for the "abort page" documented in the EDS. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175624 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/dsdt.asl | 2 ++ src/soc/intel/baytrail/acpi/southcluster.asl | 29 ++++++++++++++++++ src/soc/intel/baytrail/baytrail/iomap.h | 45 ++++++++++++++++++++++++++-- src/soc/intel/baytrail/southcluster.c | 15 +++++----- 4 files changed, 82 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 172aaf4..55e44b5 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <soc/intel/baytrail/baytrail/iomap.h> + #define ENABLE_TPM DefinitionBlock( diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 307841b..81bcd32 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -30,3 +30,32 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } } + +/* Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, IO_BASE_ADDRESS, IO_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) +#if CONFIG_CHROMEOS_RAMOOPS + Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h index d46a0fe..77a55f5 100644 --- a/src/soc/intel/baytrail/baytrail/iomap.h +++ b/src/soc/intel/baytrail/baytrail/iomap.h @@ -21,21 +21,62 @@ #define _BAYTRAIL_IOMAP_H_ -/* Memory Mapped IO bases. */ +/* + * Memory Mapped IO bases. + */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 +/* Power Management Controller */ #define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* IO Memory */ #define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_SIZE 0x4000 + +/* Intel Legacy Block */ #define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ #define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* MODPHY */ #define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* Power Management Unit */ #define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Root Complex Base Address */ #define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* High Performance Event Timer */ #define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Temporary Base Address */ #define TEMP_BASE_ADDRESS 0xfd000000 -/* IO Port base */ +/* + * IO Port bases. + */ #define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + #define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + #define SMBUS_BASE_ADDRESS 0xefa0 #endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index c71ab7e..f8b4f18 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -41,13 +41,14 @@ add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) static void sc_add_mmio_resources(device_t dev) { - add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024); - add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024); - add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024); - add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024); - add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024); - add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048); - add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024); + add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); + add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); + add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); + add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); + add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); + add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); + add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); + add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); } /* Default IO range claimed by the LPC device. The upper bound is exclusive. */

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Patch set updated for coreboot: b92850b baytrail: Add function to read top of low memory
by Aaron Durbin 26 Mar '14

26 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4935 -gerrit commit b92850bb97e448523e4e188e4768833233738c73 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 4 17:02:45 2013 -0800 baytrail: Add function to read top of low memory The top of low memory is also the start of the region where PCIe resources are allocated. This needs to be passed in ACPI but is only readable from IOSF. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175625 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iomap.h | 5 +++++ src/soc/intel/baytrail/northcluster.c | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h index 77a55f5..d231dee 100644 --- a/src/soc/intel/baytrail/baytrail/iomap.h +++ b/src/soc/intel/baytrail/baytrail/iomap.h @@ -79,4 +79,9 @@ #define SMBUS_BASE_ADDRESS 0xefa0 +#ifndef __ACPI__ +/* Read Top of Low Memory (BMBOUND) */ +uint32_t nc_read_top_of_low_memory(void); +#endif + #endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index eca122c..e259163 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> +#include <baytrail/iomap.h> #include <baytrail/iosf.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> @@ -64,6 +65,11 @@ */ #define RES_IN_KiB(r) ((r) >> 10) +uint32_t nc_read_top_of_low_memory(void) +{ + return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); +} + static void nc_read_resources(device_t dev) { unsigned long mmconf; @@ -107,7 +113,7 @@ static void nc_read_resources(device_t dev) reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1)); + bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); /* The BMBOUND_HI register matches register bits of 31:24 with address

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Patch merged into coreboot/master: 5b9a408 mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
by gerrit＠coreboot.org 26 Mar '14

26 Mar '14

the following patch was just integrated into master: commit 5b9a408c2140e17b65070e5682da1fb717687902 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Mar 25 19:23:00 2014 +1100 mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig Switch on ACPI suspend/resume support which now works after many cycles. Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5406 for details. -gerrit

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Patch set updated for coreboot: 4fb2457 NOTFORMERGE: Build boards without selecting Chrome OS
by Paul Menzel 26 Mar '14

26 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5402 -gerrit commit 4fb2457677eec7e0e1bf1c4f5ecf2cac39fe7aa6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 23 23:35:40 2014 +0100 NOTFORMERGE: Build boards without selecting Chrome OS Change-Id: I4212d3fe6c5c84e58315d455332ede6cc46fe978 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index ed358f8..176ec3f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM help Enable ChromeOS specific features like the GPIO sub table in

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Patch set updated for coreboot: f93f42b libpayload: hexdump.c: Change type of length argument to size_t
by Alexandru Gagniuc 26 Mar '14

26 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4768 -gerrit commit f93f42bfafc805104fd6a223a9f25dad3ef0c775 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jan 21 14:30:51 2014 +0100 libpayload: hexdump.c: Change type of length argument to size_t Representing a (non-negative) length with a signed integer is not optimal, so change its type to `size_t`. Change-Id: Ic0c2b7e081ba32d917409568ee53007d9ab7f8f3 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/libpayload/include/libpayload.h | 2 +- payloads/libpayload/libc/hexdump.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 10a4505..8a0d915 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -294,7 +294,7 @@ long int labs(long int j); long long int llabs(long long int j); u8 bin2hex(u8 b); u8 hex2bin(u8 h); -void hexdump(void *memory, int length); +void hexdump(void *memory, size_t length); void fatal(const char *msg) __attribute__ ((noreturn)); /** @} */ diff --git a/payloads/libpayload/libc/hexdump.c b/payloads/libpayload/libc/hexdump.c index 814adf2..e33a306 100644 --- a/payloads/libpayload/libc/hexdump.c +++ b/payloads/libpayload/libc/hexdump.c @@ -29,7 +29,7 @@ #include <libpayload.h> -void hexdump(void *memory, int length) +void hexdump(void *memory, size_t length) { int i; uint8_t *m;

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Patch set updated for coreboot: dedff2a mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
by Alexandru Gagniuc 26 Mar '14

26 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5398 -gerrit commit dedff2ac8115f91ab04e51d1b535aef2336d8d16 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 23 00:09:32 2014 +0100 mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h` It's not needed and causes build failures without CONFIG_CHROMEOS. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/bolt/ec.c | 1 - src/mainboard/google/falco/ec.c | 1 - src/mainboard/google/link/ec.c | 1 - src/mainboard/google/parrot/ec.c | 1 - src/mainboard/google/peppy/ec.c | 1 - src/mainboard/google/rambi/ec.c | 1 - src/mainboard/google/slippy/ec.c | 1 - src/mainboard/intel/emeraldlake2/ec.c | 1 - src/mainboard/samsung/lumpy/ec.c | 1 - 9 files changed, 9 deletions(-) diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/bolt/ec.c +++ b/src/mainboard/google/bolt/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/falco/ec.c +++ b/src/mainboard/google/falco/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 07da080..7dfadeb 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index e6d2d38..56f7d80 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/peppy/ec.c +++ b/src/mainboard/google/peppy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 0919f0f..04a9931 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index ac37b0b..b50ab65 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 40d8319..2406012 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -18,7 +18,6 @@ */ #include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h>

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New patch to review for coreboot: 5d09fb1 rmodule: add subsections to linker script
by Aaron Durbin 25 Mar '14

25 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5407 -gerrit commit 5d09fb184df70f05cd028bf3aef68ea10b9e25f9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 25 14:53:28 2014 -0500 rmodule: add subsections to linker script Depending on the compiler options, subsections of the form of .section.subsection could be generated. Therefore, include those subsections for .bss, .sbss, and .data. Change-Id: I80dd64d8c62e7bc449ee2bbc0a22a941777e2ea6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/rmodule.ld | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 9222f3b..401f65f 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -66,6 +66,7 @@ SECTIONS /* Data section. */ _sdata = .; *(.data); + *(.data.*); . = ALIGN(4); _edata = .; @@ -76,7 +77,9 @@ SECTIONS /* C uninitialized data of the module. */ _bss = .; *(.bss); - *(.sbss); + *(.bss.*) + *(.sbss) + *(.sbss.*) *(COMMON); . = ALIGN(8); _ebss = .;

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Patch set updated for coreboot: 001c03b util/superiotool: Add initial support for Fintek F71869ED.
by W. Duijvenvoorde 25 Mar '14

25 Mar '14

W. Duijvenvoorde (w.a.n.duijvenvoorde(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5380 -gerrit commit 001c03b858ef6d3c873f3c4286dd542b266d14d3 Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> Date: Wed Mar 12 11:19:31 2014 +0100 util/superiotool: Add initial support for Fintek F71869ED. Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf Practically the same as F71869AD, just another ID (0x1408). Tested on actual hardware, Jetway NC9C-550-LF. Update: Fixed F71869ED based on the proper datasheet: http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> --- util/superiotool/README | 1 + util/superiotool/fintek.c | 51 +++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/util/superiotool/README b/util/superiotool/README index a7eb3db..7ff6138 100644 --- a/util/superiotool/README +++ b/util/superiotool/README @@ -114,3 +114,4 @@ Ulf Jordan <jordan(a)chalmers.se> Urja Rannikko <urjaman(a)gmail.com> Uwe Hermann <uwe(a)hermann-uwe.de> Ward Vandewege <ward(a)gnu.org> +Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index e1ddfd7..fd118b7 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -4,6 +4,7 @@ * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -128,6 +129,52 @@ static const struct superio_registers reg_table[] = { {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x1c, 0x1f,0x86,0x00,0x00,0x00,0x07,0x00,EOT}}, + {EOT}}}, + {0x1408, "F71869E/ED", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2d,EOT}, + {0x00,0x00,0x08,0x14,0x19,0x34,0x00,NANA,0x38,0x6f, + 0x07,0x0f,0x28,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x01, "UART1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x02, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x03, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x04, "Hardware Monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3, + 0x90,0x91,0x92,0x93,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00, + 0x00,0x3f,NANA,0x00,EOT}}, + {0x07, "WDT", + {0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0x0a, "PME, ACPI, and EUP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfe,EOT}, + {0x00,0x00,0xcc,0x3c,0x13,0x09,0xc7,0x09,0x63,0x08, + 0x00,0x00,0x00,0x00,0x00,NANA,0x06,0x1c,0x1f,0x86, + 0x00,0x00,0x00,EOT}}, + {EOT}}}, {0x2307, "F71889", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL, @@ -405,7 +452,7 @@ void probe_idregs_fintek(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, did), vid, did, port); chip_found = 1; dump_superio("Fintek", reg_table, port, did, LDN_SEL); @@ -436,7 +483,7 @@ void probe_idregs_fintek_alternative(uint16_t port) } printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", - get_superio_name(reg_table, did), vid, did, port); + get_superio_name(reg_table, did), vid, did, port); chip_found = 1; dump_superio("Fintek", reg_table, port, did, LDN_SEL);

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New patch to review for coreboot: 5b9a408 mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
by Edward O'Callaghan 25 Mar '14

25 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5406 -gerrit commit 5b9a408c2140e17b65070e5682da1fb717687902 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Mar 25 19:23:00 2014 +1100 mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig Switch on ACPI suspend/resume support which now works after many cycles. Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 6fbd75c..f05dc55 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -30,8 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE -# FIXME: Disable S3 for now. Enable by default once stabilised. -# select HAVE_ACPI_RESUME + select HAVE_ACPI_RESUME select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT

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coreboot-gerrit March 2014