coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 52e665b Add initial support for DMP Vortex86EX CPU.
by gerrit＠coreboot.org 20 Jun '13

20 Jun '13

the following patch was just integrated into master: commit 52e665bdd2c71b86643cbb1ee7e2fa5e96223059 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Jun 19 18:55:08 2013 +0800 Add initial support for DMP Vortex86EX CPU. Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3473 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3473 for details. -gerrit

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New patch to review for coreboot: 7b444e3 inteltool: add initial support for Nehalem
by Stefan Tauner 20 Jun '13

20 Jun '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3505 -gerrit commit 7b444e3ba55b6c13ffcd17d9ebd2df56efaa792d Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Thu Jun 20 18:05:06 2013 +0200 inteltool: add initial support for Nehalem Also, add pretty printing of Westmere's DMI registers (tested on my t410s by staring at non-zero output values :) Apparently Nehalem does not have a MEMBAR? But there are some documented memory controller control registers in PCI configuration space... left out for now. The PCIEXBAR is not documented publicly AFAICT, but there is a similar register on a device on bus 0xFF. phcoder might know more... Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 1 + util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 2 +- util/inteltool/pcie.c | 52 +++++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index a4edca9..5cd964a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -71,6 +71,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index dc5c832..88008e4 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -151,6 +151,7 @@ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 /* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index be8b0cb..18382e5 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -246,7 +246,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ - mch_registers = NULL; /* No public documentation */ + mch_registers = NULL; /* TODO: 322812 */ break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: mch_registers = sandybridge_mch_registers; diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 8c95257..cafd34a 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -23,6 +23,49 @@ #include <inttypes.h> #include "inteltool.h" +/* 320766 */ +static const io_register_t nehalem_dmi_registers[] = { + { 0x00, 4, "DMIVCH" }, // DMI Virtual Channel Capability Header + { 0x04, 4, "DMIVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 4, "DMIVCCTL" }, // DMI Port VC Control + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status +/* ... - Reserved */ + { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities + { 0x88, 2, "DMILCTL" }, // DMI Link Control + { 0x8A, 2, "DMILSTS" }, // DMI Link Status +/* ... - Reserved */ +}; + +/* 322812 */ +static const io_register_t westmere_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL1" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIC1RSTS" }, // DMI VC1 Resource Status +/* ... - Reserved */ + { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities + { 0x88, 2, "DMILCTL" }, // DMI Link Control + { 0x8A, 2, "DMILSTS" }, // DMI Link Status +/* ... - Reserved */ +}; + static const io_register_t sandybridge_dmi_registers[] = { { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1 @@ -180,11 +223,18 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; + case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN: + /* DMIBAR is called DMIRCBAR in Nehalem */ + dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */ + dmi_registers = nehalem_dmi_registers; + size = ARRAY_SIZE(nehalem_dmi_registers); + break; case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ - dmi_registers = NULL; /* No public documentation */ + dmi_registers = westmere_dmi_registers; + size = ARRAY_SIZE(westmere_dmi_registers); break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: dmi_registers = sandybridge_dmi_registers;

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New patch to review for coreboot: 8a4205b qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM.
by Denis Carikli 20 Jun '13

20 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3504 -gerrit commit 8a4205bab611b8f36b7b36aadb54849540e5f108 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 19 08:30:33 2013 +0200 qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM. Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that: Loading image. CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes) Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050 Processing 1703 relocs with adjust value of 0x3ffbe000 FATAL: Essential component is missing. However without that configuration set it boots fine. Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/emulation/qemu-i440fx/memory.c | 12 +++++++++++- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 8245ca2..3249e66 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -45,8 +45,18 @@ unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; } - +#if CONFIG_DYNAMIC_CBMEM +struct cbmem_entry *get_cbmem_toc(void); +#endif struct cbmem_entry *get_cbmem_toc(void) { return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); } + +#if CONFIG_DYNAMIC_CBMEM +void *cbmem_top(void) +{ + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + return (void *)get_top_of_ram(); +} +#endif diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 96d016b..c4fb0a8 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -16,6 +16,11 @@ #include "memory.c" +#if CONFIG_DYNAMIC_CBMEM +extern uint64_t high_tables_base; +extern uint64_t high_tables_size; +#endif + static unsigned long qemu_get_high_memory_size(void) { unsigned long high;

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New patch to review for coreboot: 949e6bc Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected.
by Denis Carikli 20 Jun '13

20 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3503 -gerrit commit 949e6bc29b14e530088c4848ff3d85609da2f7f7 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 20 16:24:14 2013 +0200 Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected. src/lib/cbmem.c is for the static cbmem. Thanks to adurbin for the Makefile.inc pointer and code on #coreboot IRC channel on freenode: <adurbin> no. if you have CONFIG_DYNAMIC_CBMEM then cbmem.c shouldn't be compiled [...] <adurbin> +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) <adurbin> +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c <adurbin> +endif <adurbin> +endif Without that fix we have: src/lib/cbmem.c:58:43: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes] src/lib/cbmem.c:76:6: error: no previous prototype for 'cbmem_init' [-Werror=missing-prototypes] src/lib/cbmem.c:107:5: error: no previous prototype for 'cbmem_reinit' [-Werror=missing-prototypes] This commit was tested on qemu-i440fx with the following commit: qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM. Change-Id: I98636aad4bb4b954f3ed3957df67c77f3615964a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/lib/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2600aa5..fd2e351 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -50,7 +50,13 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +endif +endif + romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c

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Patch merged into coreboot/master: 483ff82 sandybridge: Store MRC cache in CBFS
by gerrit＠coreboot.org 20 Jun '13

20 Jun '13

the following patch was just integrated into master: commit 483ff8253943b134e5e07ac89d08e49fca1c28d8 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jun 18 11:34:01 2013 +0200 sandybridge: Store MRC cache in CBFS Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases). Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/3497 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3497 for details. -gerrit

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Patch set updated for coreboot: 7e47fac Drop some duplicates of PCI-e config functions
by Kyösti Mälkki 20 Jun '13

20 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502 -gerrit commit 7e47facb7633da099ca53e5beb6e75eeca6ef204 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 Drop some duplicates of PCI-e config functions These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused and different from hardware setting. Change that to match hardware programming. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pcie_config.h | 89 +++++++++++++++++++++++++ src/mainboard/google/stout/mainboard_smi.c | 2 +- src/mainboard/iwave/iWRainbowG6/Kconfig | 2 +- src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/i945/pcie_config.c | 68 ------------------- src/northbridge/intel/sandybridge/early_init.c | 2 +- src/northbridge/intel/sandybridge/finalize.c | 2 +- src/northbridge/intel/sandybridge/pcie_config.c | 89 ------------------------- src/northbridge/intel/sch/pcie_config.c | 66 ------------------ src/northbridge/intel/sch/sch.h | 2 +- src/southbridge/intel/bd82x6x/finalize.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 6 -- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/sch/smihandler.c | 7 -- 18 files changed, 101 insertions(+), 248 deletions(-) diff --git a/src/arch/x86/include/arch/pcie_config.h b/src/arch/x86/include/arch/pcie_config.h new file mode 100644 index 0000000..672457d --- /dev/null +++ b/src/arch/x86/include/arch/pcie_config.h @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7981046..3f7df82 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,7 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include <cpu/intel/model_206ax/model_206ax.h> /* Include romstage serial for SIO helper functions */ diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 7e05aae..e908fcf 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xe0000000 config IRQ_SLOT_COUNT int diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..97ef679 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include "i945.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c deleted file mode 100644 index 0310d67..0000000 --- a/src/northbridge/intel/i945/pcie_config.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i945.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..a1938b8 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> static void sandybridge_setup_bars(void) { diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 0fa8d1a..bafa736 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <stdlib.h> -#include "pcie_config.c" +#include <arch/pcie_config.h> #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c deleted file mode 100644 index 0677d76..0000000 --- a/src/northbridge/intel/sandybridge/pcie_config.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "sandybridge.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c deleted file mode 100644 index ad7d746..0000000 --- a/src/northbridge/intel/sch/pcie_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 4f49beb..5700842 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); #define DEFAULT_RCBABASE 0xfed1c000 -#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ /* IGD */ #define GGC 0x52 diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..1492278 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..5d4add9 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf5..4bc5506 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5913115..be22a1b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..455f37c 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890..9b0c235 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 2e29acd..1de1ec9 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pcie_config.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f..5074138 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00;

1 0

Patch set updated for coreboot: d8a3043 Match device_t between romstage and ramstage
by Kyösti Mälkki 20 Jun '13

20 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3474 -gerrit commit d8a30436fdb180861303f27134457868187d7a68 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 17:16:56 2013 +0300 Match device_t between romstage and ramstage The aliased typedef of device_t causes problems when a function declaration is included for a source compilied without __PRE_RAM__ but the function definition is compiled with __PRE_RAM__. For such cases use simple_device_t. Add a function to test if simple_device_t (from romstage) matches with a device_t (from ramstage) for PCI devices by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 1 + src/device/pci_device.c | 13 +++++++++++++ src/include/device/device.h | 1 + src/include/device/pci.h | 1 + src/include/device/pci_def.h | 4 ++++ 5 files changed, 20 insertions(+) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..3450cb2 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -207,6 +207,7 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +typedef device_t simple_device_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4c5a814..8a7d080 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1054,6 +1054,19 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) } /** + * Test for match between romstage and ramstage device instance. + * + * @param dev Pointer to the device structure. + * @param sdev Simple device model identifier, created with PCI_DEV(). + * @return Non-zero if bus:dev.fn of device matches. + */ +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev) +{ + return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1a5cfed 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,6 +10,7 @@ struct device; #ifndef __PRE_RAM__ typedef struct device * device_t; +typedef unsigned int simple_device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..249c242 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -77,6 +77,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a7321..c24c445 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -474,4 +474,8 @@ #define PCI_FUNC(devfn) ((devfn) & 0x07) #define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8) +/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ +#define PCI_DEV2DEVFN(sdev) ((sdev>>12)&0xff) +#define PCI_DEV2SEGBUS(sdev) ((sdev>>20)&0xfff) + #endif /* PCI_DEF_H */

1 0

New patch to review for coreboot: 5d2b866 Drop some duplicates of PCI-e config functions
by Kyösti Mälkki 20 Jun '13

20 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502 -gerrit commit 5d2b8666f63fc05196f17bb0a376a01105a67299 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 Drop some duplicates of PCI-e config functions These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused and different from hardware setting. Change that to match hardware programming. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pcie_config.h | 89 +++++++++++++++++++++++++ src/mainboard/google/stout/mainboard_smi.c | 2 +- src/mainboard/iwave/iWRainbowG6/Kconfig | 2 +- src/northbridge/intel/haswell/haswell.h | 1 - src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/i945/pcie_config.c | 68 ------------------- src/northbridge/intel/sandybridge/early_init.c | 2 +- src/northbridge/intel/sandybridge/finalize.c | 2 +- src/northbridge/intel/sandybridge/pcie_config.c | 89 ------------------------- src/northbridge/intel/sch/pcie_config.c | 66 ------------------ src/northbridge/intel/sch/sch.h | 2 +- src/southbridge/intel/bd82x6x/finalize.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 6 -- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/sch/smihandler.c | 7 -- 19 files changed, 101 insertions(+), 249 deletions(-) diff --git a/src/arch/x86/include/arch/pcie_config.h b/src/arch/x86/include/arch/pcie_config.h new file mode 100644 index 0000000..672457d --- /dev/null +++ b/src/arch/x86/include/arch/pcie_config.h @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7981046..3f7df82 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,7 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include <cpu/intel/model_206ax/model_206ax.h> /* Include romstage serial for SIO helper functions */ diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 7e05aae..e908fcf 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xe0000000 config IRQ_SLOT_COUNT int diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 96438ad..d2a7638 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -47,7 +47,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..97ef679 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include "i945.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c deleted file mode 100644 index 0310d67..0000000 --- a/src/northbridge/intel/i945/pcie_config.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i945.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..a1938b8 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> static void sandybridge_setup_bars(void) { diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 0fa8d1a..bafa736 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <stdlib.h> -#include "pcie_config.c" +#include <arch/pcie_config.h> #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c deleted file mode 100644 index 0677d76..0000000 --- a/src/northbridge/intel/sandybridge/pcie_config.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "sandybridge.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c deleted file mode 100644 index ad7d746..0000000 --- a/src/northbridge/intel/sch/pcie_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 4f49beb..5700842 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); #define DEFAULT_RCBABASE 0xfed1c000 -#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ /* IGD */ #define GGC 0x52 diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..1492278 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..5d4add9 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf5..4bc5506 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5913115..be22a1b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..455f37c 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890..9b0c235 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 2e29acd..1de1ec9 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pcie_config.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f..5074138 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00;

1 0

Patch set updated for coreboot: 059746c AMD S3 resume: Add framwork to write bigger data
by Siyuan Wang 20 Jun '13

20 Jun '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3413 -gerrit commit 059746c58cdf66a520426b82dfbb9583d79fdd55 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sat Jun 8 10:25:06 2013 +0800 AMD S3 resume: Add framwork to write bigger data This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1] Some AMD south bridge can write bigger data when saving S3 info. In this patch, I use macro 'SB_SPI_TX_LEN' to contral data size. I have tested on AMD Parmer and Thatcher. We will relase a new board whose south bridge can transfer more than 4 bytes each time. [1] http://review.coreboot.org/#/c/2306/ Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 22 ++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/spi.c | 8 ++++++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 8a9ffee..c957cdc 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -152,10 +152,22 @@ void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx) { msr_t msr_data; msr_data = rdmsr(idx); + +#ifdef SB_SPI_TX_LEN +#define SPI_SIZE_MTRR SB_SPI_TX_LEN +#else +#define SPI_SIZE_MTRR 4 +#endif + +#if SPI_SIZE_MTRR >= 8 + flash->write(flash, *p_nvram_pos, 8, &msr_data); + *p_nvram_pos += 8; +#else flash->write(flash, *p_nvram_pos, 4, &msr_data.lo); *p_nvram_pos += 4; flash->write(flash, *p_nvram_pos, 4, &msr_data.hi); *p_nvram_pos += 4; +#endif } #endif @@ -264,10 +276,16 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { +#ifdef SB_SPI_TX_LEN +#define SPI_DATA_PACKET_SIZE SB_SPI_TX_LEN +#else +#define SPI_DATA_PACKET_SIZE 4 +#endif + for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) { data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); } + flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 1a63ce2..bcc280a 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -31,6 +31,14 @@ static int bus_claimed = 0; #endif +/* + * SB_SPI_TX_LEN is the biggest data size which south bridge can transfer. + * This size does not include SPI command. + */ +#ifndef SB_SPI_TX_LEN +#define SB_SPI_TX_LEN 4 +#endif + static u32 spibar; static void reset_internal_fifo_pointer(void)

1 0

Patch set updated for coreboot: 781513a w83627hf: Add comments about parallel port modes in superio.asl
by Christoph Grenz 19 Jun '13

19 Jun '13

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3495 -gerrit commit 781513ad443cc0bf64b4e9ba08256c758d20b662 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Tue Jun 18 01:26:50 2013 +0200 w83627hf: Add comments about parallel port modes in superio.asl Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/acpi/superio.asl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 69017fe..ff95dfc 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -529,6 +529,7 @@ Device(SIO) { Name (_PRS, ResourceTemplate () { + /* Traditional configurations (SPP mode) */ StartDependentFn (0,1) { IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) @@ -544,6 +545,7 @@ Device(SIO) { IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Traditional configurations (EPP mode) */ StartDependentFn (0,0) { IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) @@ -554,11 +556,13 @@ Device(SIO) { IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (EPP mode) */ StartDependentFn (2,0) { IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (No EPP mode) */ StartDependentFn (2,1) { IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08)

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coreboot-gerrit June 2013