coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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744 discussions

Patch set updated for coreboot: 25e0d7f AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3315 -gerrit commit 25e0d7fdab6773ce3037e2a3c55fa88412817856 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:09:44 2013 +0200 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM The IOMMU AGESA needs a reserved scratch space and it wants to allocate the stuff for runtime. So provide a simple allocator for 4 KB CBMEM page. Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + .../amd/agesa/family15tn/fam15tn_callouts.c | 27 ++++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index baec780..efb0f90 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,6 +71,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_NONE 0x00000000 +#define CBMEM_ID_AGESA_RUNTIME 0x41474553 #ifndef __ASSEMBLER__ #include <stdint.h> diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 7031a70..65be67c 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -47,6 +47,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_ROOT, "CBMEM ROOT " }, { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, + { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 59c892f..38bf975 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -26,6 +26,29 @@ #include "cbfs.h" #include "dimmSpd.h" #include "fam15tn_callouts.h" +#include <cbmem.h> + +#define AGESA_RUNTIME_SIZE 4096 + +static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) { + static unsigned int used = 0; + void *p = cbmem_find(CBMEM_ID_AGESA_RUNTIME); + + if ((AGESA_RUNTIME_SIZE - used) < AllocParams->BufferLength) { + return AGESA_BOUNDS_CHK; + } + + /* first time allocation */ + if (!p) { + p = cbmem_add(CBMEM_ID_AGESA_RUNTIME, AGESA_RUNTIME_SIZE); + if (!p) + return AGESA_BOUNDS_CHK; + } + + AllocParams->BufferPointer = p + used; + used += AllocParams->BufferLength; + return AGESA_SUCCESS; +} AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { @@ -48,6 +71,10 @@ AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; + /* if the allocation is for runtime use simple CBMEM data */ + if (Data == HEAP_CALLOUT_RUNTIME) + return alloc_cbmem(AllocParams); + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;

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Patch set updated for coreboot: 974a23e AMD Fam15tn: Add IOMMU BAR allocation to northbridge
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3314 -gerrit commit 974a23e61b257d9f3eccf02762bee8c6ad943507 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:06:43 2013 +0200 AMD Fam15tn: Add IOMMU BAR allocation to northbridge For IOMMU we need to allocate a 512 KB BAR in a non-standard location. Use the standard allocator for that and limit the BAR to 32-bits to be compatible with older systems. Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/include/device/pci_ids.h | 1 + src/northbridge/amd/agesa/family15tn/Makefile.inc | 1 + src/northbridge/amd/agesa/family15tn/iommu.c | 73 +++++++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f5ba7f7..3ad6351 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -287,6 +287,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 #define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index b609ee6..afec3c0 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -20,6 +20,7 @@ romstage-y += fam15tn_callouts.c romstage-y += dimmSpd.c +ramstage-y += iommu.c ramstage-y += northbridge.c ramstage-y += fam15tn_callouts.c ramstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c new file mode 100644 index 0000000..3765f20 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(device_t dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x44); + /* Remember this resource has been stored */ + res->flags |= IORESOURCE_STORED; + /* For now, do only 32-bit space allocation */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x44, res->base | (1 << 0)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU, +};

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Patch set updated for coreboot: ce84fff AMD Fam15tn: Fix IOMMU scratch support in AGESA
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3316 -gerrit commit ce84fff11223ac99eda00b7a45d55972c22b1fa6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:00:25 2013 +0200 AMD Fam15tn: Fix IOMMU scratch support in AGESA The IOMMU support is broken and does not even compile. Adding the header file `GnbIommuScratch.h` for the function `GnbIommuScratchMemoryRangeInterface()` and fixing the 64-bit versus 32-bit address issue, the file compiles now and is therefore hooked up into the build system. Change-Id: I1924a113af12b186edcdf1956cb5ec5453aee34c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 8 +++- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 55 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..815ab48 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -203,6 +203,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..3fe0ff0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -78,6 +78,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 45d0cd7..9bdc854 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -57,6 +57,7 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" +#include "GnbIommuScratch.h" #define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S @@ -111,9 +112,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; } + /* align the address to 64 bytes boundary */ +#ifdef __x86_64__ AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; - +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..4edcb37 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * IOMMU scratch page + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: $ @e \$Date: $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif

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Patch set updated for coreboot: 8b41642 Asus F2A85-M: Add IRQs for IOMMU
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3318 -gerrit commit 8b416423525e9c9bebd0908c5111f5e44c0f8c39 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 18:45:32 2013 +0200 Asus F2A85-M: Add IRQs for IOMMU The IOMMU needs IRQs assigned. So add those. Change-Id: Ic9f02e28aac593cddf7d222a8abb780a10572d32 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/acpi/routing.asl | 9 +++++++++ src/mainboard/asus/f2a85-m/mptable.c | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 1f2d63c..b939b6a 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -30,6 +30,11 @@ Scope(\_SB) { Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, @@ -84,6 +89,10 @@ Scope(\_SB) { Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 6ed9fca..1760303 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -130,6 +130,12 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

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Patch merged into coreboot/master: d358a50 Add support to enable/disable builtin GbE
by gerrit＠coreboot.org 21 Jun '13

21 Jun '13

the following patch was just integrated into master: commit d358a506c4230950e34d783bd0187cd200d60691 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 16:23:40 2013 -0700 Add support to enable/disable builtin GbE In case we are going to use this in future designs. BUG=none TEST=none BRANCH=none Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/55844 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3515 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3515 for details. -gerrit

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Patch merged into coreboot/master: 8a0a848 Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected.
by gerrit＠coreboot.org 21 Jun '13

21 Jun '13

the following patch was just integrated into master: commit 8a0a8488fec6ee3b94e9f1416cc839a20e47573e Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 20 16:24:14 2013 +0200 Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected. src/lib/cbmem.c is for the static cbmem. Thanks to adurbin for the Makefile.inc pointer and code on #coreboot IRC channel on freenode: <adurbin> no. if you have CONFIG_DYNAMIC_CBMEM then cbmem.c shouldn't be compiled [...] <adurbin> +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) <adurbin> +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c <adurbin> +endif <adurbin> +endif Without that fix we have: src/lib/cbmem.c:58:43: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes] src/lib/cbmem.c:76:6: error: no previous prototype for 'cbmem_init' [-Werror=missing-prototypes] src/lib/cbmem.c:107:5: error: no previous prototype for 'cbmem_reinit' [-Werror=missing-prototypes] This commit was tested on qemu-i440fx with the following commit: qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM ( http://review.coreboot.org/#/c/3504/ ). Change-Id: I98636aad4bb4b954f3ed3957df67c77f3615964a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/3503 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3503 for details. -gerrit

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New patch to review for coreboot: 456be76 Add support to enable/disable builtin GbE
by Stefan Reinauer 21 Jun '13

21 Jun '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3515 -gerrit commit 456be76331061a8af9750a4dc3e9de95bb0f6e7a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 16:23:40 2013 -0700 Add support to enable/disable builtin GbE In case we are going to use this in future designs. BUG=none TEST=none BRANCH=none Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/55844 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/pei_data.h | 3 ++- src/northbridge/intel/sandybridge/pei_data.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 280c73b..7c10e41 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,7 +31,7 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 10 +#define PEI_VERSION 11 struct pei_data { @@ -53,6 +53,7 @@ struct pei_data uint8_t spd_addresses[4]; int boot_mode; int ec_present; + int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index fb56873..d317515 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -38,7 +38,7 @@ typedef struct { } pch_usb3_controller_settings; typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 5 +#define PEI_VERSION 6 struct pei_data { @@ -61,6 +61,7 @@ struct pei_data uint8_t ts_addresses[4]; int boot_mode; int ec_present; + int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel

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New patch to review for coreboot: 4c8ae00 intel/sandybridge: Locate CBMEM TOC early in ramstage
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3513 -gerrit commit 4c8ae00520bed65aa2eca7d8a069accfde983e0e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 21 15:37:55 2013 +0300 intel/sandybridge: Locate CBMEM TOC early in ramstage This patch allows the use of migrated CAR_GLOBAL variables from the very beginning of ramstage. Without the patch, CAR_GLOBALS were not available until northbridge set_resources(). Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/sandybridge/northbridge.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0a413b4..d8e2e9d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,6 +51,21 @@ int bridge_silicon_revision(void) return bridge_revision_id; } +static unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); + return (unsigned long) tom; +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + static struct cbmem_entry *toc = NULL; + if (!toc) + toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); + return toc; +} + /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA

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New patch to review for coreboot: 1809bdf Do CAR variable migration only once
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3512 -gerrit commit 1809bdfaa4bf6be0b0729b02f28445c16a06b28a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 21 18:02:26 2013 +0300 Do CAR variable migration only once Non-S3 resume paths of sandy/ivybridge call cbmem_initialize() more than once. Doing car_migrate_variables() more than twice caused at least loss of some lines in CBMEM console. Change-Id: Idd14aba9384984aa3a7d38937a4b3572aa5dc088 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/car.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 31fc67c..88f2807 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -80,6 +80,10 @@ void car_migrate_variables(void) car_migration_func_t *migrate_func; size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + /* Check if already migrated. */ + if (car_migrated) + return; + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); if (migrated_base == NULL) {

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Patch set updated for coreboot: 16ea97e Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected.
by Denis Carikli 21 Jun '13

21 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3503 -gerrit commit 16ea97e5d1e6d8f1fe2e63f5356c82f81bbb4072 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 20 16:24:14 2013 +0200 Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected. src/lib/cbmem.c is for the static cbmem. Thanks to adurbin for the Makefile.inc pointer and code on #coreboot IRC channel on freenode: <adurbin> no. if you have CONFIG_DYNAMIC_CBMEM then cbmem.c shouldn't be compiled [...] <adurbin> +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) <adurbin> +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c <adurbin> +endif <adurbin> +endif Without that fix we have: src/lib/cbmem.c:58:43: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes] src/lib/cbmem.c:76:6: error: no previous prototype for 'cbmem_init' [-Werror=missing-prototypes] src/lib/cbmem.c:107:5: error: no previous prototype for 'cbmem_reinit' [-Werror=missing-prototypes] This commit was tested on qemu-i440fx with the following commit: qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM ( http://review.coreboot.org/#/c/3504/ ). Change-Id: I98636aad4bb4b954f3ed3957df67c77f3615964a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/lib/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2600aa5..d44f4a7 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -50,7 +50,11 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +endif + romstage-y += compute_ip_checksum.c romstage-y += memmove.c romstage-$(CONFIG_ARCH_X86) += gcc.c

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coreboot-gerrit June 2013