coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 725dd55 Lenovo T60: Add CMOS defaults.
by Denis Carikli 23 Jun '13

23 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3520 -gerrit commit 725dd55ad4207b228aea24779cc1ae69fe44baf5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Jun 23 19:39:03 2013 +0200 Lenovo T60: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback baud_rate = 115200 debug_level = Spew hyper_threading = Enable nmi = Enable boot_devices = '' boot_default = 0x41 cmos_defaults_loaded = Yes lpt = Enable touchpad = Disable bluetooth = Enable volume = 0x93 first_battery = Primary The code for handling the invalid CMOS space in mainboard.c is now useless and so it was removed. Change-Id: I86ec6a7f73e32948adff9087d4af5372a49a46a5 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/t60/cmos.default | 14 ++++++++++++++ src/mainboard/lenovo/t60/mainboard.c | 17 ----------------- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 952004b..4809a5c 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default new file mode 100644 index 0000000..d54e803 --- /dev/null +++ b/src/mainboard/lenovo/t60/cmos.default @@ -0,0 +1,14 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +boot_default=0x41 +cmos_defaults_loaded=Yes +lpt=Enable +touchpad=Enable +bluetooth=Enable +volume=0x3 +first_battery=Primary diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2e54c7b..bfdbef6 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -50,7 +50,6 @@ static void mainboard_enable(device_t dev) { struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; - u8 defaults_loaded = 0; /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); @@ -77,22 +76,6 @@ static void mainboard_enable(device_t dev) /* set dock status led */ ec_write(0x0c, 0x08); ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); - - if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { - printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); - defaults_loaded = 0; - } - - if (!defaults_loaded) { - printk(BIOS_INFO, "Restoring CMOS defaults\n"); - set_option("tft_brightness", &(u8[]){ 0xff }); - set_option("volume", &(u8[]){ 0x03 }); - /* set baudrate to 115200 baud */ - set_option("baud_rate", &(u8[]){ 0x00 }); - /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ - set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); - set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); - } } struct chip_operations mainboard_ops = {

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Patch merged into coreboot/master: a390d77 AMD boards: routing.asl: Uniformly start `Package()` with capital letter
by gerrit＠coreboot.org 23 Jun '13

23 Jun '13

the following patch was just integrated into master: commit a390d779668146b60fdb89eaa709054d7811df7e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 22 13:47:06 2013 +0200 AMD boards: routing.asl: Uniformly start `Package()` with capital letter In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3516 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3516 for details. -gerrit

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New patch to review for coreboot: 850cd49 ARCH_ARMV7: Apply Kconfig style
by Kyösti Mälkki 23 Jun '13

23 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3519 -gerrit commit 850cd497eac8d43cc8e9ba29838159d78965dbe5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 23 13:52:56 2013 +0300 ARCH_ARMV7: Apply Kconfig style The style selected on x86 side is to not surround the "source" statements, but place the conditional "if" statement in the file to be sourced instead. Change-Id: Ia3d8badbba941687c623c1ccc8b7b5ac4325f929 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/armltd/Kconfig | 7 ------- src/cpu/armltd/cortex-a9/Kconfig | 7 +++++++ src/cpu/samsung/Kconfig | 6 +----- src/cpu/samsung/Makefile.inc | 2 +- src/cpu/samsung/exynos5250/Kconfig | 11 +++++++++++ src/cpu/ti/Kconfig | 10 ---------- src/cpu/ti/am335x/Kconfig | 13 +++++++++++++ src/mainboard/google/snow/Kconfig | 2 +- 8 files changed, 34 insertions(+), 24 deletions(-) diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig index b1f4c2e..af0c5c5 100644 --- a/src/cpu/armltd/Kconfig +++ b/src/cpu/armltd/Kconfig @@ -1,8 +1 @@ -config CPU_ARMLTD_CORTEX_A9 - depends on ARCH_ARMV7 - bool - default n - -if CPU_ARMLTD_CORTEX_A9 source src/cpu/armltd/cortex-a9/Kconfig -endif diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index 7f35cfd..16ededc 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -1,5 +1,12 @@ +config CPU_ARMLTD_CORTEX_A9 + bool + +if CPU_ARMLTD_CORTEX_A9 + config BOOTBLOCK_CPU_INIT string default "cpu/armltd/cortex-a9/bootblock.c" help CPU/SoC-specific bootblock code. + +endif # CPU_ARMLTD_CORTEX_A9 diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 9e2ec4c..c3d825e 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -1,11 +1,7 @@ config CPU_SAMSUNG_EXYNOS5 - depends on ARCH_ARMV7 + def_bool n select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select DEFAULT_EARLY_CONSOLE - bool - default n -if CPU_SAMSUNG_EXYNOS5 source src/cpu/samsung/exynos5250/Kconfig -endif diff --git a/src/cpu/samsung/Makefile.inc b/src/cpu/samsung/Makefile.inc index 97e9aab..c427925 100644 --- a/src/cpu/samsung/Makefile.inc +++ b/src/cpu/samsung/Makefile.inc @@ -1,2 +1,2 @@ subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5) += exynos5-common -subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5) += exynos5250 +subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5250) += exynos5250 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cc67abd..034dd51 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,12 @@ +config CPU_SAMSUNG_EXYNOS5250 + bool + +if CPU_SAMSUNG_EXYNOS5250 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_SAMSUNG_EXYNOS5 + config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5250/bootblock.c" @@ -97,3 +106,5 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex default 0x4000000 + +endif # CPU_SAMSUNG_EXYNOS5250 diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig index c82c290..5a62219 100644 --- a/src/cpu/ti/Kconfig +++ b/src/cpu/ti/Kconfig @@ -1,11 +1 @@ -config CPU_TI_AM335X - depends on ARCH_ARMV7 - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DEFAULT_EARLY_CONSOLE - bool - default n - -if CPU_TI_AM335X source src/cpu/ti/am335x/Kconfig -endif diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 472fbe7..5b3c7b5 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -1,3 +1,14 @@ +config CPU_TI_AM335X + bool + +if CPU_TI_AM335X + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_EARLY_CONSOLE + config BOOTBLOCK_CPU_INIT string default "cpu/ti/am335x/bootblock.c" @@ -46,3 +57,5 @@ config SYS_SDRAM_BASE config COREBOOT_TABLES_SIZE hex default 0x800 + +endif # CPU_TI_AM335X diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index aa4c3c4..3f7fb19 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -22,7 +22,7 @@ if BOARD_GOOGLE_SNOW config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARMV7 - select CPU_SAMSUNG_EXYNOS5 + select CPU_SAMSUNG_EXYNOS5250 select HAVE_UART_MEMORY_MAPPED select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C

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Patch merged into coreboot/master: eac00d2 intel/sandybridge: Locate CBMEM TOC early in ramstage
by gerrit＠coreboot.org 22 Jun '13

22 Jun '13

the following patch was just integrated into master: commit eac00d2dbbe57e10a130ea1c0c6d943c2a9f19c1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 21 15:37:55 2013 +0300 intel/sandybridge: Locate CBMEM TOC early in ramstage This patch allows the use of migrated CAR_GLOBAL variables from the very beginning of ramstage. Without the patch, CAR_GLOBALS were not available until northbridge set_resources(). Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3513 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3513 for details. -gerrit

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Patch merged into coreboot/master: 7f5897a Do CAR variable migration only once
by gerrit＠coreboot.org 22 Jun '13

22 Jun '13

the following patch was just integrated into master: commit 7f5897a1c5bcd6062169368b827975faa9feeebf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 21 18:02:26 2013 +0300 Do CAR variable migration only once Non-S3 resume paths of sandy/ivybridge call cbmem_initialize() more than once. Doing car_migrate_variables() more than twice caused at least loss of some lines in CBMEM console. Change-Id: Idd14aba9384984aa3a7d38937a4b3572aa5dc088 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3512 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3512 for details. -gerrit

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New patch to review for coreboot: 05733a2 CBMEM: high_table globals cleanup [NOTFORMERGE]
by Kyösti Mälkki 22 Jun '13

22 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3518 -gerrit commit 05733a259a62ffaba4c6844ba9ac820b34981a09 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 22 21:27:20 2013 +0300 CBMEM: high_table globals cleanup [NOTFORMERGE] Squashed for abuild only. Change-Id: I910842f51ead98af7a85c20c90dd230e6a6458ed Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/boot/tables.c | 13 +-- src/arch/x86/boot/tables.c | 16 +--- src/include/cbmem.h | 12 ++- src/lib/cbmem.c | 93 ++++++++++++++++++---- src/lib/coreboot_table.c | 5 +- src/lib/dynamic_cbmem.c | 5 ++ src/mainboard/emulation/qemu-i440fx/memory.c | 7 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 +- src/mainboard/getac/p470/romstage.c | 5 +- src/mainboard/google/butterfly/acpi_tables.c | 2 +- src/mainboard/google/link/acpi_tables.c | 2 +- src/mainboard/google/parrot/acpi_tables.c | 2 +- src/mainboard/google/snow/ramstage.c | 13 +-- src/mainboard/google/stout/acpi_tables.c | 2 +- src/mainboard/google/stout/romstage.c | 3 +- src/mainboard/ibase/mb899/romstage.c | 5 +- src/mainboard/intel/d945gclf/romstage.c | 5 +- src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 5 +- src/mainboard/roda/rk886ex/romstage.c | 5 +- src/mainboard/roda/rk9/romstage.c | 5 +- src/mainboard/samsung/lumpy/acpi_tables.c | 2 +- src/mainboard/samsung/stumpy/acpi_tables.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 18 +---- src/northbridge/amd/agesa/family12/northbridge.c | 23 +----- src/northbridge/amd/agesa/family14/northbridge.c | 22 +---- src/northbridge/amd/agesa/family15/northbridge.c | 18 +---- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +---- src/northbridge/amd/amdfam10/northbridge.c | 18 +---- src/northbridge/amd/amdk8/northbridge.c | 18 +---- src/northbridge/amd/gx1/northbridge.c | 4 +- src/northbridge/amd/gx2/northbridge.c | 4 +- src/northbridge/amd/lx/northbridge.c | 4 +- src/northbridge/intel/e7501/northbridge.c | 4 +- src/northbridge/intel/e7505/northbridge.c | 4 +- src/northbridge/intel/e7520/northbridge.c | 4 +- src/northbridge/intel/e7525/northbridge.c | 4 +- src/northbridge/intel/gm45/northbridge.c | 4 +- src/northbridge/intel/i3100/northbridge.c | 4 +- src/northbridge/intel/i440bx/northbridge.c | 4 +- src/northbridge/intel/i440lx/northbridge.c | 4 +- src/northbridge/intel/i5000/northbridge.c | 5 +- src/northbridge/intel/i82810/northbridge.c | 4 +- src/northbridge/intel/i82830/northbridge.c | 4 +- src/northbridge/intel/i855/northbridge.c | 4 +- src/northbridge/intel/i945/northbridge.c | 4 +- src/northbridge/intel/i945/raminit.c | 5 -- src/northbridge/intel/sandybridge/northbridge.c | 4 +- src/northbridge/intel/sandybridge/raminit.c | 5 -- src/northbridge/intel/sch/northbridge.c | 6 +- src/northbridge/rdc/r8610/northbridge.c | 4 +- src/northbridge/via/cn400/northbridge.c | 5 +- src/northbridge/via/cn700/northbridge.c | 5 +- src/northbridge/via/cx700/northbridge.c | 5 +- src/northbridge/via/vt8601/northbridge.c | 5 +- src/northbridge/via/vt8623/northbridge.c | 5 +- src/northbridge/via/vx900/early_vx900.c | 5 -- src/northbridge/via/vx900/northbridge.c | 6 +- 58 files changed, 177 insertions(+), 298 deletions(-) diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 0fc7399..de6b6fa 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -29,13 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - void cbmem_arch_init(void) { } @@ -44,11 +37,7 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + cbmem_base_check(); post_code(0x9d); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 6355a1b..461ca62 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -32,8 +32,6 @@ #include <lib.h> #include <smbios.h> -uint64_t high_tables_base = 0; -uint64_t high_tables_size; void cbmem_arch_init(void) { @@ -45,6 +43,7 @@ struct lb_memory *write_tables(void) { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; + uint64_t cbmem_base, cbmem_size; /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -52,15 +51,8 @@ struct lb_memory *write_tables(void) */ unsigned long high_table_pointer; -#if !CONFIG_DYNAMIC_CBMEM - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); -#endif + cbmem_base_check(); + get_cbmem_table(&cbmem_base, &cbmem_size); rom_table_start = 0xf0000; rom_table_end = 0xf0000; @@ -229,7 +221,7 @@ struct lb_memory *write_tables(void) /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); + cbmem_base, high_table_pointer); if (new_high_table_pointer > (high_table_pointer + MAX_COREBOOT_TABLE_SIZE)) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index baec780..4df9a85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -133,15 +133,21 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #else /* !CONFIG_DYNAMIC_CBMEM */ #ifndef __PRE_RAM__ -extern uint64_t high_tables_base, high_tables_size; +void set_top_of_ram(uint64_t ramtop); +void set_top_of_ram_once(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif -void cbmem_init(u64 baseaddr, u64 size); +void get_high_table(uint64_t *base, uint64_t *size); +void get_cbmem_table(uint64_t *base, uint64_t *size); + int cbmem_reinit(u64 baseaddr); extern struct cbmem_entry *get_cbmem_toc(void); +#define high_tables_base(x) ((uint64_t)get_cbmem_toc()) +#define high_tables_base32(x) ((uint32_t)get_cbmem_toc()) + #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ @@ -156,6 +162,8 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +int cbmem_base_check(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ void cbmem_list(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 3702da1..0af01f9 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -42,26 +42,73 @@ struct cbmem_entry { } __attribute__((packed)); #ifndef __PRE_RAM__ -static struct cbmem_entry *bss_cbmem_toc; +static uint64_t cbmem_base = 0; +static uint64_t cbmem_size = 0; +#endif -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +extern unsigned long get_top_of_ram(void); + +unsigned long __attribute__((weak)) get_top_of_ram(void) { - return bss_cbmem_toc; + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; } +void __attribute__((weak)) get_high_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} + +#ifndef __PRE_RAM__ void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { /* do nothing, this should be called by chipset to save TOC in NVRAM */ } -#else + +void set_top_of_ram(uint64_t ramtop) +{ + cbmem_base = ramtop - HIGH_MEMORY_SIZE; + cbmem_size = HIGH_MEMORY_SIZE; +} + +void set_top_of_ram_once(uint64_t ramtop) +{ + if (!cbmem_base) + set_top_of_ram(ramtop); +} +#endif struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; +#ifdef __PRE_RAM__ + uint64_t cbmem_base, cbmem_size; + get_high_table(&cbmem_base, &cbmem_size); +#else + if (!cbmem_base) + get_high_table(&cbmem_base, &cbmem_size); +#endif + return (struct cbmem_entry *) (unsigned)cbmem_base; } +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ +#ifdef __PRE_RAM__ + get_high_table(base, size); +#else + if (!cbmem_base) + get_high_table(&cbmem_base, &cbmem_size); + + *base = cbmem_base; + *size = cbmem_size; #endif +} /** * cbmem is a simple mechanism to do some kind of book keeping of the coreboot @@ -73,13 +120,14 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) * - suspend/resume backup memory */ -void cbmem_init(u64 baseaddr, u64 size) +static void cbmem_init(u64 baseaddr, u64 size) { struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; #ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; + cbmem_base = baseaddr; + cbmem_size = size; #endif printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", @@ -113,12 +161,27 @@ int cbmem_reinit(u64 baseaddr) (unsigned long)baseaddr); #ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; + cbmem_base = baseaddr; #endif return (cbmem_toc[0].magic == CBMEM_MAGIC); } +int cbmem_base_check(void) +{ + uint64_t base, size; + + get_cbmem_table(&base, &size); + if (!base) { + printk(BIOS_ERR, "ERROR: cbmem_base is not set.\n"); + // Are there any boards without? + // Stepan thinks we should die() here! + } + printk(BIOS_DEBUG, "cbmem_base: %llx.\n", base); + + return !!base; +} + void *cbmem_add(u32 id, u64 size) { struct cbmem_entry *cbmem_toc; @@ -205,25 +268,23 @@ void *cbmem_find(u32 id) } #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) + /* Returns True if it was not intialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + get_cbmem_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d25b59d..9914b1a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -542,8 +542,9 @@ unsigned long write_coreboot_table( #if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); #else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); + uint64_t base, size; + get_cbmem_table(&base, &size); + lb_add_memory_range(mem, LB_MEM_TABLE, base, size); #endif /* CONFIG_DYNAMIC_CBMEM */ /* No other memory areas can be added after the memory table has been diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index ba7760d..b753266 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -227,6 +227,11 @@ static int validate_entries(struct cbmem_root *root) return 0; } +int cbmem_base_check(void) +{ + return 1; +} + int cbmem_initialize(void) { struct cbmem_root *root; diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..4f9f31c 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -46,12 +46,7 @@ unsigned long get_top_of_ram(void) return qemu_get_memory_size() * 1024; } -#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 3e45d9a..0afcaed 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -54,9 +54,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) ram_resource(dev, idx++, 4 * 1024 * 1024, high); #if !CONFIG_DYNAMIC_CBMEM - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); #endif /* Reserve space for the IOAPIC. This should be in the Southbridge, diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90d38eb..d184ffa 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -358,13 +358,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 95b45db..b7bac5d 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -65,7 +65,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index dbbde68..2b012c4 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -75,7 +75,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs, igd_opregion_t *opregion) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 1; diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 45a9948..9b9ff83 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -66,7 +66,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 72f830d..f51c3a0 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -76,6 +76,13 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) framebuffer->reserved_mask_size = 0; } +void get_high_table(uint64_t *base, uint64_t *size) +{ + *base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + *size = CONFIG_COREBOOT_TABLES_SIZE; +} void hardwaremain(void); void main(void) @@ -83,11 +90,7 @@ void main(void) /* FIXME this should be moved elsewhere. We don't want ramstage.c */ /* set up coreboot tables */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + cbmem_initialize(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 62d5891..b4e897b 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -69,7 +69,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 14820dd..476a846 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -313,8 +313,7 @@ void main(unsigned long bist) #if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); #else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); + cbmem_was_initted = cbmem_reinit(high_tables_base()); #endif #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 79eaa0b..166c175 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -312,13 +312,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a37f605..3514829 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -270,13 +270,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 6e32779..7606788 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -88,7 +88,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 1; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 03b24d8..6f6f8da 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -411,13 +411,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ab200d2..0ec4e93 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -347,13 +347,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 56eea84..6e4c132 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -184,13 +184,10 @@ void main(unsigned long bist) init_iommu(); #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit((u64)high_ram_base)) { + if (s3resume && cbmem_reinit(high_tables_base()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 13e9e0f..1eb8287 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -88,7 +88,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b68edcd..a77190d 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -89,7 +89,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 1; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = high_tables_base32(); /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 4589f6d..325d2c1 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 621246f..4c230f1 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), - high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e7de273..fbf8e44 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4 * 1024 * 1024) { @@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6134830..7e33046 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f91f690..2e1ff2e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 2228fb5..be77f8b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5c1d97a..505d94d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index d670a19..3db3974 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -108,9 +108,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 038d757..27de1a4 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -290,9 +290,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index bde72a7..4df6879 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -389,9 +389,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index d30c9df..0dc7b0b 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -84,9 +84,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6ee371f..4b24b79 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -85,9 +85,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 96fcc35..8b74cec 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -102,9 +102,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 83757bd..402dbda 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -101,9 +101,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 3a4439c..d55a03a 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -166,9 +166,7 @@ static void mch_domain_read_resources(device_t dev) pcie_config_size >> 10, IORESOURCE_RESERVE); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk << 10); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index bcaded6..b3349ed 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -126,9 +126,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 2ab62a9..c1aec92 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,9 +67,7 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index fe5f09e..b41a975 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -93,9 +93,7 @@ static void i440lx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 113dc56..3e186fa 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -111,10 +111,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = tolm - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); + set_top_of_ram(tolm); } static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 1d6b66d..3fb3e11 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -121,9 +121,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, tomk - 768); uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 881551c..73c28dd 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -90,9 +90,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 75837a1..4c1cd93 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -105,9 +105,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..fc84647 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -170,9 +170,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h> -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0a413b4..4097b6c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -259,9 +259,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 78eedb8..e1fb7f4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 06d34d8..7cf1db3 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -182,11 +182,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables. */ - high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; - high_tables_base -= uma_memory_size; - high_tables_base -= tseg_memory_base; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024 - uma_memory_size - tseg_memory_base); } /* diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index e97f10a..2c830ec 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -64,9 +64,7 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); assign_resources(dev->link_list); } diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 0108170..e78d836 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -204,10 +204,7 @@ static void cn400_domain_set_resources(device_t dev) } /* Locate the High Tables at the Top of Low Memory below the Video RAM */ - high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 73bf676..c5305d8 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -134,10 +134,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index f28a0ed..0d57772 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -68,10 +68,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 45a0ac5..aa775f7 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -84,10 +84,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index f93a886..dd0271a 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -143,10 +143,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. * diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index c3c3920..35e2261 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -266,11 +266,7 @@ static void vx900_set_resources(device_t dev) u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + set_top_of_ram(tolmk << 10); print_debug("======================================================\n"); assign_resources(dev->link_list);

1 0

Patch merged into coreboot/master: 0651072 Add support for DMP Vortex86EX PCI northbridge.
by gerrit＠coreboot.org 22 Jun '13

22 Jun '13

the following patch was just integrated into master: commit 065107259774169db73c42e9a2d5777f63a78c29 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Jun 21 21:37:05 2013 +0800 Add support for DMP Vortex86EX PCI northbridge. Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3511 for details. -gerrit

1 0

Patch merged into coreboot/master: 378d046 qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM.
by gerrit＠coreboot.org 22 Jun '13

22 Jun '13

the following patch was just integrated into master: commit 378d04640d4e946be45952625c9f85efda9066ad Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 19 08:30:33 2013 +0200 qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM. This commit was tested on qemu with and without CONFIG_DYNAMIC_CBMEM by running cmbmem -c once booted. The qemu command that was used was: qemu-system-i386 -bios ./build/coreboot.rom -serial stdio -hda ../virt/parabola.img Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that: Loading image. CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes) Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050 Processing 1703 relocs with adjust value of 0x3ffbe000 FATAL: Essential component is missing. However without CONFIG_RELOCATABLE_RAMSTAGE set it boots fine. Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/3504 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3504 for details. -gerrit

1 0

New patch to review for coreboot: 4b5bf20 Asus F2A85-M: Activate IOMMU support
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3517 -gerrit commit 4b5bf202bd273a58174d64210a5ff12e7daefaef Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:12:00 2013 +0200 Asus F2A85-M: Activate IOMMU support Activate the IOMMU support for the Asus F2A85-M, by enabling it in `buildOpts.c` and by adding the device to `devicetree.cb`. The device shows up in the output of `lspci`. $ lspci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit The Linux kernel is also able to set it up. $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] [ 0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS […] [ 0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000 [ 0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600 [ 0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000 […] [ 0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT] [ 0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT] [ 0.598073] pci0000:00: >Requesting ACPI _OSC control (0x1d) [ 0.603808] pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.620508] Freeing initrd memory: 14876k freed […] [ 0.882674] pci 0000:00:01.0: >Boot video device [ 0.882876] PCI: CLS 64 bytes, default 64 [ 0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features: PreF PPR GT IA [ 0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X [ 0.917457] AMD-Vi: Lazy IO/TLB flushing enabled [ 0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff] [ 0.938535] LVT offset 0 assigned for vector 0x400 [ 0.943338] perf: AMD IBS detected (0x000000ff) [ 0.948037] audit: initializing netlink socket (disabled) [ 0.953432] type=2000 audit(1369659616.800:1): initialized [ 0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages […] [ 7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) [ 7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF […] [ 7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X [ 7.885525] radeon 0000:00:01.0: >radeon: using MSI. […] [ 8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010] [ 8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010] [ 8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010] [ 8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010] [ 8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010] [ 8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010] [ 8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010] [ 8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010] [ 8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010] [ 8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010] [ 8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010] [ 8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010] [ 8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010] [ 8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010] [ 8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010] [ 8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010] [ 8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010] [ 8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010] [ 8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010] [ 8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010] [ 8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010] [ 8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010] [ 8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010] [ 8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010] [ 8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010] [ 8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010] [ 8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010] [ 8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010] [ 8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010] [ 8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010] [ 8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010] […] [ 8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010] [ 8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010] [ 8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010] [ 8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010] [ 8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010] [ 8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010] [ 8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010] [ 8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010] [ 8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010] [ 8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010] [ 8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010] [ 8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010] [ 8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010] [ 8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010] [ 8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010] [ 8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010] [ 8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010] [ 8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010] [ 8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010] [ 8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010] [ 8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010] [ 8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010] [ 8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010] [ 8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010] [ 8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010] [ 8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010] [ 8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010] [ 8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010] [ 8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010] [ 8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010] [ 8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010] [ 8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010] [ 8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010] [ 8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 8.963165] radeon 0000:00:01.0: >WB enabled […] It is not known, what the implications of the `IO_PAGE_FAULT` are. Change-Id: I0aa530be17d31656e65db6113343f2ea7008b843 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..4080e8b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -171,7 +171,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..1cc610e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 blue

1 0

New patch to review for coreboot: 77b345b AMD boards: routing.asl: Uniformly start `Package()` with capital letter
by Paul Menzel 22 Jun '13

22 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3516 -gerrit commit 77b345b528c474b69165d7d492ceeefd85e06744 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 22 13:47:06 2013 +0200 AMD boards: routing.asl: Uniformly start `Package()` with capital letter In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/acpi/routing.asl | 2 +- src/mainboard/amd/bimini_fam10/acpi/routing.asl | 2 +- src/mainboard/amd/dbm690t/acpi/routing.asl | 2 +- src/mainboard/amd/inagua/acpi/routing.asl | 2 +- src/mainboard/amd/mahogany/acpi/routing.asl | 2 +- src/mainboard/amd/mahogany_fam10/acpi/routing.asl | 2 +- src/mainboard/amd/parmer/acpi/routing.asl | 2 +- src/mainboard/amd/persimmon/acpi/routing.asl | 2 +- src/mainboard/amd/pistachio/acpi/routing.asl | 2 +- src/mainboard/amd/south_station/acpi/routing.asl | 2 +- src/mainboard/amd/thatcher/acpi/routing.asl | 2 +- src/mainboard/amd/tilapia_fam10/acpi/routing.asl | 2 +- src/mainboard/amd/union_station/acpi/routing.asl | 2 +- src/mainboard/asrock/939a785gmh/acpi/routing.asl | 2 +- src/mainboard/asrock/e350m1/acpi/routing.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/routing.asl | 2 +- src/mainboard/asus/m4a78-em/acpi/routing.asl | 2 +- src/mainboard/asus/m4a785-m/acpi/routing.asl | 2 +- src/mainboard/asus/m4a785t-m/acpi/routing.asl | 2 +- src/mainboard/asus/m5a88-v/acpi/routing.asl | 2 +- src/mainboard/avalue/eax-785e/acpi/routing.asl | 2 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 4 ++-- src/mainboard/gigabyte/ma785gm/acpi/routing.asl | 2 +- src/mainboard/gigabyte/ma785gmt/acpi/routing.asl | 2 +- src/mainboard/gigabyte/ma78gm/acpi/routing.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl | 2 +- src/mainboard/jetway/pa78vm5/acpi/routing.asl | 2 +- src/mainboard/lippert/frontrunner-af/acpi/routing.asl | 2 +- src/mainboard/lippert/toucan-af/acpi/routing.asl | 2 +- src/mainboard/technexion/tim5690/acpi/routing.asl | 2 +- src/mainboard/technexion/tim8690/acpi/routing.asl | 2 +- 31 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/acpi/routing.asl b/src/mainboard/advansus/a785e-i/acpi/routing.asl index afea792..87a79f9 100644 --- a/src/mainboard/advansus/a785e-i/acpi/routing.asl +++ b/src/mainboard/advansus/a785e-i/acpi/routing.asl @@ -116,7 +116,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/bimini_fam10/acpi/routing.asl b/src/mainboard/amd/bimini_fam10/acpi/routing.asl index f8d2384..e9df95f 100644 --- a/src/mainboard/amd/bimini_fam10/acpi/routing.asl +++ b/src/mainboard/amd/bimini_fam10/acpi/routing.asl @@ -116,7 +116,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/dbm690t/acpi/routing.asl b/src/mainboard/amd/dbm690t/acpi/routing.asl index 28004e9..8f7419a 100644 --- a/src/mainboard/amd/dbm690t/acpi/routing.asl +++ b/src/mainboard/amd/dbm690t/acpi/routing.asl @@ -83,7 +83,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 1e62117..98ad439 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/mahogany/acpi/routing.asl b/src/mainboard/amd/mahogany/acpi/routing.asl index fd04128..bbcc61d 100644 --- a/src/mainboard/amd/mahogany/acpi/routing.asl +++ b/src/mainboard/amd/mahogany/acpi/routing.asl @@ -89,7 +89,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl index 78592c4..fa366d8 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl @@ -120,7 +120,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl index 4967edb..1b37c76 100644 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ b/src/mainboard/amd/parmer/acpi/routing.asl @@ -110,7 +110,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, - package(){0x0001FFFF, 1, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index e98047c..0395700 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -100,7 +100,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/pistachio/acpi/routing.asl b/src/mainboard/amd/pistachio/acpi/routing.asl index 28004e9..8f7419a 100644 --- a/src/mainboard/amd/pistachio/acpi/routing.asl +++ b/src/mainboard/amd/pistachio/acpi/routing.asl @@ -83,7 +83,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 1e62117..98ad439 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl index 4967edb..1b37c76 100644 --- a/src/mainboard/amd/thatcher/acpi/routing.asl +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -110,7 +110,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, - package(){0x0001FFFF, 1, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/tilapia_fam10/acpi/routing.asl b/src/mainboard/amd/tilapia_fam10/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi/routing.asl +++ b/src/mainboard/amd/tilapia_fam10/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 1e62117..98ad439 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl index 5aff356..2ce49b1 100644 --- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl +++ b/src/mainboard/asrock/939a785gmh/acpi/routing.asl @@ -70,7 +70,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 1e62117..98ad439 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 03027c3..1f2d63c 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -87,7 +87,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, - package(){0x0001FFFF, 1, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/m4a78-em/acpi/routing.asl b/src/mainboard/asus/m4a78-em/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/asus/m4a78-em/acpi/routing.asl +++ b/src/mainboard/asus/m4a78-em/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/m4a785-m/acpi/routing.asl b/src/mainboard/asus/m4a785-m/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/asus/m4a785-m/acpi/routing.asl +++ b/src/mainboard/asus/m4a785-m/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/routing.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/m5a88-v/acpi/routing.asl b/src/mainboard/asus/m5a88-v/acpi/routing.asl index afea792..87a79f9 100644 --- a/src/mainboard/asus/m5a88-v/acpi/routing.asl +++ b/src/mainboard/asus/m5a88-v/acpi/routing.asl @@ -116,7 +116,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/avalue/eax-785e/acpi/routing.asl b/src/mainboard/avalue/eax-785e/acpi/routing.asl index afea792..87a79f9 100644 --- a/src/mainboard/avalue/eax-785e/acpi/routing.asl +++ b/src/mainboard/avalue/eax-785e/acpi/routing.asl @@ -116,7 +116,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 3ae2154..0e8da7b 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -200,7 +200,7 @@ DefinitionBlock ( #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) - Name(PRTP, package() { + Name(PRTP, Package() { prt_slot_lnkE(0x0000), prt_slot_lnkF(0x0001), prt_slot_lnkG(0x0002), @@ -257,7 +257,7 @@ DefinitionBlock ( #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) - Name(PRTA, package() { + Name(PRTA, Package() { prt_slot_gsiE(0x0000), prt_slot_gsiF(0x0001), prt_slot_gsiG(0x0002), diff --git a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl +++ b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl b/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl index 66b5c3d..7b54b24 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl +++ b/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl @@ -84,7 +84,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/gigabyte/ma78gm/acpi/routing.asl b/src/mainboard/gigabyte/ma78gm/acpi/routing.asl index fd04128..bbcc61d 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi/routing.asl +++ b/src/mainboard/gigabyte/ma78gm/acpi/routing.asl @@ -89,7 +89,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl index 78592c4..fa366d8 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl @@ -120,7 +120,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/jetway/pa78vm5/acpi/routing.asl b/src/mainboard/jetway/pa78vm5/acpi/routing.asl index fd04128..bbcc61d 100644 --- a/src/mainboard/jetway/pa78vm5/acpi/routing.asl +++ b/src/mainboard/jetway/pa78vm5/acpi/routing.asl @@ -89,7 +89,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index b894719..907b0e4 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl index 7a871da..2a61ce3 100644 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ b/src/mainboard/lippert/toucan-af/acpi/routing.asl @@ -122,7 +122,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ Package(){0x0001FFFF, 0, 0, 18 }, - package(){0x0001FFFF, 1, 0, 19 }, + Package(){0x0001FFFF, 1, 0, 19 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/technexion/tim5690/acpi/routing.asl b/src/mainboard/technexion/tim5690/acpi/routing.asl index 28004e9..8f7419a 100644 --- a/src/mainboard/technexion/tim5690/acpi/routing.asl +++ b/src/mainboard/technexion/tim5690/acpi/routing.asl @@ -83,7 +83,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/technexion/tim8690/acpi/routing.asl b/src/mainboard/technexion/tim8690/acpi/routing.asl index 28004e9..8f7419a 100644 --- a/src/mainboard/technexion/tim8690/acpi/routing.asl +++ b/src/mainboard/technexion/tim8690/acpi/routing.asl @@ -83,7 +83,7 @@ Scope(\_SB) { /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ + /* Package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 },

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coreboot-gerrit June 2013