coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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744 discussions

Patch set updated for coreboot: 8e30c7c qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM.
by Denis Carikli 21 Jun '13

21 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3504 -gerrit commit 8e30c7c0c715d6a0a621922500c43b3a01861b06 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 19 08:30:33 2013 +0200 qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM. This commit was tested on qemu with and without CONFIG_DYNAMIC_CBMEM by running cmbmem -c once booted. The qemu command that was used was: qemu-system-i386 -bios ./build/coreboot.rom -serial stdio -hda ../virt/parabola.img Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that: Loading image. CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes) Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050 Processing 1703 relocs with adjust value of 0x3ffbe000 FATAL: Essential component is missing. However without CONFIG_RELOCATABLE_RAMSTAGE set it boots fine. Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/emulation/qemu-i440fx/memory.c | 8 ++++++++ src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 8245ca2..000a0f6 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -46,7 +46,15 @@ unsigned long get_top_of_ram(void) return qemu_get_memory_size() * 1024; } +#if !CONFIG_DYNAMIC_CBMEM struct cbmem_entry *get_cbmem_toc(void) { return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); } +#else +void *cbmem_top(void) +{ + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + return (void *)get_top_of_ram(); +} +#endif diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 96d016b..3e45d9a 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -53,9 +53,11 @@ static void cpu_pci_domain_read_resources(struct device *dev) if (high) ram_resource(dev, idx++, 4 * 1024 * 1024, high); +#if !CONFIG_DYNAMIC_CBMEM /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; +#endif /* Reserve space for the IOAPIC. This should be in the Southbridge, * but I couldn't tell which device to put it in. */

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New patch to review for coreboot: ea3858e Add support for DMP Vortex86EX PCI northbridge.
by Andrew Wu 21 Jun '13

21 Jun '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3511 -gerrit commit ea3858e608772ecd92c964c7a94d80f562b46405 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Jun 21 21:37:05 2013 +0800 Add support for DMP Vortex86EX PCI northbridge. Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/northbridge/Kconfig | 1 + src/northbridge/Makefile.inc | 1 + src/northbridge/dmp/Kconfig | 20 ++ src/northbridge/dmp/Makefile.inc | 20 ++ src/northbridge/dmp/vortex86ex/Kconfig | 21 ++ src/northbridge/dmp/vortex86ex/Makefile.inc | 21 ++ src/northbridge/dmp/vortex86ex/chip.h | 26 +++ src/northbridge/dmp/vortex86ex/northbridge.c | 146 ++++++++++++ src/northbridge/dmp/vortex86ex/northbridge.h | 69 ++++++ src/northbridge/dmp/vortex86ex/raminit.c | 325 +++++++++++++++++++++++++++ src/northbridge/dmp/vortex86ex/xgi_oprom.c | 35 +++ 11 files changed, 685 insertions(+) diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig index b2b8abe..0ac09a6 100644 --- a/src/northbridge/Kconfig +++ b/src/northbridge/Kconfig @@ -1,4 +1,5 @@ source src/northbridge/amd/Kconfig +source src/northbridge/dmp/Kconfig source src/northbridge/intel/Kconfig source src/northbridge/rdc/Kconfig source src/northbridge/via/Kconfig diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc index 283ba4e..1a5b1c8 100644 --- a/src/northbridge/Makefile.inc +++ b/src/northbridge/Makefile.inc @@ -1,4 +1,5 @@ subdirs-y += amd +subdirs-y += dmp subdirs-y += intel subdirs-y += rdc subdirs-y += via diff --git a/src/northbridge/dmp/Kconfig b/src/northbridge/dmp/Kconfig new file mode 100644 index 0000000..a69d1d9 --- /dev/null +++ b/src/northbridge/dmp/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 DMP Electronics Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/northbridge/dmp/vortex86ex/Kconfig diff --git a/src/northbridge/dmp/Makefile.inc b/src/northbridge/dmp/Makefile.inc new file mode 100644 index 0000000..3cfcc48 --- /dev/null +++ b/src/northbridge/dmp/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 DMP Electronics Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX) += vortex86ex diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig new file mode 100644 index 0000000..7bf5235 --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/Kconfig @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 DMP Electronics Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_DMP_VORTEX86EX + bool diff --git a/src/northbridge/dmp/vortex86ex/Makefile.inc b/src/northbridge/dmp/vortex86ex/Makefile.inc new file mode 100644 index 0000000..82b07fd --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 DMP Electronics Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += northbridge.c +ramstage-y += xgi_oprom.c diff --git a/src/northbridge/dmp/vortex86ex/chip.h b/src/northbridge/dmp/vortex86ex/chip.h new file mode 100644 index 0000000..93384c4 --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NORTHBRIDGE_DMP_VORTEX86EX +#define _NORTHBRIDGE_DMP_VORTEX86EX + +struct northbridge_dmp_vortex86ex_config { +}; + +#endif /* _NORTHBRIDGE_DMP_VORTEX86EX */ diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c new file mode 100644 index 0000000..e3be6c3 --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" +#include "northbridge.h" + +#define SPI_BASE 0xfc00 + +static void northbridge_init(device_t dev) +{ + printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); + // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. + pci_write_config32(dev, NB_REG_MAR, 0x3ff000f0); + // enable C0000h - C3FFFh/C4000h - C7FFF can be in L1 cache selection. + pci_write_config32(dev, NB_REG_HOST_CTL, (1 << 18) | (1 << 19)); + // Set SPI register base. + pci_write_config16(dev, NB_REG_SPI_BASE, SPI_BASE | 1); +} + +static struct device_operations northbridge_operations = { + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init +}; + +static const struct pci_driver northbridge_driver_6021 __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x6021, /* DX CPU N/B ID */ +}; + +static const struct pci_driver northbridge_driver_6025 __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x6025, /* EX CPU N/B ID */ +}; + +/* Set CMOS register 15h/16h/17h/18h for base/extended + * memory size. */ +static void set_cmos_memory_size(unsigned long sizek) +{ + unsigned long ext_mem_size; + u8 ext_mem_size_hb, ext_mem_size_lb; + /* calculate memory size between 1M - 65M. */ + ext_mem_size = sizek - 1024; + if (ext_mem_size > 65535) + ext_mem_size = 65535; + ext_mem_size_hb = (u8) (ext_mem_size >> 8); + ext_mem_size_lb = (u8) (ext_mem_size & 0xff); + /* Base memory is always 640K. */ + cmos_write(0x80, 0x15); + cmos_write(0x02, 0x16); + /* Write extended memory size. */ + cmos_write(ext_mem_size_lb, 0x17); + cmos_write(ext_mem_size_hb, 0x18); + /* register 0x30(48) is RTC_BOOT_BYTE for coreboot, + * don't touch it. */ +} + +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + + printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); + + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; + if (mc_dev) { + unsigned long tomk, tolmk; + int idx; + int ss; + /* Get DDRII size setting from northbridge register. */ + /* SS = 0 for 2MB, 1 for 4MB, 2 for 8MB, 3 for 16MB ... */ + ss = pci_read_config16(mc_dev, 0x6c); + ss = ((ss >> 8) & 0xf); + tomk = (2 * 1024) << ss; + printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10)); + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) + /* The PCI hole does does not overlap the memory. + */ + tolmk = tomk; + + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk * 1024, high_tables_base, high_tables_size); + + /* Report the memory regions */ + idx = 10; + ram_resource(dev, idx++, 0, 640); /* first 640k */ + ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */ + set_cmos_memory_size(tolmk); + } + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +}; + +static void enable_dev(struct device *dev) +{ + printk(BIOS_SPEW, "In vortex86ex enable_dev for device %s.\n", dev_path(dev)); + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } +} + +struct chip_operations northbridge_dmp_vortex86ex_ops = { + CHIP_NAME("DMP Vortex86EX Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/dmp/vortex86ex/northbridge.h b/src/northbridge/dmp/vortex86ex/northbridge.h new file mode 100644 index 0000000..e6f21cd --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/northbridge.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_H +#define NORTHBRIDGE_H + +#define NB PCI_DEV(0, 0, 0) +#define NB_REG_SPI_BASE 0x40 +#define NB_REG_CLK_OUT_CTL 0x48 +#define NB_REG_PCI_CLK_CTL 0x4b +#define NB_REG_STRAP 0x60 +#define NB_REG_STRAP2 0x64 +#define NB_REG_MBR 0x6c +#define NB_REG_DDR3_CFG 0x74 +#define NB_REG_DDR3_MTR1 0x78 +#define NB_REG_DDR3_MTR2 0x7c +#define NB_REG_SMM 0x83 +#define NB_REG_MAR 0x84 +#define NB_REG_CID 0x90 +#define NB_REG_S1R 0x94 +#define NB_REG_S2R 0x98 +#define NB_REG_S3R 0x9c +#define NB_REG_HOST_CTL 0xa0 +#define NB_REG_CPU_MBCR 0xc4 +#define NB_REG_CDR 0xd0 +#define NB_REG_PACR 0xf0 +#define NB_REG_PMCR 0xf4 +#define NB_REG_PCI_TARGET 0xf8 +#define NB_REG_PCSCR 0xfc + +/* Additional "virtual" device, just extension of NB */ +#define NB1 PCI_DEV(0, 0, 1) +#define NB1_REG_FJZ_PHY_CTL1 0x80 +#define NB1_REG_FJZ_PHY_CTL2 0x84 +#define NB1_REG_FJZ_PHY_CTL3 0x88 +#define NB1_REG_FJZ_DRAM_CTL1 0x90 +#define NB1_REG_FJZ_DRAM_CTL2 0x94 +#define NB1_REG_FJZ_DRAM_CTL3 0x98 +#define NB1_REG_FJZ_DRAM_CTL4 0x9c +#define NB1_REG_PLL_TEST_CTL 0xa8 +#define NB1_REG_DDR3_PWR_SAV 0xbc +#define NB1_REG_DDR3_CTL_OPT1 0xc0 +#define NB1_REG_DDR3_CTL_OPT3 0xc8 +#define NB1_REG_DDR3_CTL_OPT4 0xcc +#define NB1_REG_DDR3_CTL_OPT5 0xce +#define NB1_REG_PLL_TEST_MODE 0xd0 +#define NB1_REG_L2_CACHE_CTL 0xe8 +#define NB1_REG_SSCR 0xec +#define NB1_REG_NB_CTL_OPT1 0xf4 +#define NB1_REG_UPDATE_PHY_IO 0xf8 +#define NB1_REG_RESET_DRAMC_PHY 0xfa + +#endif /* NORTHBRIDGE_H */ diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c new file mode 100644 index 0000000..2382fe2 --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/raminit.c @@ -0,0 +1,325 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static u16 get_mask(u16 bit_width, u16 bit_offset) +{ + u16 mask = (((1 << bit_width) - 1) << bit_offset); + return mask; +} + +static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset) +{ + u16 mask = get_mask(bit_width, bit_offset); + val = (val & ~mask) | (bits << bit_offset); + return val; +} + +static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset) +{ + u16 mask = get_mask(bit_width, bit_offset); + return (val & mask) >> bit_offset; +} + +static u8 check_address_bit(int addr_bit) +{ + u16 dummy; + *(volatile u16 *)(0) = 0; + dummy = *(volatile u16 *)(0); // read push write + *(volatile u16 *)(1 << addr_bit) = 0x5a5a; + dummy = *(volatile u16 *)(1 << addr_bit); // read push write + if ((*(volatile u16 *)(0)) != 0) + return 0; // address bit wrapped. + return 1; // address bit not wrapped. +} + +static u8 check_dram_side(int addr_bit) +{ + *(volatile u16 *)(1 << addr_bit) = 0x5a5a; + *(volatile u16 *)(0) = 0; + if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a) + return 0; // DRAM only one side. + return 1; // two sides. +} + +// DDRIII memory bank register control: +// bit : +// 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit +// : 0 0 1 = 11bit +// 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit +// : 0 0 1 = 14bit +// : 0 1 0 = 15bit +// : 0 1 1 = 16bit +// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M +// : 0 1 1 0 = 128M +// : 0 1 1 1 = 256M +// : 1 0 0 0 = 512M +// : 1 0 0 1 = 1GB +// : 1 0 1 0 = 2GB +// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable + +#define DDR3_COL_10BIT 0 +#define DDR3_COL_11BIT 1 +#define DDR3_ROW_13BIT 0 +#define DDR3_ROW_14BIT 1 +#define DDR3_ROW_15BIT 2 +#define DDR3_ROW_16BIT 3 +#define DDR3_SIZE_64M 5 +#define DDR3_SIZE_128M 6 +#define DDR3_SIZE_256M 7 +#define DDR3_SIZE_512M 8 +#define DDR3_SIZE_1GB 9 +#define DDR3_SIZE_2GB 10 +#define DDR3_C1M_ACTIVE 0 +#define DDR3_C1M_MASK 1 + +static u16 set_ddr3_mem_reg_col(u16 reg, u16 col) +{ + return set_bitfield(reg, col, 3, 0); +} + +static u16 get_ddr3_mem_reg_col(u16 reg) +{ + return get_bitfield(reg, 3, 0); +} + +static u16 set_ddr3_mem_reg_row(u16 reg, u16 row) +{ + return set_bitfield(reg, row, 3, 5); +} + +static u16 get_ddr3_mem_reg_row(u16 reg) +{ + return get_bitfield(reg, 3, 5); +} + +static u16 set_ddr3_mem_reg_size(u16 reg, u16 size) +{ + return set_bitfield(reg, size, 4, 8); +} + +static u16 get_ddr3_mem_reg_size(u16 reg) +{ + return get_bitfield(reg, 4, 8); +} + +static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m) +{ + return set_bitfield(reg, c1m, 1, 13); +} + +static u16 get_ddr3_mem_reg_c1m(u16 reg) +{ + return get_bitfield(reg, 1, 13); +} + +static u16 auto_set_ddr3_mem_reg_size(u16 reg) +{ + u8 ss = 0; + // If reg is the minimum DRAM size, + // SS is also the minimum size 128M. + // If size in reg is bigger, SS is also bigger. + ss += get_ddr3_mem_reg_col(reg); + ss += get_ddr3_mem_reg_row(reg); + ss += (1 - get_ddr3_mem_reg_c1m(reg)); + ss += DDR3_SIZE_128M; + return set_ddr3_mem_reg_size(reg, ss); +} + +static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m) +{ + u16 reg; + reg = 0; + reg = set_ddr3_mem_reg_col(reg, col); + reg = set_ddr3_mem_reg_row(reg, row); + reg = set_ddr3_mem_reg_c1m(reg, c1m); + reg = auto_set_ddr3_mem_reg_size(reg); + return reg; +} + +static void ddr3_phy_reset(void) +{ + // PCI N/B reg FAh bit 6 = RST_DRAM_PHY. + pci_write_config8(NB1, NB1_REG_RESET_DRAMC_PHY, 0x40); + while ((pci_read_config8(NB1, NB1_REG_RESET_DRAMC_PHY) & 0x40) == 0x40) { + } + // reload mode. + u32 ddr3_cfg = pci_read_config32(NB, NB_REG_DDR3_CFG); + pci_write_config32(NB, NB_REG_DDR3_CFG, ddr3_cfg); +} + +static u8 detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit) +{ + reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_dram_side(base_addr_bit + 1)) { + base_addr_bit += 1; + return 0; + } + + reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + // no need to check CS = 0. + // Need to reset DDR3 PHY. + ddr3_phy_reset(); + return 0; +} + +static u8 detect_ddr3_dram_row(u16 reg, u8 base_addr_bit) +{ + reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 16)) { + base_addr_bit += 16; + return detect_ddr3_dram_cs(reg, base_addr_bit); + } + + reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 15)) { + base_addr_bit += 15; + return detect_ddr3_dram_cs(reg, base_addr_bit); + } + + reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 14)) { + base_addr_bit += 14; + return detect_ddr3_dram_cs(reg, base_addr_bit); + } + + reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 13)) { + base_addr_bit += 13; + return detect_ddr3_dram_cs(reg, base_addr_bit); + } + // row test error. + return 1; +} + +static u8 detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit) +{ + /* DDR3 is always 3 bank bits */ + base_addr_bit += 3; + return detect_ddr3_dram_row(reg, base_addr_bit); +} + +static u8 detect_ddr3_dram_col(u16 reg, u8 base_addr_bit) +{ + reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 11)) { + base_addr_bit += 11; + return detect_ddr3_dram_bank(reg, base_addr_bit); + } + + reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT); + reg = auto_set_ddr3_mem_reg_size(reg); + pci_write_config16(NB, NB_REG_MBR, reg); + if (check_address_bit(base_addr_bit + 10)) { + base_addr_bit += 10; + return detect_ddr3_dram_bank(reg, base_addr_bit); + } + // col test error. + return 1; +} + +static u8 detect_ddr3_dram_size(void) +{ + u16 reg; + u8 base_addr_bit = 0; + reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK); + return detect_ddr3_dram_col(reg, base_addr_bit); +} + +static void print_ddr3_memory_setup(void) +{ +#if CONFIG_DEBUG_RAM_SETUP + print_debug("DDR3 Timing Reg 0-3:\n"); + print_debug("NB 6e : "); + print_debug_hex16(pci_read_config16(NB, 0x6e)); + print_debug("\nNB 74 : "); + print_debug_hex32(pci_read_config32(NB, 0x74)); + print_debug("\nNB 78 : "); + print_debug_hex32(pci_read_config32(NB, 0x78)); + print_debug("\nNB 7c : "); + print_debug_hex32(pci_read_config32(NB, 0x7c)); + u16 mbr = pci_read_config16(NB, 0x6c); + print_debug("\nNB 6c(MBR) : "); + print_debug_hex16(mbr); + const char *s; + u8 col = get_ddr3_mem_reg_col(mbr); + if (col == DDR3_COL_10BIT) + s = " (COL=10"; + else + s = " (COL=11"; + print_debug(s); + u8 row = get_ddr3_mem_reg_row(mbr); + switch (row) { + case DDR3_ROW_13BIT: + s = ", ROW = 13"; + break; + case DDR3_ROW_14BIT: + s = ", ROW = 14"; + break; + case DDR3_ROW_15BIT: + s = ", ROW = 15"; + break; + default: + s = ", ROW = 16"; + break; + } + print_debug(s); + u8 size = get_ddr3_mem_reg_size(mbr); + switch (size) { + case DDR3_SIZE_64M: + s = ", 64M"; + break; + case DDR3_SIZE_128M: + s = ", 128M"; + break; + case DDR3_SIZE_256M: + s = ", 256M"; + break; + case DDR3_SIZE_512M: + s = ", 512M"; + break; + case DDR3_SIZE_1GB: + s = ", 1GB"; + break; + case DDR3_SIZE_2GB: + s = ", 2GB"; + break; + } + print_debug(s); + u8 mask = get_ddr3_mem_reg_c1m(mbr); + if (mask == DDR3_C1M_ACTIVE) + s = ", CS MASK Enable)\n"; + else + s = ", CS Mask Disable)\n"; + print_debug(s); +#endif +} diff --git a/src/northbridge/dmp/vortex86ex/xgi_oprom.c b/src/northbridge/dmp/vortex86ex/xgi_oprom.c new file mode 100644 index 0000000..dc814c2 --- /dev/null +++ b/src/northbridge/dmp/vortex86ex/xgi_oprom.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/******************************************************************** + * Change the vendor / device IDs to match the XGI Z9S VBIOS header. + ********************************************************************/ +#include <device/pci.h> +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x18ca0020: + new_vendev = 0x18ca0021; + break; + } + + return new_vendev; +}

1 0

Patch merged into coreboot/master: e761b71 bd82x6x: Fix early EHCI BAR programming
by gerrit＠coreboot.org 21 Jun '13

21 Jun '13

the following patch was just integrated into master: commit e761b71e52e699abcfd22cc5e931b89cf354476e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 12:29:23 2013 +0300 bd82x6x: Fix early EHCI BAR programming Change EHCI #2 to different BAR from EHCI #1. Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles. Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3471 for details. -gerrit

1 0

Patch set updated for coreboot: 1b33637 bd82x6x: Fix early EHCI BAR programming
by Nico Huber 21 Jun '13

21 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3471 -gerrit commit 1b33637c4ed122c205d3e4fd2c6207cff961b551 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 12:29:23 2013 +0300 bd82x6x: Fix early EHCI BAR programming Change EHCI #2 to different BAR from EHCI #1. Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles. Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/early_usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index f4e526d..baf8c4f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -49,9 +49,9 @@ void enable_usb_bar(void) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd); - /* USB Controller 1 */ + /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd);

1 0

New patch to review for coreboot: 10ed74c Add simple_device_t
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3508 -gerrit commit 10ed74c6d50a969f5d82ed8056a9940c1178bef7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 20 20:25:21 2013 +0300 Add simple_device_t Declare the functions that may be used in both romstage and ramstage to use simple_device_t instead. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 71 +++++++++++++++++---------------- src/arch/x86/include/arch/pcie_config.h | 18 ++++----- 2 files changed, 45 insertions(+), 44 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..33d124a 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -206,14 +206,15 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +typedef unsigned int simple_device_t; +typedef simple_device_t device_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ -static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(simple_device_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -226,14 +227,14 @@ static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_ } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(simple_device_t dev, unsigned where) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; return read8(addr); } #endif -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint8_t pci_read_config8(simple_device_t dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config8(dev, where); @@ -242,7 +243,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d #endif } -static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(simple_device_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -255,7 +256,7 @@ static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(simple_device_t dev, unsigned where) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); @@ -263,7 +264,7 @@ static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(dev } #endif -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint16_t pci_read_config16(simple_device_t dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config16(dev, where); @@ -273,7 +274,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t } -static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(simple_device_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -286,7 +287,7 @@ static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(simple_device_t dev, unsigned where) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); @@ -294,7 +295,7 @@ static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(dev } #endif -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint32_t pci_read_config32(simple_device_t dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config32(dev, where); @@ -303,7 +304,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t #endif } -static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) void pci_io_write_config8(simple_device_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -316,7 +317,7 @@ static inline __attribute__((always_inline)) void pci_io_write_config8(device_t } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) void pci_mmio_write_config8(simple_device_t dev, unsigned where, uint8_t value) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; @@ -324,7 +325,7 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_ } #endif -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) void pci_write_config8(simple_device_t dev, unsigned where, uint8_t value) { #if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config8(dev, where, value); @@ -334,7 +335,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev } -static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) void pci_io_write_config16(simple_device_t dev, unsigned where, uint16_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -347,7 +348,7 @@ static inline __attribute__((always_inline)) void pci_io_write_config16(device_t } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) void pci_mmio_write_config16(simple_device_t dev, unsigned where, uint16_t value) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); @@ -355,7 +356,7 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config16(device } #endif -static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) void pci_write_config16(simple_device_t dev, unsigned where, uint16_t value) { #if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config16(dev, where, value); @@ -365,7 +366,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de } -static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) void pci_io_write_config32(simple_device_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -378,7 +379,7 @@ static inline __attribute__((always_inline)) void pci_io_write_config32(device_t } #if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) void pci_mmio_write_config32(simple_device_t dev, unsigned where, uint32_t value) { unsigned addr; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); @@ -386,7 +387,7 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config32(device } #endif -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) void pci_write_config32(simple_device_t dev, unsigned where, uint32_t value) { #if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config32(dev, where, value); @@ -395,23 +396,23 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de #endif } -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) void pci_or_config8(simple_device_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) void pci_or_config16(simple_device_t dev, unsigned where, uint16_t value) { pci_write_config16(dev, where, pci_read_config16(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) void pci_or_config32(simple_device_t dev, unsigned where, uint32_t value) { pci_write_config32(dev, where, pci_read_config32(dev, where) | value); } #define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +static inline simple_device_t pci_io_locate_device(unsigned pci_id, simple_device_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -423,7 +424,7 @@ static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +static inline simple_device_t pci_locate_device(unsigned pci_id, simple_device_t dev) { for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -435,9 +436,9 @@ static inline device_t pci_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static inline simple_device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + simple_device_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); @@ -453,53 +454,53 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) } /* Generic functions for pnp devices */ -static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +static inline __attribute__((always_inline)) void pnp_write_config(simple_device_t dev, uint8_t reg, uint8_t value) { unsigned port = dev >> 8; outb(reg, port ); outb(value, port +1); } -static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) +static inline __attribute__((always_inline)) uint8_t pnp_read_config(simple_device_t dev, uint8_t reg) { unsigned port = dev >> 8; outb(reg, port); return inb(port +1); } -static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) +static inline __attribute__((always_inline)) void pnp_set_logical_device(simple_device_t dev) { unsigned device = dev & 0xff; pnp_write_config(dev, 0x07, device); } -static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) +static inline __attribute__((always_inline)) void pnp_set_enable(simple_device_t dev, int enable) { pnp_write_config(dev, 0x30, enable?0x1:0x0); } -static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) +static inline __attribute__((always_inline)) int pnp_read_enable(simple_device_t dev) { return !!pnp_read_config(dev, 0x30); } -static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +static inline __attribute__((always_inline)) void pnp_set_iobase(simple_device_t dev, unsigned index, unsigned iobase) { pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); pnp_write_config(dev, index + 1, iobase & 0xff); } -static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) +static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(simple_device_t dev, unsigned index) { return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); } -static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +static inline __attribute__((always_inline)) void pnp_set_irq(simple_device_t dev, unsigned index, unsigned irq) { pnp_write_config(dev, index, irq); } -static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +static inline __attribute__((always_inline)) void pnp_set_drq(simple_device_t dev, unsigned index, unsigned drq) { pnp_write_config(dev, index, drq & 0xff); } diff --git a/src/arch/x86/include/arch/pcie_config.h b/src/arch/x86/include/arch/pcie_config.h index 672457d..61afd7f 100644 --- a/src/arch/x86/include/arch/pcie_config.h +++ b/src/arch/x86/include/arch/pcie_config.h @@ -20,7 +20,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) +u8 pcie_read_config8(simple_device_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -28,7 +28,7 @@ u8 pcie_read_config8(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) +u16 pcie_read_config16(simple_device_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -36,7 +36,7 @@ u16 pcie_read_config16(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) +u32 pcie_read_config32(simple_device_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -44,7 +44,7 @@ u32 pcie_read_config32(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) +void pcie_write_config8(simple_device_t dev, unsigned int where, u8 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -52,7 +52,7 @@ void pcie_write_config8(device_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) +void pcie_write_config16(simple_device_t dev, unsigned int where, u16 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -60,7 +60,7 @@ void pcie_write_config16(device_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) +void pcie_write_config32(simple_device_t dev, unsigned int where, u32 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -68,21 +68,21 @@ void pcie_write_config32(device_t dev, unsigned int where, u32 value) } static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +void pcie_or_config8(simple_device_t dev, unsigned int where, u8 ormask) { u8 value = pcie_read_config8(dev, where); pcie_write_config8(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +void pcie_or_config16(simple_device_t dev, unsigned int where, u16 ormask) { u16 value = pcie_read_config16(dev, where); pcie_write_config16(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +void pcie_or_config32(simple_device_t dev, unsigned int where, u32 ormask) { u32 value = pcie_read_config32(dev, where); pcie_write_config32(dev, where, value | ormask);

1 0

New patch to review for coreboot: 4dc0fbb intel/sch: Use MMCONF_BASE_ADDRESS
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3507 -gerrit commit 4dc0fbbdba17160d5b8264c19091fd34e24b1fc1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 intel/sch: Use MMCONF_BASE_ADDRESS For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused and different from hardware setting. Change that to match hardware programming. Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/iwave/iWRainbowG6/Kconfig | 2 +- src/northbridge/intel/sch/sch.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 7e05aae..e908fcf 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xe0000000 config IRQ_SLOT_COUNT int diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 4f49beb..5700842 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); #define DEFAULT_RCBABASE 0xfed1c000 -#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ /* IGD */ #define GGC 0x52

1 0

Patch set updated for coreboot: 3071785 Drop some duplicates of PCI-e config functions
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502 -gerrit commit 30717856261e86c2a6bcae6b02764c3e769b49a0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 Drop some duplicates of PCI-e config functions These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pcie_config.h | 89 +++++++++++++++++++++++++ src/mainboard/google/stout/mainboard_smi.c | 2 +- src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/i945/pcie_config.c | 68 ------------------- src/northbridge/intel/sandybridge/early_init.c | 2 +- src/northbridge/intel/sandybridge/finalize.c | 2 +- src/northbridge/intel/sandybridge/pcie_config.c | 89 ------------------------- src/northbridge/intel/sch/pcie_config.c | 66 ------------------ src/southbridge/intel/bd82x6x/finalize.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 6 -- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/sch/smihandler.c | 7 -- 16 files changed, 99 insertions(+), 246 deletions(-) diff --git a/src/arch/x86/include/arch/pcie_config.h b/src/arch/x86/include/arch/pcie_config.h new file mode 100644 index 0000000..672457d --- /dev/null +++ b/src/arch/x86/include/arch/pcie_config.h @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7981046..3f7df82 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,7 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include <cpu/intel/model_206ax/model_206ax.h> /* Include romstage serial for SIO helper functions */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..97ef679 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include "i945.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c deleted file mode 100644 index 0310d67..0000000 --- a/src/northbridge/intel/i945/pcie_config.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i945.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..a1938b8 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" -#include "pcie_config.c" +#include <arch/pcie_config.h> static void sandybridge_setup_bars(void) { diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 0fa8d1a..bafa736 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <stdlib.h> -#include "pcie_config.c" +#include <arch/pcie_config.h> #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c deleted file mode 100644 index 0677d76..0000000 --- a/src/northbridge/intel/sandybridge/pcie_config.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "sandybridge.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c deleted file mode 100644 index ad7d746..0000000 --- a/src/northbridge/intel/sch/pcie_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..1492278 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..5d4add9 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf5..4bc5506 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5913115..be22a1b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..455f37c 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pcie_config.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890..9b0c235 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 2e29acd..1de1ec9 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pcie_config.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f..5074138 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00;

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Patch set updated for coreboot: e3654d1 Add test to match struct device with simple_device_t
by Kyösti Mälkki 21 Jun '13

21 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3474 -gerrit commit e3654d1719d1a01f6ad239b7333c02448d042594 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 17:16:56 2013 +0300 Add test to match struct device with simple_device_t Add a function to test if simple_device_t matches with a device instance of struct device, by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 13 +++++++++++++ src/include/device/device.h | 1 + src/include/device/pci.h | 1 + src/include/device/pci_def.h | 4 ++++ 4 files changed, 19 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4c5a814..8a7d080 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1054,6 +1054,19 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) } /** + * Test for match between romstage and ramstage device instance. + * + * @param dev Pointer to the device structure. + * @param sdev Simple device model identifier, created with PCI_DEV(). + * @return Non-zero if bus:dev.fn of device matches. + */ +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev) +{ + return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..1a5cfed 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,6 +10,7 @@ struct device; #ifndef __PRE_RAM__ typedef struct device * device_t; +typedef unsigned int simple_device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..249c242 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -77,6 +77,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a7321..c24c445 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -474,4 +474,8 @@ #define PCI_FUNC(devfn) ((devfn) & 0x07) #define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8) +/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ +#define PCI_DEV2DEVFN(sdev) ((sdev>>12)&0xff) +#define PCI_DEV2SEGBUS(sdev) ((sdev>>20)&0xfff) + #endif /* PCI_DEF_H */

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Patch merged into coreboot/master: cca6859 fix bootstate typo (bs_dev_eanble -> bs_dev_enable)
by gerrit＠coreboot.org 20 Jun '13

20 Jun '13

the following patch was just integrated into master: commit cca685936aeadfba65ecbeb854dbe632d6c89e95 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 20 14:08:27 2013 -0700 fix bootstate typo (bs_dev_eanble -> bs_dev_enable) Change-Id: I2e3fd58404c48e863a3a1b255337fb397086651b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3506 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3506 for details. -gerrit

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New patch to review for coreboot: c576a75 fix bootstate typo (bs_dev_eanble -> bs_dev_enable)
by David Hendricks 20 Jun '13

20 Jun '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3506 -gerrit commit c576a756430c52ab3094efed5dfed5e7368d9b8b Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 20 14:08:27 2013 -0700 fix bootstate typo (bs_dev_eanble -> bs_dev_enable) Change-Id: I2e3fd58404c48e863a3a1b255337fb397086651b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/lib/hardwaremain.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 14b3fff..56539cb 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -51,7 +51,7 @@ static boot_state_t bs_pre_device(void *arg); static boot_state_t bs_dev_init_chips(void *arg); static boot_state_t bs_dev_enumerate(void *arg); static boot_state_t bs_dev_resources(void *arg); -static boot_state_t bs_dev_eanble(void *arg); +static boot_state_t bs_dev_enable(void *arg); static boot_state_t bs_dev_init(void *arg); static boot_state_t bs_post_device(void *arg); static boot_state_t bs_os_resume_check(void *arg); @@ -110,7 +110,7 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_DEV_INIT_CHIPS, bs_dev_init_chips), BS_INIT_ENTRY(BS_DEV_ENUMERATE, bs_dev_enumerate), BS_INIT_ENTRY(BS_DEV_RESOURCES, bs_dev_resources), - BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), + BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_enable), BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), BS_INIT_ENTRY(BS_OS_RESUME_CHECK, bs_os_resume_check), @@ -154,7 +154,7 @@ static boot_state_t bs_dev_resources(void *arg) return BS_DEV_ENABLE; } -static boot_state_t bs_dev_eanble(void *arg) +static boot_state_t bs_dev_enable(void *arg) { timestamp_stash(TS_DEVICE_ENABLE); /* Now actually enable devices on the bus */

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coreboot-gerrit June 2013