coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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744 discussions

Patch set updated for coreboot: 8eec290 bd82x6x: Fix early EHCI BAR programming
by Kyösti Mälkki 18 Jun '13

18 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3471 -gerrit commit 8eec290f7beb6b0150855e8316ab5cd856ba2d4b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 12:29:23 2013 +0300 bd82x6x: Fix early EHCI BAR programming Change EHCI #2 to different BAR from EHCI #1. Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles. Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/early_usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index f4e526d..baf8c4f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -49,9 +49,9 @@ void enable_usb_bar(void) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd); - /* USB Controller 1 */ + /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd);

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Patch set updated for coreboot: 16172a5 lynxpoint: Fix early EHCI BAR programming
by Kyösti Mälkki 18 Jun '13

18 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3472 -gerrit commit 16172a53014b1566a109033b26a03cfec399bdb6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 12:30:13 2013 +0300 lynxpoint: Fix early EHCI BAR programming LynxPoint LP has only EHCI controller #1. Change EHCI #2 to different BAR from EHCI #1. Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles. Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/lynxpoint/early_usb.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index ebd5c2c..d71467e 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -34,23 +34,19 @@ * The BAR will be re-assigned during device * enumeration so these are only temporary. */ -void enable_usb_bar(void) +static void enable_usb_bar_on_device(device_t dev, u32 bar) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; u32 cmd; - - /* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + cmd = pci_read_config32(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_write_config32(dev, PCI_COMMAND, cmd); +} - /* USB Controller 1 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); +void enable_usb_bar(void) +{ + enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); +#if !CONFIG_INTEL_LYNXPOINT_LP + enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); +#endif }

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Patch set updated for coreboot: 2544f76 winbond/w83627dhg: Correct resource setting for SPI (LDN6)
by Nico Huber 18 Jun '13

18 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3391 -gerrit commit 2544f76f71f28b274768a5e385cd940230bb822b Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 15:25:26 2013 +0200 winbond/w83627dhg: Correct resource setting for SPI (LDN6) The SPI logical device on the W83627DHG uses the second i/o port register pair but not the first one. So we have to also set `io1` (the second io_info struct) and not `io0` in the pnp_info structure. Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to hang in pnp_enable_devices() until commit aeead274 which added a check for an unset mask. Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/superio/winbond/w83627dhg/superio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index bbde26a..510a6f3 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -101,8 +101,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, - /* the next line makes coreboot hang in pnp_enable_devices() */ - /* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */ + { &ops, W83627DHG_SPI, PNP_IO1, {}, { 0x7f8, 0 }, }, { &ops, W83627DHG_GPIO6, }, { &ops, W83627DHG_WDTO_PLED, }, { &ops, W83627DHG_GPIO2, },

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Patch set updated for coreboot: fe4b23b libpayload: ahci: Increase timeout for signature reading
by Nico Huber 18 Jun '13

18 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3493 -gerrit commit fe4b23b4727d41d5cacb4bb6b2af7d5ffe1cb9c2 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:42:35 2013 +0200 libpayload: ahci: Increase timeout for signature reading We can't read the drives signature before it's ready, i.e. spun up. So set the timeout to the standard 30s. Also put a notice on the console, so the user knows why the signature reading failed. Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/storage/ahci.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 2b33b59..ec4db4c 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -406,11 +406,19 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, dev->cmdtable = cmdtable; dev->rcvd_fis = rcvd_fis; - /* Wait for D2H Register FIS with device' signature. */ - int timeout = 200; /* Time out after 200 * 10ms == 2s. */ + /* + * Wait for D2H Register FIS with device' signature. + * The drive has to spin up here, so wait up to 30s. + */ + const int timeout_s = 30; /* Time out after 30s. */ + int timeout = timeout_s * 100; while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--) mdelay(10); + if (port->taskfile_data & HBA_PxTFD_BSY) + printf("ahci: Timed out after %d seconds " + "of waiting for device to spin up.\n", timeout_s); + /* Initialize device or fall through to clean up. */ switch (port->signature) { case HBA_PxSIG_ATA:

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Patch set updated for coreboot: c7e5b76 sandybridge: Store MRC cache in CBFS
by Patrick Georgi 18 Jun '13

18 Jun '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3497 -gerrit commit c7e5b76734c1ed34f2654b2504f26bae1feb8d05 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jun 18 11:34:01 2013 +0200 sandybridge: Store MRC cache in CBFS Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases). Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/intel/sandybridge/Makefile.inc | 10 ++++++++++ src/northbridge/intel/sandybridge/mrccache.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 01b328b..1428bdb 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -43,4 +43,14 @@ mrc.bin-position := 0xfffe0000 endif mrc.bin-type := 0xab +$(obj)/mrc.cache: + dd if=/dev/zero count=1 \ + bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ + tr '\000' '\377' > $@ + +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.cache +mrc.cache-file := $(obj)/mrc.cache +mrc.cache-position := 0xfff80000 +mrc.cache-type := 0xac + $(obj)/northbridge/intel/sandybridge/acpi.ramstage.o : $(obj)/build.h diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 745958a..e19d2c5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -71,8 +71,8 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = (struct mrc_data_container *) - (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); + *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + "mrc.cache", 0xac); #endif return region_size;

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New patch to review for coreboot: d53b953 sandybridge: Store MRC cache in CBFS
by Patrick Georgi 18 Jun '13

18 Jun '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3497 -gerrit commit d53b9531e507dab4004fc8c35a76182742d5f003 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jun 18 11:34:01 2013 +0200 sandybridge: Store MRC cache in CBFS Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases). Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/intel/sandybridge/Makefile.inc | 10 ++++++++++ src/northbridge/intel/sandybridge/mrccache.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 01b328b..3c5a4f0 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -43,4 +43,14 @@ mrc.bin-position := 0xfffe0000 endif mrc.bin-type := 0xab +$(obj)/mrc.cache: + dd if=/dev/zero count=1 \ + bs=$(shell echo $(CONFIG_MRC_CACHE_SIZE) | awk '{ printf "%d", $$0;}') | \ + tr '\000' '\377' > $@ + +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.cache +mrc.cache-file := $(obj)/mrc.cache +mrc.cache-position := 0xfff80000 +mrc.cache-type := 0xac + $(obj)/northbridge/intel/sandybridge/acpi.ramstage.o : $(obj)/build.h diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 745958a..e19d2c5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -71,8 +71,8 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = (struct mrc_data_container *) - (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); + *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + "mrc.cache", 0xac); #endif return region_size;

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New patch to review for coreboot: 417d43c qemu/q35: uncomment cache-as-ram Kconfig entries
by Gerd Hoffmann 18 Jun '13

18 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3496 -gerrit commit 417d43cb1fc78e26147b99d7a292017b7b72a04f Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Tue Jun 18 11:09:29 2013 +0200 qemu/q35: uncomment cache-as-ram Kconfig entries Change-Id: I8371764e3f2d16a3a776beb1c064f461b20a4262 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-q35/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 95209cb..cf13f35 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -27,13 +27,13 @@ config MAINBOARD_PART_NUMBER # int # default 6 -#config DCACHE_RAM_BASE -# hex -# default 0xd0000 +config DCACHE_RAM_BASE + hex + default 0xd0000 -#config DCACHE_RAM_SIZE -# hex -# default 0x10000 +config DCACHE_RAM_SIZE + hex + default 0x10000 endif # BOARD_EMULATION_QEMU_X86

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Patch set updated for coreboot: 2c0270e w83627hf: Fix address alignment error in superio.asl and add comments about parallel port modes.
by Anonymous Coward 18 Jun '13

18 Jun '13

Anonymous Coward (cg909(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3495 -gerrit commit 2c0270edab39f0c609a54ce97211c7371d065314 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Tue Jun 18 01:26:50 2013 +0200 w83627hf: Fix address alignment error in superio.asl and add comments about parallel port modes. The resource template for the parallel port contained 0x0FFC as maximum acceptable I/O starting address for EPP mode. EPP mode needs 8 bit alignment, and according to the data sheet 0x0FF8 is correct. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/acpi/superio.asl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 69017fe..67cf67a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -529,6 +529,7 @@ Device(SIO) { Name (_PRS, ResourceTemplate () { + /* Traditional configurations (SPP mode) */ StartDependentFn (0,1) { IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) @@ -544,6 +545,7 @@ Device(SIO) { IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Traditional configurations (EPP mode) */ StartDependentFn (0,0) { IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) @@ -554,11 +556,13 @@ Device(SIO) { IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (EPP mode) */ StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (No EPP mode) */ StartDependentFn (2,1) { IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08)

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New patch to review for coreboot: da5f76b w83627hf: Fix address alignment error in superio.asl and add comments about parallel port modes.
by Christoph Grenz 18 Jun '13

18 Jun '13

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3495 -gerrit commit da5f76b57622a8cf984e0423ac7b3ca48160e21b Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Tue Jun 18 01:26:50 2013 +0200 w83627hf: Fix address alignment error in superio.asl and add comments about parallel port modes. The resource template for the parallel port contained 0x0FFC as maximum acceptable I/O starting address for EPP mode. EPP mode needs 8 bit alignment, so 0x0FF8 is correct. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/acpi/superio.asl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 69017fe..67cf67a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -529,6 +529,7 @@ Device(SIO) { Name (_PRS, ResourceTemplate () { + /* Traditional configurations (SPP mode) */ StartDependentFn (0,1) { IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) @@ -544,6 +545,7 @@ Device(SIO) { IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Traditional configurations (EPP mode) */ StartDependentFn (0,0) { IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) @@ -554,11 +556,13 @@ Device(SIO) { IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (EPP mode) */ StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) IRQNoFlags () {3,4,5,7,9,10,11,12} } + /* Any configurable address (No EPP mode) */ StartDependentFn (2,1) { IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08)

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Patch set updated for coreboot: 2e71337 libpayload: ahci: Increase timeout for signature reading
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3493 -gerrit commit 2e71337345893e1b4214110a071f0fe9b2ffa10c Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:42:35 2013 +0200 libpayload: ahci: Increase timeout for signature reading We can't read the drives signature before it's ready, i.e. spun up. So set the timeout to the standard 30s. Also put a notice on the console, so the user knows why the signature reading failed. Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/storage/ahci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 2b33b59..f1fe729 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -406,11 +406,17 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, dev->cmdtable = cmdtable; dev->rcvd_fis = rcvd_fis; - /* Wait for D2H Register FIS with device' signature. */ - int timeout = 200; /* Time out after 200 * 10ms == 2s. */ + /* + * Wait for D2H Register FIS with device' signature. + * The drive has to spin up here, so wait up to 30s. + */ + int timeout = 3 * 1000; /* Time out after 3,000 * 10ms == 30s. */ while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--) mdelay(10); + if (port->taskfile_data & HBA_PxTFD_BSY) + printf("ahci: Timed out waiting for device to spin up.\n"); + /* Initialize device or fall through to clean up. */ switch (port->signature) { case HBA_PxSIG_ATA:

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coreboot-gerrit June 2013