coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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856 discussions

New patch to review for coreboot: 5af8794 wtm2: Set SerialIO I2C ports to 3.3V
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4164 -gerrit commit 5af8794c300cb5b559871e3d6f0ad37cc3091223 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 13:28:56 2013 -0700 wtm2: Set SerialIO I2C ports to 3.3V These are both pulled up to 3.3V in the schematic. Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50356 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/wtm2/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 3193369..2790cb9 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -52,8 +52,8 @@ chip northbridge/intel/haswell register "sata_port_map" = "0x2" register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "1" # 1.8V + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V device pci 13.0 on end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI

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New patch to review for coreboot: 03bb8cd haswell: Remove limit on package C-state
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4163 -gerrit commit 03bb8cdf8367872ac6fc60540b1868bd9067f4f7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 13:19:56 2013 -0700 haswell: Remove limit on package C-state With the XHCI controller enabled we no longer hang the system when dropping into a package C-state so remove the code that was disabling it. Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50355 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 071135c..b2e6eaf 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -426,10 +426,7 @@ static void configure_c_states(void) msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - msr.lo &= ~(0xf); // Clear deepest package c-state - /* FIXME: The deepest package c-state is set to C0/C1 to work around - * platform instability when package C3 or deeper c-states are used. */ - msr.lo |= 0; // Deepeset package c-state is C0/C1. + /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);

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New patch to review for coreboot: 050c11a haswell: Update ChromeOS ACPI GPIO package
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4162 -gerrit commit 050c11a424056497f9f1b6e6e0e93d1321feda04 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 7 11:31:33 2013 -0700 haswell: Update ChromeOS ACPI GPIO package The chromeos_acpi driver sysfs naming is not what crossystem expects if there is just one entry in the package because it does not add a ".#" suffix in that case. Specify all the expected GPIOs on wtm2 as undefined, which should be 0xFF and not 0x00 becuase 0 is a valid GPIO. Change-Id: I9b17e9bab94219695e65b17914c84acf02a0983b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50337 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/acpi/chromeos.asl | 6 +++--- src/mainboard/intel/wtm2/acpi/chromeos.asl | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl index 307e2e2..da4fb40 100644 --- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl +++ b/src/mainboard/intel/baskingridge/acpi/chromeos.asl @@ -18,7 +18,7 @@ */ Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect + Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 48, "LynxPoint" }, // developer + Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect }) diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl index c6b258b..40ffcf0 100644 --- a/src/mainboard/intel/wtm2/acpi/chromeos.asl +++ b/src/mainboard/intel/wtm2/acpi/chromeos.asl @@ -18,6 +18,7 @@ */ Name(OIPG, Package() { - // This GPIO is not available but the package cannot be empty - Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery + Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer + Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect })

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New patch to review for coreboot: 030cbed cbfstool: check potential microcode update earlier
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4161 -gerrit commit 030cbed1d37dce5f5cd352fd277caf18831a3841 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 11:14:01 2013 -0500 cbfstool: check potential microcode update earlier The update-fit command takes in a parameter for number of slots in the FIT table. It then processes the microcobe blob in cbfs adding those entries to the FIT table. However, the tracking of the number of mircocode updates was incremented before validating the update. Therefore, move the sanity checking before an increment of the number of updates. Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50319 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- util/cbfstool/fit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 12a7e3b..02cfaee 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -206,6 +206,10 @@ static int parse_microcode_blob(struct cbfs_image *image, mcu_header = rom_buffer_pointer(image, current_offset); + /* Quickly sanity check a prospective microcode update. */ + if (mcu_header->total_size < sizeof(*mcu_header)) + break; + /* FIXME: Should the checksum be validated? */ mcus[num_mcus].offset = current_offset; mcus[num_mcus].size = mcu_header->total_size; @@ -215,10 +219,6 @@ static int parse_microcode_blob(struct cbfs_image *image, num_mcus++; file_length -= mcus[num_mcus].size; - /* Can't determine any more entries. */ - if (!mcu_header->total_size) - break; - /* Reached limit of FIT entries. */ if (num_mcus == *total_mcus) break;

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New patch to review for coreboot: 7dca858 haswell: split microcode between ULT and non-ULT
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4160 -gerrit commit 7dca85891fbc07d7e386007d71868ebb142e702a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 11:05:06 2013 -0500 haswell: split microcode between ULT and non-ULT The current microcode blobs contain both ULT and non-ULT revisions. Only include one or the other based off of the CONFIG_INTEL_LYNXPOINT_LP Kconfig option. Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50318 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/microcode_blob.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index fabadee..5b4f74a 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -17,11 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_INTEL_LYNXPOINT_LP +#include "microcode-M7240650_ffff000a.h" +#include "microcode-M7240651_0000000a.h" +#else #include "microcode-M32306c1_ffff000d.h" #include "microcode-M32306c2_ffff0003.h" #include "microcode-M3240660_ffff000b.h" -#include "microcode-M7240650_ffff000a.h" -#include "microcode-M7240651_0000000a.h" +#endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

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New patch to review for coreboot: e270222 x86: call cbfstool update-fit when fit selected
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4159 -gerrit commit e270222b391f7bfc6ad208031b77c06f2b7306c4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 7 10:56:16 2013 -0500 x86: call cbfstool update-fit when fit selected In order for the FIT entries to be populated in the table the update-fit command needs to be done on the coreboot image. That way the microcode entries are added to the table properly. Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50317 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index dee56c5..3939122 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -130,6 +130,12 @@ endif ifeq ($(CONFIG_PXE_ROM),y) $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw endif +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) + @printf " UPDATE-FIT \n" + $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) +endif +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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New patch to review for coreboot: 34c5861 lynxpoint: Expose ACPI Device for LP GPIO controller
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4158 -gerrit commit 34c5861a70d3a3c71b2dd14bfd26ba15f1acc1bf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 6 14:02:27 2013 -0700 lynxpoint: Expose ACPI Device for LP GPIO controller In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 58 ++++------------------- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 50 +++++++++++++++++++ 2 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index f9bf578..7e26926 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -199,60 +199,22 @@ Device (LPCB) 0x1, 0xff) // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, - 0x1, 0x00, GPR1) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3) - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) }) Method (_CRS, 0, NotSerialized) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateByteField (^RBUF, ^GPR2._LEN, R2LN) - CreateByteField (^RBUF, ^GPR3._LEN, R3LN) - CreateByteField (^RBUF, ^GPR4._LEN, R4LN) + // LynxPoint-LP GPIO resources are defined in the + // SerialIO GPIO device and LynxPoint-H GPIO resources + // are defined here. + If (LNot (\ISLP ())) { + CreateByteField (^RBUF, ^GPR1._LEN, R1LN) + CreateWordField (^RBUF, ^GPR1._MIN, R1MN) + CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR2._MIN, R2MN) - CreateWordField (^RBUF, ^GPR3._MIN, R3MN) - CreateWordField (^RBUF, ^GPR4._MIN, R4MN) - - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - CreateWordField (^RBUF, ^GPR2._MAX, R2MX) - CreateWordField (^RBUF, ^GPR3._MAX, R3MX) - CreateWordField (^RBUF, ^GPR4._MAX, R4MX) - - // Update GPIO region for LynxPoint-LP - If (\ISLP ()) { - // LynxPoint-LP - Store (R1MN, Local0) - - // Update GPIO bank 1 - Store (Local0, R1MN) - Store (Local0, R1MX) - Store (0xff, R1LN) - - // Update GPIO bank 2 - Add (Local0, 0x100, Local0) - Store (Local0, R2MN) - Store (Local0, R2MX) - Store (0xff, R2LN) - - // Update GPIO bank 3 - Add (Local0, 0x100, Local0) - Store (Local0, R3MN) - Store (Local0, R3MN) - Store (0xff, R3LN) - - // Update GPIO bank 4 - Add (Local0, 0x100, Local0) - Store (Local0, R4MN) - Store (Local0, R4MN) - Store (0xff, R4LN) - } Else { - // LynxPoint-H // Update GPIO region length + Store (DEFAULT_GPIOBASE, R1MN) + Store (DEFAULT_GPIOBASE, R1MX) Store (DEFAULT_GPIOSIZE, R1LN) } Return (RBUF) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 6ea23c6..03f6974 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -468,3 +468,53 @@ Device (SDIO) } } } + +Device (GPIO) +{ + // GPIO Controller + Name (_HID, "INT33C7") + Name (_CID, "INT33C7") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + DWordIo (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + EntireRange, // ISARanges + 0x00000000, // AddressGranularity + 0x00000000, // AddressMinimum + 0x00000000, // AddressMaximum + 0x00000000, // AddressTranslation + 0x00000000, // RangeLength + , // ResourceSourceIndex + , // ResourceSource + BAR0) + }) + + Method (_CRS, 0, NotSerialized) + { + If (\ISLP ()) { + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + + Store (DEFAULT_GPIOSIZE, BLEN) + Store (DEFAULT_GPIOBASE, BMIN) + Store (Subtract (Add (DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE), 1), BMAX) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (\ISLP ()) { + Return (0xF) + } Else { + Return (0x0) + } + } +}

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New patch to review for coreboot: 4111e48 slippy: Update SPD
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4157 -gerrit commit 4111e488ea3f5e0c1cec01bd5231fcd493669f2a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 3 15:59:59 2013 -0700 slippy: Update SPD Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50082 --- src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex | 17 +++++++++++++++++ src/mainboard/google/slippy/Makefile.inc | 3 ++- src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex | 17 +++++++++++++++++ .../google/slippy/Micron_MT41K256M16HA.spd.hex | 17 ----------------- 4 files changed, 36 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 1b80e6b..67b82e5 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -28,7 +28,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41K256M16HA +SPD_SOURCES = Micron_4KTF25664HZ +SPD_SOURCES += Hynix_HMT425S6AFR6A SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex deleted file mode 100644 index a310e17..0000000 --- a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Micron MT41K256M16HA-125 DDR3L-1600 -92 11 0B 03 04 19 00 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 06 F2 -34 4A 54 46 32 35 36 36 20 34 48 5A 2D 31 47 36 -45 31 45 31 80 2C 00 00 00 00 00 00 00 00 01 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

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New patch to review for coreboot: d30c08f Make ssize_t an actual ssize_t
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4156 -gerrit commit d30c08f30da9fb043598ebbb8609b4a4447e0cef Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 14:02:28 2013 -0700 Make ssize_t an actual ssize_t In the process of getting rid of compiler includes during in coreboot and libpayload, we defined size_t and ssize_t ourselves, using a GCC macro for size_t: __SIZE_TYPE__. Unfortunately, there is no __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make __SIZE_TYPE__ __SSIZE_TYPE__. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b Reviewed-on: https://gerrit.chromium.org/gerrit/49947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/stddef.h | 8 +++++++- src/include/stddef.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index 91ae782..f9deaeb 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -5,7 +5,13 @@ #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) diff --git a/src/include/stddef.h b/src/include/stddef.h index 5b51c00..d0dad62 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -6,7 +6,13 @@ typedef long ptrdiff_t; #define __SIZE_TYPE__ unsigned long #endif typedef __SIZE_TYPE__ size_t; -typedef long ssize_t; +/* There is a GCC macro for a size_t type, but not + * for a ssize_t type. Below construct tricks GCC + * into making __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned typedef int wchar_t; typedef unsigned int wint_t;

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New patch to review for coreboot: df05ad5 call fill_lb_framebuffer() earlier
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4155 -gerrit commit df05ad55d799dc7dab9eb9bbdf91e5dac83b06a4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 2 18:23:24 2013 -0700 call fill_lb_framebuffer() earlier fill_lb_framebuffer() now sets the framebuffer pointer according to the EDID information, so it must be called before setting the tag and size. (credit to rminnich for this, I'm just uploading it) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I5ac783fa3a776eee504d39889284041d1dc2c92a Reviewed-on: https://gerrit.chromium.org/gerrit/50012 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/lib/coreboot_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e5729ba..a0a806d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -177,9 +177,9 @@ static void lb_framebuffer(struct lb_header *header) return; struct lb_framebuffer *framebuffer; framebuffer = (struct lb_framebuffer *)lb_new_record(header); + fill_lb_framebuffer(framebuffer); framebuffer->tag = LB_TAG_FRAMEBUFFER; framebuffer->size = sizeof(*framebuffer); - fill_lb_framebuffer(framebuffer); #endif }

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coreboot-gerrit November 2013