coreboot-gerrit November 2013

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Patch set updated for coreboot: 12f523f lynxpoint: Do not clear ACPI NVS region on resume
by Stefan Reinauer 30 Nov '13

30 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4210 -gerrit commit 12f523f839f36d70adfe989ccc24b28e4ae29811 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 29 07:49:55 2013 -0700 lynxpoint: Do not clear ACPI NVS region on resume There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff50476..cc95454 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -701,7 +701,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs) + if (acpi_slp_type != 3 && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); }

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Patch merged into coreboot/master: 2e0c3dc CBMEM console: increase temporary buffer size for non-dynamic CBMEM
by gerrit＠coreboot.org 30 Nov '13

30 Nov '13

the following patch was just integrated into master: commit 2e0c3dc80cd6235ffd8dbf489e0e07e76b9c307b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 27 22:54:11 2013 +0200 CBMEM console: increase temporary buffer size for non-dynamic CBMEM Make temporary buffer allocation equal with the allocation in CBMEM and let copy_console_buffer() handle possible truncation. When not using dynamic CBMEM the CBMEM area is initialized late in the ramstage and should be able to hold almost as many characters as the CBMEM can hold. We have seen 40000 was not always enough with logging level set to spew, new default size is 0x10000. Change-Id: If4b143fdf807e28b6766b8b99db5216b767948d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4295 for details. -gerrit

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Patch merged into coreboot/master: a44fecb cbmem console: reduce temporary buffer size for dynamic CBMEM
by gerrit＠coreboot.org 30 Nov '13

30 Nov '13

the following patch was just integrated into master: commit a44fecb246503cfe4f43c11303d16255fb3c1bbd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Sep 9 11:22:18 2013 -0700 cbmem console: reduce temporary buffer size for dynamic CBMEM When using dynamic CBMEM the CBMEM area is initialized before entering ram stage, and so we need a way smaller temporary buffer for the CBMEM console during early bits of ram stage. In practice around 256 bytes are needed, but keep the buffer at 1k so we make sure we don't run out. TEST=Boot tested on pit BRANCH=none BUG=none Change-Id: I462810b7bafbcc57f8e5f9b1d1f38cfdf85fa630 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/168575 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> [km: cherry-pick 7fd1bbc0 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4293 for details. -gerrit

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Patch merged into coreboot/master: 55e8c22 CBMEM console: Prevent buffer overrun
by gerrit＠coreboot.org 30 Nov '13

30 Nov '13

the following patch was just integrated into master: commit 55e8c2221942e150099ef61db87fca7fbeb1475b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 27 17:51:31 2013 +0200 CBMEM console: Prevent buffer overrun Make sure memcpy target and a possible message telling log was truncated stay within the allocated region for CBMEM console. This fixes observed CBMEM corruption on platforms that do not use CBMEM console during romstage. Those platforms will need an additional fix to reset cursor position to zero on s3 resume. Change-Id: I76501ca3afc716545ca76ebca1119995126a43f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4292 for details. -gerrit

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Patch merged into coreboot/master: 3238565 dmp/vortex86ex: Add timeout for keyboard system flag checking.
by gerrit＠coreboot.org 30 Nov '13

30 Nov '13

the following patch was just integrated into master: commit 323856524ea1bdb70556c501f985ce9e1f4b623d Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Abort and die after 11 tries as this means the CPU is defect. Also inform the user by printing a message. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> See http://review.coreboot.org/3988 for details. -gerrit

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New patch to review for coreboot: f96a70e Fix build with USE_OPTION_TABLE
by Kyösti Mälkki 30 Nov '13

30 Nov '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4299 -gerrit commit f96a70ee0794c017c0ee7d100b1e32530283b6a1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Nov 30 21:06:18 2013 +0200 Fix build with USE_OPTION_TABLE Parallelized build might try to build SMM before option_table.h is created. Remove related redundant explicit rules. Change-Id: Ida8b5c408af05adcf3210ce7bfc8a1e5959194c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- Makefile.inc | 1 + src/lib/Makefile.inc | 8 -------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 69ad3a1..0fb86ce 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -127,6 +127,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) bootblock-c-deps:=$$(OPTION_TABLE_H) +smm-c-deps:=$$(OPTION_TABLE_H) ####################################################################### # Add handler to compile ACPI's ASL diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b0d9366..92ec663 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -131,14 +131,6 @@ smm-y += gcc.c $(obj)/lib/version.ramstage.o : $(obj)/build.h -OPTION_TABLE_H:= -ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) -OPTION_TABLE_H:=$(obj)/option_table.h -endif - -$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H) -$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H) - ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c

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New patch to review for coreboot: 03fb4db Makefile: Drop obsolete rules
by Kyösti Mälkki 30 Nov '13

30 Nov '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4298 -gerrit commit 03fb4db8f92ac401320d5122bdce6a203244a317 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Nov 30 21:04:40 2013 +0200 Makefile: Drop obsolete rules The source files were removed with commit 3e4e3038. Change-Id: I2df9d8cce0ec1462dcba4790a6c62abade0d223c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/Makefile.inc | 2 -- src/arch/x86/boot/Makefile.inc | 1 - 2 files changed, 3 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4b1c591..dfd5164 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -192,8 +192,6 @@ romstage-y += memmove.S ramstage-y += memmove.S bootblock-y += memmove.S -$(obj)/arch/armv7/coreboot_table.ramstage.o : $(OPTION_TABLE_H) - romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 4b4a841..3e53d79 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -14,6 +14,5 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += ramstage_module_header.c -$(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) $(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h

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Patch set updated for coreboot: 3238565 dmp/vortex86ex: Add timeout for keyboard system flag checking.
by Andrew Wu 30 Nov '13

30 Nov '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3988 -gerrit commit 323856524ea1bdb70556c501f985ce9e1f4b623d Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Abort and die after 11 tries as this means the CPU is defect. Also inform the user by printing a message. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/cpu/dmp/dmp_post_code.h | 1 + src/southbridge/dmp/vortex86ex/southbridge.c | 32 ++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/src/cpu/dmp/dmp_post_code.h b/src/cpu/dmp/dmp_post_code.h index 6658ce8..f699171 100644 --- a/src/cpu/dmp/dmp_post_code.h +++ b/src/cpu/dmp/dmp_post_code.h @@ -25,6 +25,7 @@ #define POST_DMP_KBD_FW_UPLOAD 0x06 #define POST_DMP_KBD_CHK_READY 0x07 #define POST_DMP_KBD_IS_READY 0x08 +#define POST_DMP_KBD_IS_BAD 0x09 #define POST_DMP_KBD_FW_VERIFY_ERR 0x82 #define POST_DMP_ID_ERR 0x85 #define POST_DMP_DRAM_TEST_ERR 0x86 diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 61c484f..61dceea 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -25,6 +25,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> #include <string.h> +#include <delay.h> #include "arch/io.h" #include "chip.h" #include "southbridge.h" @@ -90,6 +91,9 @@ static const unsigned char irq_to_int_routing[16] = { #define LPT_PDMAS 0 #define LPT_DREQS 0 +/* keyboard controller system flag timeout : 400 ms */ +#define KBC_TIMEOUT_SYS_FLAG 400 + static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -135,15 +139,21 @@ static void upload_dmp_keyboard_firmware(struct device *dev) pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); } -static void kbc_wait_system_flag(void) +static int kbc_wait_system_flag(void) { /* wait keyboard controller ready by checking system flag * (status port bit 2). */ post_code(POST_DMP_KBD_CHK_READY); - while ((inb(0x64) & 0x4) == 0) { + u32 timeout; + for (timeout = KBC_TIMEOUT_SYS_FLAG; + timeout && ((inb(0x64) & 0x4) == 0); timeout--) + mdelay(1); + + if (!timeout) { + printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); } - post_code(POST_DMP_KBD_IS_READY); + return !!timeout; } static void pci_routing_fixup(struct device *dev) @@ -572,7 +582,21 @@ static void southbridge_init(struct device *dev) fix_cmos_rtc_time(); rtc_init(0); - kbc_wait_system_flag(); + /* Check keyboard controller ready. If timeout, reload firmware code + * and try again. + */ + u32 retries = 10; + while (!kbc_wait_system_flag()) { + if (!retries) { + post_code(POST_DMP_KBD_IS_BAD); + die("The keyboard timeout occurred too often. " + "Your CPU is probably defect. " + "Contact your dealer to replace it\n"); + } + upload_dmp_keyboard_firmware(dev); + retries--; + } + post_code(POST_DMP_KBD_IS_READY); pc_keyboard_init(0); }

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Patch merged into coreboot/master: a82f9fc ibexpeak: set HAVE_USBDEBUG_OPTIONS
by gerrit＠coreboot.org 30 Nov '13

30 Nov '13

the following patch was just integrated into master: commit a82f9fc6c7acef701cab1e39f0adde3b73f02f11 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Nov 25 23:40:01 2013 +0100 ibexpeak: set HAVE_USBDEBUG_OPTIONS Previously, I've set this config in mobo config, yet according to Kyösti Mälkki this parameter is southbridge-specific and not mobo-specific. Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4276 for details. -gerrit

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New patch to review for coreboot: 972c32d AMD IMC AGESA: Access the data in stack by correct length.
by Zheng Bao 29 Nov '13

29 Nov '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4297 -gerrit commit 972c32d9ea77447c53874ec46c0616bd0e74503a Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Nov 29 21:06:53 2013 +0800 AMD IMC AGESA: Access the data in stack by correct length. The values of AccessWidthxx are { AccessWidth8 = 1, AccessWidth16, AccessWidth32,} For the case of AccessWidth8, we only need to access the index/data once. But ReadECmsg and WriteECmsg did the loop 1 more time than they are supposed to do. So did the 16-bit and 32-bits accessing. The data in stack next to "Value" will be overwritten. That is an AGESA bug. We need to push this issue back to AMD's team to fix that. Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c | 4 ++-- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c | 4 ++-- src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c index 1a3f7dd..da85390 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c @@ -58,7 +58,7 @@ WriteECmsg ( OpFlag = OpFlag & 0x7f; if (OpFlag == 0x02) OpFlag = 0x03; - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); Address++; @@ -80,7 +80,7 @@ ReadECmsg ( OpFlag = OpFlag & 0x7f; if (OpFlag == 0x02) OpFlag = 0x03; - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); Address++; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c index a451c41..10f8dfc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c @@ -60,7 +60,7 @@ WriteECmsg ( OpFlag = 0x03; } - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); Address++; @@ -84,7 +84,7 @@ ReadECmsg ( OpFlag = 0x03; } - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); Address++; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c index 05f5727..5490cf5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c @@ -71,7 +71,7 @@ WriteECmsg ( OpFlag = 0x03; } - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); Address++; @@ -106,7 +106,7 @@ ReadECmsg ( OpFlag = 0x03; } - for (Index = 0; Index <= OpFlag; Index++) { + for (Index = 0; Index < OpFlag; Index++) { /// EC_LDN9_MAILBOX_BASE_ADDRESS LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); Address++;

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coreboot-gerrit November 2013