coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ef7a932 global: Fix usage of get_option() to make use of CB_CMOS_ codes
by Alexandru Gagniuc 29 Nov '13

29 Nov '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4266 -gerrit commit ef7a932b03668b2bbf51b3a6ada8260e1c297072 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Nov 23 19:22:53 2013 -0600 global: Fix usage of get_option() to make use of CB_CMOS_ codes Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/console.c | 6 ++++-- src/cpu/amd/model_fxx/model_fxx_init.c | 4 +--- src/ec/lenovo/h8/h8.c | 6 +++--- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/lib/uart8250.c | 3 +-- src/lib/uart8250mem.c | 3 +-- src/mainboard/ibase/mb899/mainboard.c | 12 ++++++------ src/mainboard/kontron/986lcd-m/mainboard.c | 12 ++++++------ src/mainboard/kontron/ktqm77/mainboard.c | 4 ++-- src/mainboard/lenovo/t60/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 8 ++++---- src/northbridge/amd/amdk8/misc_control.c | 4 +--- src/northbridge/intel/i945/gma.c | 2 +- src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 18 files changed, 37 insertions(+), 41 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 39a30b5..a31e293 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,6 +24,7 @@ #ifndef __PRE_RAM__ #include <string.h> +#include <types.h> /* * FIXME: get_option() needs to be abstracted better so that other non-volatile @@ -33,14 +34,15 @@ #if CONFIG_USE_OPTION_TABLE #include <pc80/mc146818rtc.h> #else -static inline int get_option(void *dest, const char *name) { return -1; } +static inline enum cb_err get_option(void *dest, const char *name) + { return CB_CMOS_OTABLE_DISABLED; } #endif /* initialize the console */ void console_init(void) { struct console_driver *driver; - if(get_option(&console_loglevel, "debug_level")) + if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; for(driver = console_drivers; driver < econsole_drivers; driver++) { diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 42c6f95..4beecab 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -245,10 +245,8 @@ static void init_ecc_memory(unsigned node_id) /* See if we scrubbing should be enabled */ enable_scrubbing = 1; - if( get_option(&enable_scrubbing, "hw_scrubber") < 0 ) - { + if (get_option(&enable_scrubbing, "hw_scrubber") != CB_SUCCESS) enable_scrubbing = CONFIG_HW_SCRUBBER; - } /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index af2aab3..0430fa9 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -152,14 +152,14 @@ static void h8_enable(device_t dev) h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); - if (!get_option(&val, "volume")) + if (get_option(&val, "volume") == CB_SUCCESS) ec_write(H8_VOLUME_CONTROL, val); - if (!get_option(&val, "bluetooth")) + if (get_option(&val, "bluetooth") == CB_SUCCESS) h8_bluetooth_enable(val); - if (!get_option(&val, "first_battery")) { + if (get_option(&val, "first_battery") == CB_SUCCESS) { tmp = ec_read(H8_CONFIG3); tmp &= ~(1 << 4); tmp |= (val & 1)<< 4; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 7bbe471..b02b52a 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -113,7 +113,7 @@ static void enable_dev(device_t dev) pmh7_backlight_enable(conf->backlight_enable); pmh7_dock_event_enable(conf->dock_event_enable); - if (!get_option(&val, "touchpad")) + if (get_option(&val, "touchpad") == CB_SUCCESS) pmh7_touchpad_enable(val); } diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 261b90f..aa18d2a 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -123,9 +123,8 @@ void uart_init(void) b_index &= 7; div = divisor[b_index]; #else - if (get_option(&b_index, "baud_rate") == 0) { + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) div = divisor[b_index]; - } #endif #endif diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 8d85855..1482142 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -118,9 +118,8 @@ u32 uart_mem_init(void) b_index &= 7; uart_baud = baud[b_index]; #else - if (get_option(&b_index, "baud_rate") == 0) { + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) uart_baud = baud[b_index]; - } #endif #endif diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index ea3b010..373edae 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -117,18 +117,18 @@ static void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") < 0) + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") < 0) + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0) + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - if (get_option(&sysfan_control, "sysfan_cruise_control") < 0) + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") < 0) + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) // sysfan_temperature = FAN_TEMPERATURE_30DEGC; // hwm_write(0x31, 0x20); // AVCC high limit diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 0bee70e..f4e1a24 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -124,18 +124,18 @@ static void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") < 0) + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") < 0) + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0) + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - if (get_option(&sysfan_control, "sysfan_cruise_control") < 0) + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") < 0) + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) // sysfan_temperature = FAN_TEMPERATURE_30DEGC; // hwm_write(0x31, 0x20); // AVCC high limit diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 3829d72..30f0468 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -163,7 +163,7 @@ static void mainboard_enable(device_t dev) verb_setup(); unsigned disable = 0; - if ((get_option(&disable, "ethernet1") == 0) && disable) { + if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); @@ -171,7 +171,7 @@ static void mainboard_enable(device_t dev) } } disable = 0; - if ((get_option(&disable, "ethernet2") == 0) && disable) { + if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2e54c7b..52f5dcf 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0x08); ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); - if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { + if (get_option(&defaults_loaded, "cmos_defaults_loaded") != CB_SUCCESS) { printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); defaults_loaded = 0; } diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 4fc6855..89309f2 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -448,11 +448,11 @@ static void set_thermal_config(void) cpu_fan_control = cpu_fan_control_defaults; case_fan_control = case_fan_control_defaults; - if( get_option(&byte, "cpu_fan_control") == -4 ) { + if (get_option(&byte, "cpu_fan_control") == CB_CMOS_CHECKSUM_INVALID) { printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__); } else { // get all the options needed - if( get_option(&byte, "cpu_fan_control") == 0 ) + if( get_option(&byte, "cpu_fan_control") == CB_SUCCESS ) cpu_fan_control.enable = byte ? 1 : 0; get_option(&cpu_fan_control.polarity, "cpu_fan_polarity"); @@ -461,7 +461,7 @@ static void set_thermal_config(void) get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min"); get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max"); - if( get_option(&byte, "chassis_fan_control") == 0) + if( get_option(&byte, "chassis_fan_control") == CB_SUCCESS) case_fan_control.enable = byte ? 1 : 0; get_option(&case_fan_control.polarity, "chassis_fan_polarity"); get_option(&case_fan_control.t_min, "chassis_t_min"); @@ -816,7 +816,7 @@ static void mainboard_init(device_t dev) dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE - if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 ) + if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS) int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; int15_func.regs.func05_TV_standard = TV_MODE_NO; install_INT15_function_extensions(&int15_func); diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 030c992..cab56c2 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -48,10 +48,8 @@ static void mcf3_read_resources(device_t dev) } iommu = 1; - if( get_option(&iommu, "iommu") < 0 ) - { + if (get_option(&iommu, "iommu") != CB_SUCCESS) iommu = CONFIG_IOMMU; - } if (iommu) { /* Add a GART aperture resource */ diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index deda2fa..433152c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -94,7 +94,7 @@ static void gma_func1_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); - if (!get_option(&val, "tft_brightness")) + if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val); else pci_write_config8(dev, 0xf4, 0xff); diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 8664483..a17aab8 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -119,7 +119,7 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x40, byte); // 1 means IDE, 0 means AHCI - if( get_option(&i, "sata_mode") < 0 ) { + if (get_option(&i, "sata_mode") != CB_SUCCESS) { // no cmos option i = CONFIG_SATA_MODE; } diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index cf4e132..de09b16 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -116,7 +116,7 @@ static void i82801dx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") < 0) + if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) pwr_on = MAINBOARD_POWER_ON; reg8 = pci_read_config8(dev, GEN_PMCON_3); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9285080..b9caac6 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -175,7 +175,7 @@ static void i82801gx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") < 0) + if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) pwr_on = MAINBOARD_POWER_ON; reg8 = pci_read_config8(dev, GEN_PMCON_3); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bea0d98..61a11b3 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -181,7 +181,7 @@ static void i82801ix_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") < 0) + if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) pwr_on = MAINBOARD_POWER_ON; reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 01d2a9c..d8251a0 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -543,7 +543,7 @@ static void vt8237_common_init(struct device *dev) } /* configure power state of the board after loss of power */ - if (get_option(&pwr_on, "power_on_after_fail") < 0) + if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) pwr_on = 1; enables = pci_read_config8(dev, 0x58); pci_write_config8(dev, 0x58, enables & ~0x02);

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Patch set updated for coreboot: 2e0c3dc CBMEM console: increase temporary buffer size for non-dynamic CBMEM
by Kyösti Mälkki 28 Nov '13

28 Nov '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4295 -gerrit commit 2e0c3dc80cd6235ffd8dbf489e0e07e76b9c307b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 27 22:54:11 2013 +0200 CBMEM console: increase temporary buffer size for non-dynamic CBMEM Make temporary buffer allocation equal with the allocation in CBMEM and let copy_console_buffer() handle possible truncation. When not using dynamic CBMEM the CBMEM area is initialized late in the ramstage and should be able to hold almost as many characters as the CBMEM can hold. We have seen 40000 was not always enough with logging level set to spew, new default size is 0x10000. Change-Id: If4b143fdf807e28b6766b8b99db5216b767948d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/cbmem_console.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index fec11f7..83d44e3 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -57,7 +57,7 @@ static struct cbmem_console car_cbmem_console CAR_CBMEM; #if CONFIG_DYNAMIC_CBMEM #define STATIC_CONSOLE_SIZE 1024 #else -#define STATIC_CONSOLE_SIZE 40000 +#define STATIC_CONSOLE_SIZE CONFIG_CONSOLE_CBMEM_BUFFER_SIZE #endif static u8 static_console[STATIC_CONSOLE_SIZE]; #endif

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Patch set updated for coreboot: 693e9f3 AMD Kabini: Add ACPI sleep/wakeup calls for southbridge
by Paul Menzel 28 Nov '13

28 Nov '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4260 -gerrit commit 693e9f317bb263ba1aa8b5c705fdd4298b9cdc1c Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Nov 21 16:11:40 2013 +0800 AMD Kabini: Add ACPI sleep/wakeup calls for southbridge The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT though it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/olivehill/acpi/sleep.asl | 6 ++++++ src/mainboard/asrock/imb-a180/acpi/sleep.asl | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index dd0d9a4..fc04ecc 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -36,6 +36,10 @@ Name(WKST,Package(){Zero, Zero}) * the ACPI driver. This method cannot modify the configuration or power * state of any device in the system. */ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + Method(_PTS, 1) { /* DBGO("\\_PTS\n") */ /* DBGO("From S0 to S") */ @@ -46,6 +50,7 @@ Method(_PTS, 1) { Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) Store(7, UPWS) + \_SB.APTS(Arg0) } /* End Method(\_PTS) */ /* @@ -84,6 +89,7 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + \_SB.AWAK(Arg0) Return(WKST) } /* End Method(\_WAK) */ diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index dd0d9a4..fc04ecc 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -36,6 +36,10 @@ Name(WKST,Package(){Zero, Zero}) * the ACPI driver. This method cannot modify the configuration or power * state of any device in the system. */ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + Method(_PTS, 1) { /* DBGO("\\_PTS\n") */ /* DBGO("From S0 to S") */ @@ -46,6 +50,7 @@ Method(_PTS, 1) { Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) Store(7, UPWS) + \_SB.APTS(Arg0) } /* End Method(\_PTS) */ /* @@ -84,6 +89,7 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + \_SB.AWAK(Arg0) Return(WKST) } /* End Method(\_WAK) */

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Patch set updated for coreboot: 07b3b68 AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'
by Zheng Bao 28 Nov '13

28 Nov '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4261 -gerrit commit 07b3b68ff7251a3f70e9a796772cf64103e1f9a0 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Nov 21 16:12:27 2013 +0800 AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard' Propagated from http://review.coreboot.org/3347 http://review.coreboot.org/3374 The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/olivehill/acpi/mainboard.asl | 7 +++++++ src/mainboard/amd/olivehill/acpi/sleep.asl | 2 ++ src/mainboard/asrock/imb-a180/acpi/mainboard.asl | 7 +++++++ src/mainboard/asrock/imb-a180/acpi/sleep.asl | 2 ++ 4 files changed, 18 insertions(+) diff --git a/src/mainboard/amd/olivehill/acpi/mainboard.asl b/src/mainboard/amd/olivehill/acpi/mainboard.asl index 5487b79..4045143 100644 --- a/src/mainboard/amd/olivehill/acpi/mainboard.asl +++ b/src/mainboard/amd/olivehill/acpi/mainboard.asl @@ -32,3 +32,10 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index fc04ecc..2fc2efe 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -89,6 +89,8 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + Store(1,USBS) + \_SB.AWAK(Arg0) Return(WKST) diff --git a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl index 5487b79..4045143 100644 --- a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl +++ b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl @@ -32,3 +32,10 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index fc04ecc..2fc2efe 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -89,6 +89,8 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + Store(1,USBS) + \_SB.AWAK(Arg0) Return(WKST)

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Patch set updated for coreboot: 1e9c4f0 AMD Kabini: Add ACPI sleep/wakeup calls for southbridge
by Zheng Bao 28 Nov '13

28 Nov '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4260 -gerrit commit 1e9c4f023ed0faab61d0abb2ee57b12c6f5f5c0a Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Nov 21 16:11:40 2013 +0800 AMD Kabini: Add ACPI sleep/wakeup calls for southbridge The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT even it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/olivehill/acpi/sleep.asl | 6 ++++++ src/mainboard/asrock/imb-a180/acpi/sleep.asl | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index dd0d9a4..fc04ecc 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -36,6 +36,10 @@ Name(WKST,Package(){Zero, Zero}) * the ACPI driver. This method cannot modify the configuration or power * state of any device in the system. */ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + Method(_PTS, 1) { /* DBGO("\\_PTS\n") */ /* DBGO("From S0 to S") */ @@ -46,6 +50,7 @@ Method(_PTS, 1) { Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) Store(7, UPWS) + \_SB.APTS(Arg0) } /* End Method(\_PTS) */ /* @@ -84,6 +89,7 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + \_SB.AWAK(Arg0) Return(WKST) } /* End Method(\_WAK) */ diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index dd0d9a4..fc04ecc 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -36,6 +36,10 @@ Name(WKST,Package(){Zero, Zero}) * the ACPI driver. This method cannot modify the configuration or power * state of any device in the system. */ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + Method(_PTS, 1) { /* DBGO("\\_PTS\n") */ /* DBGO("From S0 to S") */ @@ -46,6 +50,7 @@ Method(_PTS, 1) { Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) Store(7, UPWS) + \_SB.APTS(Arg0) } /* End Method(\_PTS) */ /* @@ -84,6 +89,7 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ + \_SB.AWAK(Arg0) Return(WKST) } /* End Method(\_WAK) */

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New patch to review for coreboot: 05ab6fa src/: Annoy all the whitespace guys
by Vladimir Serbinenko 28 Nov '13

28 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4296 -gerrit commit 05ab6fa0d68d9fd8abcbb0c71ab15eccdd4a6ae2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Nov 28 00:22:54 2013 +0100 src/: Annoy all the whitespace guys Here is a result of pretty simple script which fixes all whitespaces when tab is more appropriate. Be annoyed. Change-Id: Ib743a0a619d53b6807e7992f7423c3655dd55a80 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 16 +- src/arch/armv7/Makefile.inc | 42 +- src/arch/armv7/bootblock.inc | 2 +- src/arch/armv7/cache.c | 4 +- src/arch/armv7/coreboot_ram.ld | 16 +- src/arch/armv7/id.inc | 4 +- src/arch/armv7/include/arch/cache.h | 2 +- src/arch/armv7/include/arch/cpu.h | 6 +- src/arch/armv7/include/assembler.h | 4 +- src/arch/armv7/include/stdint.h | 44 +- src/arch/armv7/interrupts.c | 20 +- src/arch/armv7/memmove.S | 38 +- src/arch/armv7/mmu.c | 8 +- src/arch/armv7/romstage.ld | 2 +- src/arch/x86/Makefile.inc | 66 +- src/arch/x86/acpi/statdef.asl | 44 +- src/arch/x86/boot/acpi.c | 8 +- src/arch/x86/boot/acpigen.c | 98 +- src/arch/x86/boot/boot.c | 2 +- src/arch/x86/boot/mpspec.c | 64 +- src/arch/x86/boot/pirq_routing.c | 6 +- src/arch/x86/boot/smbios.c | 4 +- src/arch/x86/boot/tables.c | 12 +- src/arch/x86/coreboot_ram.ld | 16 +- src/arch/x86/include/arch/acpi.h | 32 +- src/arch/x86/include/arch/cpu.h | 34 +- src/arch/x86/include/arch/io.h | 84 +- src/arch/x86/include/arch/pci_io_cfg.h | 26 +- src/arch/x86/include/arch/smp/mpspec.h | 8 +- src/arch/x86/include/stdint.h | 44 +- src/arch/x86/lib/c_start.S | 10 +- src/arch/x86/lib/cpu.c | 40 +- src/arch/x86/lib/exception.c | 300 +- src/arch/x86/lib/id.inc | 2 +- src/arch/x86/lib/ioapic.c | 14 +- src/arch/x86/lib/pci_ops_conf1.c | 8 +- src/arch/x86/lib/pci_ops_mmconf.c | 8 +- src/arch/x86/lib/rom_media.c | 2 +- src/arch/x86/lib/thread.c | 2 +- src/arch/x86/lib/thread_switch.S | 14 +- src/console/cbmem_console.c | 2 +- src/console/console.c | 2 +- src/console/logbuf_console.c | 2 +- src/console/post.c | 2 +- src/console/qemu_debugcon_console.c | 4 +- src/console/spkmodem_console.c | 2 +- src/console/uart8250_console.c | 2 +- src/console/uart8250mem_console.c | 2 +- src/console/usbdebug_console.c | 2 +- src/cpu/Makefile.inc | 4 +- src/cpu/amd/agesa/family10/Kconfig | 10 +- src/cpu/amd/agesa/family10/model_10_init.c | 10 +- src/cpu/amd/agesa/family12/Makefile.inc | 12 +- src/cpu/amd/agesa/family12/model_12_init.c | 10 +- src/cpu/amd/agesa/family14/model_14_init.c | 10 +- src/cpu/amd/agesa/family15/Kconfig | 10 +- src/cpu/amd/agesa/family15/model_15_init.c | 24 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/agesa/s3_resume.c | 6 +- src/cpu/amd/agesa/s3_resume.h | 4 +- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 4 +- src/cpu/amd/dualcore/amd_sibling.c | 32 +- src/cpu/amd/dualcore/dualcore.c | 18 +- src/cpu/amd/dualcore/dualcore_id.c | 24 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 22 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 30 +- src/cpu/amd/geode_lx/cpureginit.c | 22 +- src/cpu/amd/model_10xxx/defaults.h | 40 +- src/cpu/amd/model_10xxx/fidvid.c | 330 +- src/cpu/amd/model_10xxx/init_cpus.c | 28 +- src/cpu/amd/model_10xxx/mc_patch_01000086.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_01000095.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_01000096.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_0100009f.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000b6.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000bf.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000c4.h | 10 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 18 +- src/cpu/amd/model_10xxx/processor_name.c | 2 +- src/cpu/amd/model_10xxx/update_microcode.c | 32 +- src/cpu/amd/model_fxx/fidvid.c | 44 +- src/cpu/amd/model_fxx/init_cpus.c | 14 +- src/cpu/amd/model_fxx/model_fxx_init.c | 20 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 54 +- src/cpu/amd/model_fxx/powernow_acpi.c | 20 +- src/cpu/amd/sc520/raminit.c | 42 +- src/cpu/amd/sc520/sc520.c | 62 +- src/cpu/amd/socket_S1G1/Kconfig | 2 +- src/cpu/dmp/vortex86ex/biosdata.inc | 20 +- src/cpu/dmp/vortex86ex/biosdata_ex.inc | 62 +- src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc | 1024 ++--- src/cpu/intel/car/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram_ht.inc | 2 +- src/cpu/intel/fit/fit.inc | 2 +- src/cpu/intel/haswell/Makefile.inc | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/haswell/cache_as_ram.inc | 28 +- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/haswell/haswell_init.c | 54 +- src/cpu/intel/haswell/microcode_blob.h | 8 +- src/cpu/intel/haswell/mp_init.c | 28 +- src/cpu/intel/haswell/romstage.c | 14 +- src/cpu/intel/haswell/smmrelocate.c | 42 +- src/cpu/intel/microcode/microcode.c | 10 +- src/cpu/intel/microcode/update-microcodes.sh | 24 +- src/cpu/intel/model_1067x/model_1067x_init.c | 14 +- src/cpu/intel/model_106cx/model_106cx_init.c | 12 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 22 +- src/cpu/intel/model_2065x/microcode_blob.h | 8 +- src/cpu/intel/model_2065x/model_2065x_init.c | 18 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 28 +- src/cpu/intel/model_206ax/microcode_blob.h | 8 +- src/cpu/intel/model_206ax/model_206ax_init.c | 18 +- src/cpu/intel/model_65x/model_65x_init.c | 4 +- src/cpu/intel/model_67x/microcode-293-MU267114.h | 2 +- src/cpu/intel/model_67x/microcode-530-MU16730e.h | 2 +- src/cpu/intel/model_67x/microcode-531-MU26732e.h | 2 +- src/cpu/intel/model_67x/microcode-539-MU167210.h | 2 +- src/cpu/intel/model_67x/microcode-540-MU267238.h | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 4 +- src/cpu/intel/model_68x/microcode-534-MU16810d.h | 2 +- src/cpu/intel/model_68x/microcode-535-MU16810e.h | 2 +- src/cpu/intel/model_68x/microcode-536-MU16810f.h | 2 +- src/cpu/intel/model_68x/microcode-537-MU268110.h | 2 +- src/cpu/intel/model_68x/microcode-538-MU168111.h | 2 +- src/cpu/intel/model_68x/microcode-550-MU168307.h | 2 +- src/cpu/intel/model_68x/microcode-551-MU168308.h | 2 +- src/cpu/intel/model_68x/microcode-611-MU168607.h | 2 +- src/cpu/intel/model_68x/microcode-612-MU168608.h | 2 +- src/cpu/intel/model_68x/microcode-615-MU16860a.h | 2 +- src/cpu/intel/model_68x/microcode-617-MU16860c.h | 2 +- src/cpu/intel/model_68x/microcode-618-MU268602.h | 2 +- src/cpu/intel/model_68x/microcode-662-MU168a01.h | 2 +- src/cpu/intel/model_68x/microcode-691-MU168a04.h | 2 +- src/cpu/intel/model_68x/microcode-692-MU168a05.h | 2 +- src/cpu/intel/model_68x/microcode-727-MU168313.h | 2 +- src/cpu/intel/model_68x/microcode-728-MU168314.h | 2 +- src/cpu/intel/model_68x/microcode-729-MU268310.h | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 12 +- src/cpu/intel/model_69x/model_69x_init.c | 12 +- src/cpu/intel/model_6bx/model_6bx_init.c | 12 +- src/cpu/intel/model_6dx/model_6dx_init.c | 12 +- src/cpu/intel/model_6ex/model_6ex_init.c | 12 +- src/cpu/intel/model_6fx/model_6fx_init.c | 14 +- src/cpu/intel/model_6xx/model_6xx_init.c | 12 +- src/cpu/intel/model_f0x/model_f0x_init.c | 12 +- src/cpu/intel/model_f1x/model_f1x_init.c | 12 +- src/cpu/intel/model_f2x/model_f2x_init.c | 12 +- src/cpu/intel/model_f3x/model_f3x_init.c | 10 +- src/cpu/intel/model_f4x/model_f4x_init.c | 10 +- src/cpu/intel/slot_1/l2_cache.c | 12 +- src/cpu/intel/socket_LGA771/Kconfig | 2 +- src/cpu/intel/speedstep/acpi.c | 20 +- src/cpu/intel/speedstep/speedstep.c | 4 +- src/cpu/qemu-x86/qemu.c | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/cpu/samsung/exynos5250/clk.h | 2 +- src/cpu/samsung/exynos5250/clock.c | 8 +- src/cpu/samsung/exynos5250/cpu.c | 12 +- src/cpu/samsung/exynos5250/cpu.h | 2 +- src/cpu/samsung/exynos5250/dmc.h | 2 +- src/cpu/samsung/exynos5250/dmc_common.c | 4 +- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 +- src/cpu/samsung/exynos5250/dp.h | 4 +- src/cpu/samsung/exynos5250/dsim.h | 4 +- src/cpu/samsung/exynos5250/fb.c | 26 +- src/cpu/samsung/exynos5250/gpio.c | 2 +- src/cpu/samsung/exynos5250/gpio.h | 8 +- src/cpu/samsung/exynos5250/power.h | 6 +- src/cpu/samsung/exynos5250/setup.h | 224 +- src/cpu/samsung/exynos5250/spi.c | 6 +- src/cpu/samsung/exynos5250/spi.h | 4 +- src/cpu/samsung/exynos5250/uart.c | 2 +- src/cpu/samsung/exynos5250/usb.h | 58 +- src/cpu/samsung/exynos5420/Makefile.inc | 2 +- src/cpu/samsung/exynos5420/clk.h | 2 +- src/cpu/samsung/exynos5420/clock.c | 8 +- src/cpu/samsung/exynos5420/cpu.c | 12 +- src/cpu/samsung/exynos5420/cpu.h | 2 +- src/cpu/samsung/exynos5420/dmc.h | 2 +- src/cpu/samsung/exynos5420/dmc_common.c | 4 +- src/cpu/samsung/exynos5420/dp.h | 4 +- src/cpu/samsung/exynos5420/dsim.h | 4 +- src/cpu/samsung/exynos5420/fb.c | 26 +- src/cpu/samsung/exynos5420/gpio.c | 2 +- src/cpu/samsung/exynos5420/gpio.h | 8 +- src/cpu/samsung/exynos5420/i2c.c | 24 +- src/cpu/samsung/exynos5420/power.h | 6 +- src/cpu/samsung/exynos5420/setup.h | 114 +- src/cpu/samsung/exynos5420/spi.c | 16 +- src/cpu/samsung/exynos5420/spi.h | 4 +- src/cpu/samsung/exynos5420/uart.c | 2 +- src/cpu/samsung/exynos5420/usb.h | 58 +- src/cpu/ti/am335x/Makefile.inc | 4 +- src/cpu/ti/am335x/bootblock_media.c | 2 +- src/cpu/ti/am335x/header.c | 4 +- src/cpu/ti/am335x/nand.c | 2 +- src/cpu/ti/am335x/uart.c | 2 +- src/cpu/via/c3/c3_init.c | 4 +- src/cpu/via/c7/c7_init.c | 16 +- src/cpu/via/car/cache_as_ram.inc | 4 +- src/cpu/via/nano/nano_init.c | 8 +- src/cpu/via/nano/update_ucode.c | 2 +- src/cpu/via/nano/update_ucode.h | 46 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/16bit/reset16.inc | 2 +- src/cpu/x86/16bit/reset16.lds | 2 +- src/cpu/x86/car.c | 6 +- src/cpu/x86/lapic/apic_timer.c | 4 +- src/cpu/x86/lapic/lapic_cpu_init.c | 4 +- src/cpu/x86/lapic/secondary.S | 4 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 62 +- src/cpu/x86/smm/Makefile.inc | 6 +- src/cpu/x86/smm/smihandler.c | 4 +- src/cpu/x86/smm/smm_module_handler.c | 2 +- src/cpu/x86/smm/smm_module_loader.c | 30 +- src/cpu/x86/smm/smm_stub.S | 2 +- src/cpu/x86/smm/smmhandler.S | 56 +- src/cpu/x86/smm/smmhandler_tseg.S | 60 +- src/cpu/x86/smm/smmrelocate.S | 8 +- src/device/agp_device.c | 12 +- src/device/azalia_device.c | 2 +- src/device/cardbus_device.c | 18 +- src/device/device.c | 156 +- src/device/device_util.c | 30 +- src/device/dram/ddr3.c | 68 +- src/device/hypertransport.c | 90 +- src/device/oprom/include/x86emu/fpu_regs.h | 44 +- src/device/oprom/include/x86emu/regs.h | 154 +- src/device/oprom/include/x86emu/types.h | 8 +- src/device/oprom/include/x86emu/x86emu.h | 58 +- src/device/oprom/realmode/x86.c | 8 +- src/device/oprom/realmode/x86_asm.S | 4 +- src/device/oprom/realmode/x86_interrupts.c | 6 +- src/device/oprom/x86emu/LICENSE | 4 +- src/device/oprom/x86emu/debug.c | 260 +- src/device/oprom/x86emu/debug.h | 112 +- src/device/oprom/x86emu/decode.c | 832 ++-- src/device/oprom/x86emu/decode.h | 46 +- src/device/oprom/x86emu/fpu.c | 1096 ++--- src/device/oprom/x86emu/fpu.h | 12 +- src/device/oprom/x86emu/ops.c | 4702 ++++++++++---------- src/device/oprom/x86emu/ops.h | 8 +- src/device/oprom/x86emu/ops2.c | 1926 ++++---- src/device/oprom/x86emu/prim_asm.h | 1246 +++--- src/device/oprom/x86emu/prim_ops.c | 1440 +++--- src/device/oprom/x86emu/prim_ops.h | 188 +- src/device/oprom/x86emu/sys.c | 18 +- src/device/oprom/x86emu/x86emui.h | 12 +- src/device/oprom/yabel/biosemu.c | 10 +- src/device/oprom/yabel/compat/functions.c | 4 +- src/device/oprom/yabel/compat/rtas.h | 14 +- src/device/oprom/yabel/device.c | 12 +- src/device/oprom/yabel/interrupt.c | 86 +- src/device/oprom/yabel/io.c | 84 +- src/device/oprom/yabel/mem.c | 32 +- src/device/oprom/yabel/pmm.c | 52 +- src/device/oprom/yabel/vbe.c | 28 +- src/device/pci_device.c | 88 +- src/device/pci_ops.c | 16 +- src/device/pci_rom.c | 36 +- src/device/pciexp_device.c | 24 +- src/device/pcix_device.c | 14 +- src/device/pnp_device.c | 10 +- src/device/root_device.c | 14 +- src/device/smbus_ops.c | 6 +- src/drivers/ati/ragexl/atyfb.h | 18 +- src/drivers/ati/ragexl/fb.h | 116 +- src/drivers/ati/ragexl/fbcon.h | 48 +- src/drivers/ati/ragexl/mach64.h | 4 +- src/drivers/ati/ragexl/mach64_ct.c | 16 +- src/drivers/ati/ragexl/xlinit.c | 882 ++-- src/drivers/dec/21143/21143.c | 12 +- src/drivers/elog/elog.c | 42 +- src/drivers/elog/elog_internal.h | 2 +- src/drivers/elog/gsmi.c | 8 +- src/drivers/emulation/qemu/bochs.c | 48 +- src/drivers/emulation/qemu/cirrus.c | 26 +- src/drivers/generic/debug/debug_dev.c | 174 +- src/drivers/generic/ioapic/ioapic.c | 16 +- src/drivers/i2c/adm1026/adm1026.c | 14 +- src/drivers/i2c/lm63/lm63.c | 2 +- src/drivers/i2c/w83795/w83795.c | 4 +- src/drivers/ics/954309/ics954309.c | 8 +- src/drivers/ipmi/ipmi_kcs.c | 4 +- src/drivers/oxford/oxpcie/oxpcie.c | 10 +- src/drivers/pc80/i8254.c | 16 +- src/drivers/pc80/i8259.c | 34 +- src/drivers/pc80/isa-dma.c | 18 +- src/drivers/pc80/keyboard.c | 6 +- src/drivers/pc80/mc146818rtc.c | 2 +- src/drivers/pc80/tpm.c | 80 +- src/drivers/pc80/vga/vga.h | 6 +- src/drivers/pc80/vga/vga_font_8x16.c | 6 +- src/drivers/pc80/vga/vga_io.c | 26 +- src/drivers/pc80/vga/vga_palette.c | 498 +-- src/drivers/sil/3114/sil_sata.c | 12 +- src/drivers/spi/eon.c | 20 +- src/drivers/spi/gigadevice.c | 22 +- src/drivers/spi/macronix.c | 2 +- src/drivers/spi/spansion.c | 2 +- src/drivers/spi/spi_flash.c | 2 +- src/drivers/spi/spi_flash_internal.h | 2 +- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 2 +- src/drivers/spi/winbond.c | 2 +- src/drivers/ti/tps65090/tps65090.c | 12 +- src/drivers/ti/tps65090/tps65090.h | 12 +- src/drivers/trident/blade3d/blade3d.c | 40 +- src/ec/acpi/ec.h | 22 +- src/ec/compal/ene932/acpi/battery.asl | 8 +- src/ec/compal/ene932/acpi/ec.asl | 438 +- src/ec/compal/ene932/ec.c | 6 +- src/ec/compal/ene932/ec.h | 10 +- src/ec/google/chromeec/Kconfig | 2 +- src/ec/google/chromeec/acpi/battery.asl | 14 +- src/ec/google/chromeec/acpi/superio.asl | 14 +- src/ec/google/chromeec/crosec_proto.c | 16 +- src/ec/google/chromeec/ec.c | 18 +- src/ec/google/chromeec/ec.h | 4 +- src/ec/google/chromeec/ec_commands.h | 182 +- src/ec/google/chromeec/ec_i2c.c | 20 +- src/ec/google/chromeec/ec_lpc.c | 6 +- src/ec/google/chromeec/ec_spi.c | 2 +- src/ec/kontron/it8516e/acpi/ec.asl | 4 +- src/ec/kontron/it8516e/ec.c | 56 +- src/ec/lenovo/h8/acpi/battery.asl | 4 +- src/ec/lenovo/h8/acpi/ec.asl | 94 +- src/ec/lenovo/h8/acpi/lid.asl | 2 +- src/ec/lenovo/h8/acpi/sleepbutton.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 12 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/quanta/ene_kb3940q/acpi/battery.asl | 10 +- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 158 +- src/ec/quanta/ene_kb3940q/ec.c | 4 +- src/ec/quanta/ene_kb3940q/ec.h | 74 +- src/ec/quanta/it8518/acpi/battery.asl | 32 +- src/ec/quanta/it8518/acpi/ec.asl | 922 ++-- src/ec/quanta/it8518/ec.c | 4 +- src/ec/quanta/it8518/ec.h | 64 +- src/ec/smsc/mec1308/acpi/battery.asl | 12 +- src/ec/smsc/mec1308/ec.c | 2 +- src/ec/smsc/mec1308/ec.h | 8 +- src/include/boot/coreboot_tables.h | 48 +- src/include/bootstate.h | 48 +- src/include/cbfs.h | 10 +- src/include/cbfs_core.h | 18 +- src/include/cbmem.h | 2 +- src/include/console/console.h | 176 +- src/include/console/loglevel.h | 18 +- src/include/cpu/amd/common/cbtypes.h | 2 +- src/include/cpu/amd/gx1def.h | 22 +- src/include/cpu/amd/model_fxx_msr.h | 2 +- src/include/cpu/amd/model_fxx_rev.h | 72 +- src/include/cpu/amd/sc520.h | 8 +- src/include/cpu/amd/vr.h | 148 +- src/include/cpu/intel/l2_cache.h | 22 +- src/include/cpu/intel/speedstep.h | 8 +- src/include/cpu/x86/bist.h | 2 +- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/msr.h | 4 +- src/include/cpu/x86/mtrr.h | 12 +- src/include/cpu/x86/multiboot.h | 14 +- src/include/cpu/x86/post_code.h | 6 +- src/include/cpu/x86/smm.h | 18 +- src/include/device/azalia.h | 130 +- src/include/device/device.h | 12 +- src/include/device/dram/ddr3.h | 44 +- src/include/device/drm_dp_helper.h | 184 +- src/include/device/hypertransport_def.h | 12 +- src/include/device/i915_reg.h | 2820 ++++++------ src/include/device/pci_def.h | 52 +- src/include/device/pci_ids.h | 346 +- src/include/device/pciexp.h | 4 +- src/include/device/pnp.h | 2 +- src/include/ehci.h | 8 +- src/include/elog.h | 148 +- src/include/memrange.h | 20 +- src/include/pc80/i8254.h | 50 +- src/include/pc80/mc146818rtc.h | 18 +- src/include/rmodule.h | 2 +- src/include/sdram_mode.h | 18 +- src/include/smbios.h | 4 +- src/include/spd.h | 184 +- src/include/stdlib.h | 8 +- src/include/string.h | 12 +- src/include/thread.h | 4 +- src/include/timer.h | 14 +- src/include/trace.h | 2 +- src/include/uart8250.h | 110 +- src/include/usb_ch9.h | 100 +- src/include/vbe.h | 8 +- src/lib/cbfs.c | 38 +- src/lib/cbfs_core.c | 32 +- src/lib/cbmem.c | 8 +- src/lib/cbmem_console.c | 2 +- src/lib/cbmem_info.c | 10 +- src/lib/clog2.c | 20 +- src/lib/coreboot_table.c | 22 +- src/lib/dynamic_cbmem.c | 12 +- src/lib/edid.c | 240 +- src/lib/gcov-io.c | 2 +- src/lib/gcov-io.h | 38 +- src/lib/generic_sdram.c | 8 +- src/lib/hardwaremain.c | 42 +- src/lib/jpeg.c | 80 +- src/lib/libgcov.c | 74 +- src/lib/lzmadecode.c | 342 +- src/lib/memrange.c | 44 +- src/lib/ne2k.c | 16 +- src/lib/ns8390.h | 2 +- src/lib/ramtest.c | 4 +- src/lib/rmodule.c | 28 +- src/lib/rmodule.ld | 2 +- src/lib/selfboot.c | 8 +- src/lib/stack.c | 2 +- src/lib/thread.c | 10 +- src/lib/timer_queue.c | 4 +- src/lib/uart8250.c | 4 +- src/lib/usbdebug.c | 10 +- src/lib/version.c | 6 +- src/lib/xmodem.c | 4 +- src/mainboard/Kconfig | 2 +- src/mainboard/a-trend/atc-6220/devicetree.cb | 66 +- src/mainboard/a-trend/atc-6220/irq_tables.c | 2 +- src/mainboard/a-trend/atc-6240/devicetree.cb | 84 +- src/mainboard/a-trend/atc-6240/irq_tables.c | 2 +- src/mainboard/aaeon/pfm-540i_revb/irq_tables.c | 4 +- src/mainboard/abit/be6-ii_v2_0/devicetree.cb | 66 +- src/mainboard/abit/be6-ii_v2_0/irq_tables.c | 2 +- src/mainboard/advansus/a785e-i/Kconfig | 4 +- src/mainboard/advansus/a785e-i/acpi/ide.asl | 8 +- src/mainboard/advansus/a785e-i/acpi_tables.c | 2 +- src/mainboard/advansus/a785e-i/cmos.layout | 160 +- src/mainboard/advansus/a785e-i/devicetree.cb | 80 +- src/mainboard/advansus/a785e-i/dsdt.asl | 128 +- src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/advansus/a785e-i/mptable.c | 8 +- src/mainboard/advansus/a785e-i/platform_cfg.h | 8 +- src/mainboard/advansus/a785e-i/resourcemap.c | 190 +- src/mainboard/advansus/a785e-i/romstage.c | 4 +- src/mainboard/advantech/pcm-5820/devicetree.cb | 76 +- src/mainboard/advantech/pcm-5820/irq_tables.c | 2 +- src/mainboard/amd/bimini_fam10/acpi/ide.asl | 8 +- src/mainboard/amd/bimini_fam10/acpi_tables.c | 2 +- src/mainboard/amd/bimini_fam10/cmos.layout | 160 +- src/mainboard/amd/bimini_fam10/devicetree.cb | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 128 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/mptable.c | 8 +- src/mainboard/amd/bimini_fam10/resourcemap.c | 190 +- src/mainboard/amd/bimini_fam10/romstage.c | 4 +- src/mainboard/amd/db800/cmos.layout | 118 +- src/mainboard/amd/db800/irq_tables.c | 6 +- src/mainboard/amd/dbm690t/acpi/ide.asl | 8 +- src/mainboard/amd/dbm690t/acpi_tables.c | 2 +- src/mainboard/amd/dbm690t/cmos.layout | 160 +- src/mainboard/amd/dbm690t/devicetree.cb | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 80 +- src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +- src/mainboard/amd/dbm690t/mainboard.c | 4 +- src/mainboard/amd/dbm690t/mptable.c | 8 +- src/mainboard/amd/dinar/BiosCallOuts.c | 72 +- src/mainboard/amd/dinar/BiosCallOuts.h | 18 +- src/mainboard/amd/dinar/OptionsIds.h | 8 +- src/mainboard/amd/dinar/acpi/ide.asl | 8 +- src/mainboard/amd/dinar/agesawrapper.c | 82 +- src/mainboard/amd/dinar/agesawrapper.h | 88 +- src/mainboard/amd/dinar/buildOpts.c | 250 +- src/mainboard/amd/dinar/cmos.layout | 160 +- src/mainboard/amd/dinar/devicetree.cb | 2 +- src/mainboard/amd/dinar/dsdt.asl | 2230 +++++----- src/mainboard/amd/dinar/fadt.c | 2 +- src/mainboard/amd/dinar/get_bus_conf.c | 2 +- src/mainboard/amd/dinar/gpio.c | 148 +- src/mainboard/amd/dinar/gpio.h | 2838 ++++++------ src/mainboard/amd/dinar/mptable.c | 4 +- src/mainboard/amd/dinar/rd890_cfg.c | 4 +- src/mainboard/amd/dinar/rd890_cfg.h | 36 +- src/mainboard/amd/dinar/sb700_cfg.c | 4 +- src/mainboard/amd/dinar/sb700_cfg.h | 64 +- src/mainboard/amd/inagua/BiosCallOuts.c | 68 +- src/mainboard/amd/inagua/BiosCallOuts.h | 18 +- src/mainboard/amd/inagua/Kconfig | 6 +- src/mainboard/amd/inagua/OptionsIds.h | 6 +- src/mainboard/amd/inagua/PlatformGnbPcie.c | 6 +- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 50 +- src/mainboard/amd/inagua/acpi/ide.asl | 8 +- src/mainboard/amd/inagua/agesawrapper.c | 4 +- src/mainboard/amd/inagua/agesawrapper.h | 26 +- src/mainboard/amd/inagua/broadcom.c | 22 +- src/mainboard/amd/inagua/buildOpts.c | 78 +- src/mainboard/amd/inagua/cmos.layout | 160 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/inagua/get_bus_conf.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 6 +- src/mainboard/amd/inagua/platform_cfg.h | 8 +- src/mainboard/amd/mahogany/acpi/ide.asl | 8 +- src/mainboard/amd/mahogany/acpi_tables.c | 2 +- src/mainboard/amd/mahogany/cmos.layout | 160 +- src/mainboard/amd/mahogany/devicetree.cb | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 84 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 2 +- src/mainboard/amd/mahogany/mptable.c | 8 +- src/mainboard/amd/mahogany_fam10/acpi/ide.asl | 8 +- src/mainboard/amd/mahogany_fam10/cmos.layout | 160 +- src/mainboard/amd/mahogany_fam10/devicetree.cb | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 84 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 2 +- src/mainboard/amd/mahogany_fam10/mptable.c | 8 +- src/mainboard/amd/mahogany_fam10/resourcemap.c | 190 +- src/mainboard/amd/mahogany_fam10/romstage.c | 4 +- src/mainboard/amd/norwich/cmos.layout | 120 +- src/mainboard/amd/norwich/irq_tables.c | 6 +- src/mainboard/amd/olivehill/BiosCallOuts.c | 28 +- src/mainboard/amd/olivehill/OptionsIds.h | 8 +- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 6 +- src/mainboard/amd/olivehill/acpi/ide.asl | 74 +- src/mainboard/amd/olivehill/acpi_tables.c | 4 +- src/mainboard/amd/olivehill/agesawrapper.c | 154 +- src/mainboard/amd/olivehill/agesawrapper.h | 28 +- src/mainboard/amd/olivehill/buildOpts.c | 460 +- src/mainboard/amd/olivehill/cmos.layout | 160 +- src/mainboard/amd/olivehill/devicetree.cb | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/olivehill/get_bus_conf.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 16 +- src/mainboard/amd/parmer/BiosCallOuts.c | 18 +- src/mainboard/amd/parmer/OptionsIds.h | 8 +- src/mainboard/amd/parmer/PlatformGnbPcie.c | 14 +- src/mainboard/amd/parmer/acpi/mainboard.asl | 2 +- src/mainboard/amd/parmer/acpi/routing.asl | 4 +- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 154 +- src/mainboard/amd/parmer/agesawrapper.h | 28 +- src/mainboard/amd/parmer/buildOpts.c | 466 +- src/mainboard/amd/parmer/cmos.layout | 160 +- src/mainboard/amd/parmer/devicetree.cb | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/parmer/get_bus_conf.c | 2 +- src/mainboard/amd/parmer/mptable.c | 16 +- src/mainboard/amd/persimmon/BiosCallOuts.c | 28 +- src/mainboard/amd/persimmon/OptionsIds.h | 6 +- src/mainboard/amd/persimmon/acpi/ide.asl | 8 +- src/mainboard/amd/persimmon/agesawrapper.c | 40 +- src/mainboard/amd/persimmon/cmos.layout | 160 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/persimmon/get_bus_conf.c | 2 +- src/mainboard/amd/persimmon/platform_cfg.h | 24 +- src/mainboard/amd/pistachio/acpi/ide.asl | 8 +- src/mainboard/amd/pistachio/acpi_tables.c | 2 +- src/mainboard/amd/pistachio/cmos.layout | 160 +- src/mainboard/amd/pistachio/devicetree.cb | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 76 +- src/mainboard/amd/pistachio/get_bus_conf.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 26 +- src/mainboard/amd/pistachio/mptable.c | 8 +- src/mainboard/amd/pistachio/resourcemap.c | 190 +- src/mainboard/amd/rumba/cmos.layout | 118 +- src/mainboard/amd/rumba/devicetree.cb | 10 +- src/mainboard/amd/rumba/irq_tables.c | 10 +- src/mainboard/amd/rumba/mainboard.c | 4 +- .../amd/serengeti_cheetah/acpi/amd8111.asl | 276 +- .../amd/serengeti_cheetah/acpi/amd8111_isa.asl | 332 +- .../amd/serengeti_cheetah/acpi/amd8111_pic.asl | 706 +-- .../amd/serengeti_cheetah/acpi/amd8131.asl | 192 +- .../amd/serengeti_cheetah/acpi/amd8131_2.asl | 206 +- .../amd/serengeti_cheetah/acpi/amd8132_2.asl | 206 +- .../amd/serengeti_cheetah/acpi/amd8151.asl | 52 +- src/mainboard/amd/serengeti_cheetah/cmos.layout | 160 +- src/mainboard/amd/serengeti_cheetah/devicetree.cb | 194 +- src/mainboard/amd/serengeti_cheetah/dsdt.asl | 230 +- src/mainboard/amd/serengeti_cheetah/fadt.c | 6 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 56 +- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 96 +- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 18 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 180 +- src/mainboard/amd/serengeti_cheetah/resourcemap.c | 190 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 142 +- src/mainboard/amd/serengeti_cheetah/ssdt2.asl | 40 +- src/mainboard/amd/serengeti_cheetah/ssdt3.asl | 40 +- src/mainboard/amd/serengeti_cheetah/ssdt4.asl | 40 +- .../serengeti_cheetah_fam10/acpi/amd8111_isa.asl | 4 +- .../amd/serengeti_cheetah_fam10/cmos.layout | 160 +- src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 6 +- .../amd/serengeti_cheetah_fam10/resourcemap.c | 190 +- .../amd/serengeti_cheetah_fam10/romstage.c | 4 +- src/mainboard/amd/south_station/BiosCallOuts.c | 172 +- src/mainboard/amd/south_station/BiosCallOuts.h | 18 +- src/mainboard/amd/south_station/OptionsIds.h | 6 +- src/mainboard/amd/south_station/PlatformGnbPcie.c | 124 +- .../amd/south_station/PlatformGnbPcieComplex.h | 60 +- src/mainboard/amd/south_station/acpi/ide.asl | 8 +- src/mainboard/amd/south_station/agesawrapper.c | 6 +- src/mainboard/amd/south_station/agesawrapper.h | 26 +- src/mainboard/amd/south_station/buildOpts.c | 394 +- src/mainboard/amd/south_station/cmos.layout | 160 +- src/mainboard/amd/south_station/devicetree.cb | 106 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/south_station/get_bus_conf.c | 2 +- src/mainboard/amd/south_station/mptable.c | 8 +- src/mainboard/amd/south_station/platform_cfg.h | 8 +- src/mainboard/amd/thatcher/BiosCallOuts.c | 18 +- src/mainboard/amd/thatcher/OptionsIds.h | 8 +- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 40 +- src/mainboard/amd/thatcher/acpi/mainboard.asl | 2 +- src/mainboard/amd/thatcher/acpi/routing.asl | 4 +- src/mainboard/amd/thatcher/acpi_tables.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 154 +- src/mainboard/amd/thatcher/agesawrapper.h | 28 +- src/mainboard/amd/thatcher/buildOpts.c | 468 +- src/mainboard/amd/thatcher/cmos.layout | 160 +- src/mainboard/amd/thatcher/devicetree.cb | 4 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/thatcher/get_bus_conf.c | 2 +- src/mainboard/amd/thatcher/mptable.c | 16 +- src/mainboard/amd/tilapia_fam10/Kconfig | 10 +- src/mainboard/amd/tilapia_fam10/acpi/ide.asl | 8 +- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 2 +- src/mainboard/amd/tilapia_fam10/cmos.layout | 160 +- src/mainboard/amd/tilapia_fam10/devicetree.cb | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 84 +- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 8 +- src/mainboard/amd/tilapia_fam10/mptable.c | 8 +- src/mainboard/amd/tilapia_fam10/resourcemap.c | 190 +- src/mainboard/amd/tilapia_fam10/romstage.c | 4 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 148 +- src/mainboard/amd/torpedo/BiosCallOuts.h | 8 +- src/mainboard/amd/torpedo/Kconfig | 84 +- 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src/mainboard/aopen/dxplplusu/fadt.c | 12 +- src/mainboard/aopen/dxplplusu/irq_tables.c | 20 +- src/mainboard/arima/hdama/cmos.layout | 160 +- src/mainboard/arima/hdama/irq_tables.c | 6 +- src/mainboard/arima/hdama/mptable.c | 2 +- src/mainboard/arima/hdama/romstage.c | 4 +- src/mainboard/artecgroup/dbe61/cmos.layout | 118 +- src/mainboard/artecgroup/dbe61/irq_tables.c | 6 +- src/mainboard/artecgroup/dbe61/mainboard.c | 4 +- src/mainboard/artecgroup/dbe61/spd_table.h | 34 +- src/mainboard/asi/mb_5blgp/devicetree.cb | 72 +- src/mainboard/asi/mb_5blgp/irq_tables.c | 2 +- src/mainboard/asi/mb_5blmp/devicetree.cb | 56 +- src/mainboard/asi/mb_5blmp/irq_tables.c | 10 +- src/mainboard/asrock/939a785gmh/acpi_tables.c | 2 +- src/mainboard/asrock/939a785gmh/cmos.layout | 160 +- src/mainboard/asrock/939a785gmh/devicetree.cb | 2 +- src/mainboard/asrock/939a785gmh/dsdt.asl | 34 +- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +- src/mainboard/asrock/939a785gmh/mainboard.c | 2 +- src/mainboard/asrock/939a785gmh/mptable.c | 6 +- src/mainboard/asrock/e350m1/BiosCallOuts.c | 108 +- src/mainboard/asrock/e350m1/BiosCallOuts.h | 2 +- src/mainboard/asrock/e350m1/Kconfig | 72 +- src/mainboard/asrock/e350m1/OptionsIds.h | 8 +- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 128 +- .../asrock/e350m1/PlatformGnbPcieComplex.h | 60 +- src/mainboard/asrock/e350m1/acpi/ide.asl | 8 +- src/mainboard/asrock/e350m1/acpi/smbus.asl | 24 +- src/mainboard/asrock/e350m1/agesawrapper.c | 6 +- src/mainboard/asrock/e350m1/agesawrapper.h | 26 +- src/mainboard/asrock/e350m1/buildOpts.c | 362 +- src/mainboard/asrock/e350m1/cmos.layout | 160 +- src/mainboard/asrock/e350m1/devicetree.cb | 96 +- src/mainboard/asrock/e350m1/get_bus_conf.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 8 +- src/mainboard/asrock/e350m1/platform_cfg.h | 8 +- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 38 +- src/mainboard/asrock/imb-a180/OptionsIds.h | 8 +- src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 6 +- src/mainboard/asrock/imb-a180/acpi/ide.asl | 74 +- src/mainboard/asrock/imb-a180/acpi_tables.c | 4 +- src/mainboard/asrock/imb-a180/agesawrapper.c | 154 +- src/mainboard/asrock/imb-a180/agesawrapper.h | 28 +- src/mainboard/asrock/imb-a180/buildOpts.c | 460 +- src/mainboard/asrock/imb-a180/cmos.layout | 160 +- src/mainboard/asrock/imb-a180/devicetree.cb | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/get_bus_conf.c | 2 +- src/mainboard/asrock/imb-a180/mptable.c | 16 +- src/mainboard/asus/a8n_e/cmos.layout | 44 +- src/mainboard/asus/a8n_e/devicetree.cb | 202 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 4 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8v-e_deluxe/cmos.layout | 160 +- src/mainboard/asus/a8v-e_deluxe/devicetree.cb | 160 +- src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 2 +- src/mainboard/asus/a8v-e_deluxe/mptable.c | 2 +- src/mainboard/asus/a8v-e_se/cmos.layout | 160 +- src/mainboard/asus/a8v-e_se/devicetree.cb | 160 +- src/mainboard/asus/a8v-e_se/dsdt.asl | 20 +- src/mainboard/asus/a8v-e_se/mptable.c | 2 +- src/mainboard/asus/dsbf/cmos.layout | 154 +- src/mainboard/asus/dsbf/devicetree.cb | 28 +- src/mainboard/asus/dsbf/irq_tables.c | 4 +- src/mainboard/asus/dsbf/romstage.c | 28 +- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 18 +- src/mainboard/asus/f2a85-m/OptionsIds.h | 10 +- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 40 +- src/mainboard/asus/f2a85-m/acpi/mainboard.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/routing.asl | 4 +- src/mainboard/asus/f2a85-m/acpi_tables.c | 2 +- src/mainboard/asus/f2a85-m/agesawrapper.c | 154 +- src/mainboard/asus/f2a85-m/agesawrapper.h | 28 +- src/mainboard/asus/f2a85-m/buildOpts.c | 470 +- src/mainboard/asus/f2a85-m/cmos.layout | 160 +- src/mainboard/asus/f2a85-m/devicetree.cb | 4 +- src/mainboard/asus/f2a85-m/dsdt.asl | 10 +- src/mainboard/asus/f2a85-m/get_bus_conf.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 16 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/cmos.layout | 160 +- src/mainboard/asus/k8v-x/devicetree.cb | 162 +- src/mainboard/asus/k8v-x/dsdt.asl | 20 +- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/m2n-e/cmos.layout | 160 +- src/mainboard/asus/m2n-e/devicetree.cb | 164 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 32 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2n-e/resourcemap.c | 190 +- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 10 +- src/mainboard/asus/m2v-mx_se/cmos.layout | 162 +- src/mainboard/asus/m2v-mx_se/devicetree.cb | 116 +- src/mainboard/asus/m2v-mx_se/dsdt.asl | 20 +- src/mainboard/asus/m2v/cmos.layout | 160 +- src/mainboard/asus/m2v/devicetree.cb | 116 +- src/mainboard/asus/m2v/dsdt.asl | 40 +- src/mainboard/asus/m2v/irq_tables.c | 16 +- src/mainboard/asus/m2v/mptable.c | 2 +- src/mainboard/asus/m2v/romstage.c | 12 +- src/mainboard/asus/m4a78-em/acpi/ide.asl | 8 +- src/mainboard/asus/m4a78-em/acpi_tables.c | 2 +- src/mainboard/asus/m4a78-em/cmos.layout | 160 +- src/mainboard/asus/m4a78-em/devicetree.cb | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 84 +- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/irq_tables.c | 4 +- src/mainboard/asus/m4a78-em/mptable.c | 8 +- src/mainboard/asus/m4a78-em/resourcemap.c | 190 +- src/mainboard/asus/m4a78-em/romstage.c | 4 +- src/mainboard/asus/m4a785-m/acpi/ide.asl | 8 +- src/mainboard/asus/m4a785-m/acpi_tables.c | 2 +- src/mainboard/asus/m4a785-m/cmos.layout | 160 +- src/mainboard/asus/m4a785-m/devicetree.cb | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 84 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/irq_tables.c | 4 +- src/mainboard/asus/m4a785-m/mainboard.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 8 +- src/mainboard/asus/m4a785-m/resourcemap.c | 190 +- src/mainboard/asus/m4a785-m/romstage.c | 6 +- src/mainboard/asus/m4a785t-m/acpi/ide.asl | 8 +- src/mainboard/asus/m4a785t-m/cmos.layout | 160 +- src/mainboard/asus/m4a785t-m/devicetree.cb | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 84 +- src/mainboard/asus/m5a88-v/Kconfig | 4 +- src/mainboard/asus/m5a88-v/acpi/ide.asl | 8 +- src/mainboard/asus/m5a88-v/acpi_tables.c | 2 +- src/mainboard/asus/m5a88-v/cmos.layout | 160 +- src/mainboard/asus/m5a88-v/devicetree.cb | 80 +- src/mainboard/asus/m5a88-v/dsdt.asl | 128 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/mptable.c | 8 +- src/mainboard/asus/m5a88-v/platform_cfg.h | 8 +- src/mainboard/asus/m5a88-v/resourcemap.c | 190 +- src/mainboard/asus/m5a88-v/romstage.c | 4 +- src/mainboard/asus/mew-am/devicetree.cb | 72 +- src/mainboard/asus/mew-am/irq_tables.c | 2 +- src/mainboard/asus/mew-vm/cmos.layout | 118 +- src/mainboard/asus/mew-vm/irq_tables.c | 6 +- src/mainboard/asus/p2b-d/devicetree.cb | 66 +- src/mainboard/asus/p2b-d/irq_tables.c | 2 +- src/mainboard/asus/p2b-d/mptable.c | 6 +- src/mainboard/asus/p2b-ds/devicetree.cb | 66 +- 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src/mainboard/broadcom/blast/mptable.c | 98 +- src/mainboard/broadcom/blast/resourcemap.c | 190 +- src/mainboard/broadcom/blast/romstage.c | 68 +- .../compaq/deskpro_en_sff_p600/devicetree.cb | 72 +- .../compaq/deskpro_en_sff_p600/irq_tables.c | 2 +- src/mainboard/digitallogic/adl855pc/cmos.layout | 118 +- src/mainboard/digitallogic/adl855pc/devicetree.cb | 48 +- src/mainboard/digitallogic/adl855pc/irq_tables.c | 20 +- src/mainboard/digitallogic/adl855pc/romstage.c | 6 +- src/mainboard/digitallogic/msm586seg/cmos.layout | 118 +- src/mainboard/digitallogic/msm586seg/irq_tables.c | 10 +- src/mainboard/digitallogic/msm586seg/mainboard.c | 2 +- src/mainboard/digitallogic/msm586seg/romstage.c | 48 +- src/mainboard/digitallogic/msm800sev/cmos.layout | 118 +- src/mainboard/digitallogic/msm800sev/devicetree.cb | 6 +- src/mainboard/digitallogic/msm800sev/irq_tables.c | 6 +- src/mainboard/digitallogic/msm800sev/mainboard.c | 4 +- src/mainboard/dmp/vortex86ex/Kconfig | 2 +- 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src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h | 80 +- src/mainboard/emulation/qemu-i440fx/irq_tables.c | 10 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 6 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 20 +- src/mainboard/emulation/qemu-q35/acpi_tables.c | 4 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 670 +-- src/mainboard/emulation/qemu-q35/mainboard.c | 8 +- src/mainboard/getac/p470/acpi/platform.asl | 14 +- src/mainboard/getac/p470/cmos.layout | 166 +- src/mainboard/getac/p470/devicetree.cb | 82 +- src/mainboard/getac/p470/ec_oem.h | 22 +- src/mainboard/getac/p470/irq_tables.c | 6 +- src/mainboard/getac/p470/mptable.c | 8 +- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/getac/p470/smihandler.c | 4 +- src/mainboard/gigabyte/ga-6bxc/devicetree.cb | 62 +- src/mainboard/gigabyte/ga-6bxc/irq_tables.c | 2 +- src/mainboard/gigabyte/ga-6bxe/devicetree.cb | 62 +- src/mainboard/gigabyte/ga-6bxe/irq_tables.c | 4 +- src/mainboard/gigabyte/ga_2761gxdk/cmos.layout | 160 +- src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 124 +- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 32 +- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 100 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 56 +- src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 190 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 140 +- src/mainboard/gigabyte/m57sli/cmos.layout | 160 +- src/mainboard/gigabyte/m57sli/devicetree.cb | 268 +- src/mainboard/gigabyte/m57sli/dsdt.asl | 20 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 32 +- src/mainboard/gigabyte/m57sli/irq_tables.c | 50 +- src/mainboard/gigabyte/m57sli/mptable.c | 56 +- src/mainboard/gigabyte/m57sli/resourcemap.c | 190 +- src/mainboard/gigabyte/m57sli/romstage.c | 132 +- src/mainboard/gigabyte/ma785gm/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma785gm/cmos.layout | 160 +- src/mainboard/gigabyte/ma785gm/devicetree.cb | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 84 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 2 +- src/mainboard/gigabyte/ma785gm/mptable.c | 8 +- src/mainboard/gigabyte/ma785gm/resourcemap.c | 190 +- src/mainboard/gigabyte/ma785gm/romstage.c | 4 +- src/mainboard/gigabyte/ma785gmt/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma785gmt/cmos.layout | 160 +- src/mainboard/gigabyte/ma785gmt/devicetree.cb | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 84 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 6 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 8 +- src/mainboard/gigabyte/ma785gmt/resourcemap.c | 190 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 4 +- src/mainboard/gigabyte/ma78gm/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma78gm/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma78gm/cmos.layout | 160 +- src/mainboard/gigabyte/ma78gm/devicetree.cb | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 84 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma78gm/mptable.c | 8 +- src/mainboard/gigabyte/ma78gm/resourcemap.c | 190 +- src/mainboard/gigabyte/ma78gm/romstage.c | 4 +- src/mainboard/google/butterfly/acpi/chromeos.asl | 2 +- .../google/butterfly/acpi/sandybridge_pci_irqs.asl | 2 +- src/mainboard/google/butterfly/acpi/superio.asl | 2 +- src/mainboard/google/butterfly/acpi_tables.c | 2 +- src/mainboard/google/butterfly/cmos.layout | 152 +- src/mainboard/google/butterfly/dsdt.asl | 2 +- src/mainboard/google/butterfly/ec.c | 6 +- src/mainboard/google/butterfly/ec.h | 2 +- src/mainboard/google/butterfly/hda_verb.h | 22 +- src/mainboard/google/butterfly/mainboard.c | 20 +- src/mainboard/google/butterfly/onboard.h | 6 +- src/mainboard/google/butterfly/romstage.c | 14 +- .../google/falco/acpi/haswell_pci_irqs.asl | 8 +- src/mainboard/google/falco/acpi/superio.asl | 8 +- src/mainboard/google/falco/acpi_tables.c | 2 +- src/mainboard/google/falco/cmos.layout | 150 +- src/mainboard/google/falco/ec.c | 4 +- src/mainboard/google/falco/ec.h | 14 +- src/mainboard/google/falco/gpio.h | 186 +- src/mainboard/google/falco/mainboard.c | 8 +- src/mainboard/google/falco/romstage.c | 24 +- src/mainboard/google/link/acpi/superio.asl | 8 +- src/mainboard/google/link/acpi_tables.c | 2 +- src/mainboard/google/link/cmos.layout | 150 +- src/mainboard/google/link/drm_dp_helper.h | 184 +- src/mainboard/google/link/ec.c | 4 +- src/mainboard/google/link/ec.h | 12 +- src/mainboard/google/link/fadt.c | 10 +- src/mainboard/google/link/gpio.h | 6 +- src/mainboard/google/link/i915_reg.h | 2820 ++++++------ src/mainboard/google/link/intel_dp.c | 4 +- src/mainboard/google/link/mainboard.c | 6 +- src/mainboard/google/link/romstage.c | 28 +- src/mainboard/google/parrot/acpi/chromeos.asl | 2 +- src/mainboard/google/parrot/acpi/superio.asl | 2 +- src/mainboard/google/parrot/acpi_tables.c | 2 +- src/mainboard/google/parrot/cmos.layout | 150 +- src/mainboard/google/parrot/ec.h | 4 +- src/mainboard/google/parrot/gpio.h | 6 +- src/mainboard/google/parrot/mainboard.c | 6 +- src/mainboard/google/parrot/onboard.h | 6 +- src/mainboard/google/parrot/romstage.c | 10 +- src/mainboard/google/parrot/smihandler.c | 2 +- .../google/peppy/acpi/haswell_pci_irqs.asl | 8 +- src/mainboard/google/peppy/acpi/superio.asl | 8 +- src/mainboard/google/peppy/acpi_tables.c | 2 +- src/mainboard/google/peppy/cmos.layout | 150 +- src/mainboard/google/peppy/ec.c | 4 +- src/mainboard/google/peppy/ec.h | 14 +- src/mainboard/google/peppy/gpio.h | 190 +- src/mainboard/google/peppy/mainboard.c | 8 +- src/mainboard/google/peppy/romstage.c | 32 +- src/mainboard/google/pit/mainboard.c | 2 +- src/mainboard/google/pit/romstage.c | 20 +- .../google/slippy/acpi/haswell_pci_irqs.asl | 8 +- src/mainboard/google/slippy/acpi/superio.asl | 8 +- src/mainboard/google/slippy/acpi_tables.c | 2 +- src/mainboard/google/slippy/cmos.layout | 150 +- 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src/mainboard/google/stout/thermal.h | 6 +- src/mainboard/hp/dl145_g1/cmos.layout | 160 +- src/mainboard/hp/dl145_g1/devicetree.cb | 6 +- src/mainboard/hp/dl145_g1/resourcemap.c | 4 +- src/mainboard/hp/dl145_g3/cmos.layout | 160 +- src/mainboard/hp/dl145_g3/devicetree.cb | 6 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/irq_tables.c | 72 +- src/mainboard/hp/dl145_g3/mptable.c | 4 +- src/mainboard/hp/dl165_g6_fam10/Kconfig | 2 +- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 4 +- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 160 +- src/mainboard/hp/dl165_g6_fam10/devicetree.cb | 6 +- src/mainboard/hp/dl165_g6_fam10/irq_tables.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 8 +- src/mainboard/hp/e_vectra_p2706t/devicetree.cb | 66 +- src/mainboard/hp/e_vectra_p2706t/irq_tables.c | 2 +- src/mainboard/ibase/mb899/cmos.layout | 232 +- src/mainboard/ibase/mb899/devicetree.cb | 76 +- src/mainboard/ibase/mb899/irq_tables.c | 6 +- src/mainboard/ibase/mb899/mptable.c | 10 +- src/mainboard/ibm/e325/cmos.layout | 160 +- src/mainboard/ibm/e325/devicetree.cb | 2 +- src/mainboard/ibm/e325/irq_tables.c | 4 +- src/mainboard/ibm/e325/mptable.c | 36 +- src/mainboard/ibm/e325/resourcemap.c | 12 +- src/mainboard/ibm/e325/romstage.c | 20 +- src/mainboard/ibm/e326/cmos.layout | 160 +- src/mainboard/ibm/e326/devicetree.cb | 4 +- src/mainboard/ibm/e326/irq_tables.c | 4 +- src/mainboard/ibm/e326/mptable.c | 36 +- src/mainboard/ibm/e326/resourcemap.c | 12 +- src/mainboard/ibm/e326/romstage.c | 20 +- src/mainboard/iei/juki-511p/cmos.layout | 118 +- src/mainboard/iei/juki-511p/devicetree.cb | 76 +- src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl | 8 +- src/mainboard/iei/kino-780am2-fam10/cmos.layout | 160 +- src/mainboard/iei/kino-780am2-fam10/devicetree.cb | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 84 +- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 8 +- src/mainboard/iei/kino-780am2-fam10/resourcemap.c | 190 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 4 +- src/mainboard/iei/nova4899r/cmos.layout | 118 +- src/mainboard/iei/nova4899r/devicetree.cb | 100 +- src/mainboard/iei/nova4899r/irq_tables.c | 12 +- src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c | 2 +- src/mainboard/iei/pm-lx-800-r11/devicetree.cb | 6 +- src/mainboard/intel/baskingridge/acpi/superio.asl | 20 +- src/mainboard/intel/baskingridge/acpi_tables.c | 2 +- src/mainboard/intel/baskingridge/cmos.layout | 146 +- src/mainboard/intel/baskingridge/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/gpio.h | 6 +- src/mainboard/intel/baskingridge/mainboard.c | 8 +- src/mainboard/intel/baskingridge/onboard.h | 16 +- src/mainboard/intel/baskingridge/romstage.c | 14 +- src/mainboard/intel/d810e2cb/devicetree.cb | 84 +- src/mainboard/intel/d810e2cb/gpio.c | 2 +- src/mainboard/intel/d810e2cb/irq_tables.c | 4 +- src/mainboard/intel/d945gclf/cmos.layout | 156 +- src/mainboard/intel/d945gclf/devicetree.cb | 78 +- src/mainboard/intel/d945gclf/irq_tables.c | 6 +- src/mainboard/intel/d945gclf/mptable.c | 8 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/eagleheights/cmos.layout | 140 +- src/mainboard/intel/eagleheights/debug.c | 182 +- src/mainboard/intel/eagleheights/devicetree.cb | 78 +- src/mainboard/intel/eagleheights/dsdt.asl | 68 +- src/mainboard/intel/eagleheights/fadt.c | 32 +- src/mainboard/intel/eagleheights/irq_tables.c | 4 +- src/mainboard/intel/eagleheights/mptable.c | 8 +- src/mainboard/intel/eagleheights/romstage.c | 8 +- src/mainboard/intel/emeraldlake2/acpi/superio.asl | 20 +- src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 +- src/mainboard/intel/emeraldlake2/cmos.layout | 150 +- src/mainboard/intel/emeraldlake2/ec.h | 36 +- src/mainboard/intel/emeraldlake2/gpio.h | 62 +- src/mainboard/intel/emeraldlake2/mainboard.c | 4 +- src/mainboard/intel/emeraldlake2/onboard.h | 16 +- src/mainboard/intel/emeraldlake2/romstage.c | 20 +- src/mainboard/intel/jarrell/cmos.layout | 128 +- src/mainboard/intel/jarrell/debug.c | 186 +- src/mainboard/intel/jarrell/irq_tables.c | 8 +- src/mainboard/intel/jarrell/jarrell_fixups.c | 36 +- src/mainboard/intel/jarrell/mptable.c | 12 +- src/mainboard/intel/jarrell/romstage.c | 18 +- src/mainboard/intel/mtarvon/devicetree.cb | 84 +- src/mainboard/intel/mtarvon/irq_tables.c | 6 +- src/mainboard/intel/truxton/devicetree.cb | 86 +- src/mainboard/intel/truxton/irq_tables.c | 6 +- src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl | 4 +- src/mainboard/intel/wtm2/acpi_tables.c | 2 +- src/mainboard/intel/wtm2/cmos.layout | 150 +- src/mainboard/intel/wtm2/gpio.h | 190 +- src/mainboard/intel/wtm2/i915.c | 8 +- src/mainboard/intel/wtm2/intel_dp.c | 4 +- src/mainboard/intel/wtm2/mainboard.c | 8 +- src/mainboard/intel/wtm2/romstage.c | 8 +- src/mainboard/intel/xe7501devkit/acpi_tables.c | 2 +- src/mainboard/intel/xe7501devkit/cmos.layout | 60 +- src/mainboard/intel/xe7501devkit/irq_tables.c | 10 +- src/mainboard/intel/xe7501devkit/mptable.c | 50 +- src/mainboard/intel/xe7501devkit/romstage.c | 2 +- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 +- src/mainboard/iwave/iWRainbowG6/cmos.layout | 164 +- src/mainboard/iwave/iWRainbowG6/fadt.c | 2 +- src/mainboard/iwave/iWRainbowG6/irq_tables.c | 26 +- src/mainboard/iwave/iWRainbowG6/romstage.c | 14 +- src/mainboard/iwill/dk8_htx/acpi/amd8111.asl | 276 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl | 332 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl | 706 +-- src/mainboard/iwill/dk8_htx/acpi/amd8131.asl | 192 +- src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl | 206 +- src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl | 206 +- src/mainboard/iwill/dk8_htx/acpi/amd8151.asl | 52 +- src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl | 26 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 248 +- 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src/mainboard/jetway/j7f24/cmos.layout | 118 +- src/mainboard/jetway/j7f24/devicetree.cb | 46 +- src/mainboard/jetway/j7f24/irq_tables.c | 2 +- src/mainboard/jetway/pa78vm5/acpi/ide.asl | 8 +- src/mainboard/jetway/pa78vm5/acpi_tables.c | 2 +- src/mainboard/jetway/pa78vm5/cmos.layout | 160 +- src/mainboard/jetway/pa78vm5/devicetree.cb | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 84 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 8 +- src/mainboard/jetway/pa78vm5/resourcemap.c | 190 +- src/mainboard/jetway/pa78vm5/romstage.c | 4 +- src/mainboard/kontron/986lcd-m/cmos.layout | 242 +- src/mainboard/kontron/986lcd-m/devicetree.cb | 98 +- src/mainboard/kontron/986lcd-m/irq_tables.c | 6 +- src/mainboard/kontron/986lcd-m/mptable.c | 8 +- src/mainboard/kontron/kt690/acpi/ide.asl | 8 +- src/mainboard/kontron/kt690/acpi_tables.c | 2 +- src/mainboard/kontron/kt690/cmos.layout | 160 +- src/mainboard/kontron/kt690/devicetree.cb | 4 +- src/mainboard/kontron/kt690/dsdt.asl | 80 +- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 +- src/mainboard/kontron/kt690/mptable.c | 6 +- .../kontron/ktqm77/acpi/sandybridge_pci_irqs.asl | 20 +- src/mainboard/kontron/ktqm77/acpi_tables.c | 2 +- src/mainboard/kontron/ktqm77/cmos.layout | 206 +- src/mainboard/kontron/ktqm77/gpio.h | 4 +- src/mainboard/kontron/ktqm77/hda_verb.h | 26 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +- src/mainboard/kontron/ktqm77/romstage.c | 60 +- src/mainboard/lanner/em8510/cmos.layout | 118 +- src/mainboard/lanner/em8510/devicetree.cb | 48 +- src/mainboard/lanner/em8510/irq_tables.c | 4 +- src/mainboard/lanner/em8510/romstage.c | 6 +- src/mainboard/lenovo/Kconfig | 2 +- src/mainboard/lenovo/t60/acpi/dock.asl | 2 +- src/mainboard/lenovo/t60/acpi/platform.asl | 14 +- src/mainboard/lenovo/t60/acpi/video.asl | 2 +- src/mainboard/lenovo/t60/cmos.layout | 176 +- src/mainboard/lenovo/t60/irq_tables.c | 20 +- src/mainboard/lenovo/t60/mptable.c | 34 +- src/mainboard/lenovo/x60/acpi/dock.asl | 6 +- src/mainboard/lenovo/x60/acpi/platform.asl | 14 +- src/mainboard/lenovo/x60/acpi/video.asl | 2 +- src/mainboard/lenovo/x60/cmos.layout | 176 +- src/mainboard/lenovo/x60/drm_dp_helper.h | 184 +- src/mainboard/lenovo/x60/i915.c | 8 +- src/mainboard/lenovo/x60/i915_reg.h | 2714 +++++------ src/mainboard/lenovo/x60/intel_dp.c | 6 +- src/mainboard/lenovo/x60/irq_tables.c | 20 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/lenovo/x60/mptable.c | 36 +- src/mainboard/lenovo/x60/romstage.c | 4 +- .../lippert/frontrunner-af/BiosCallOuts.c | 28 +- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 6 +- src/mainboard/lippert/frontrunner-af/acpi/ide.asl | 8 +- .../lippert/frontrunner-af/agesawrapper.c | 40 +- src/mainboard/lippert/frontrunner-af/cmos.layout | 160 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 126 +- .../lippert/frontrunner-af/get_bus_conf.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 38 +- .../lippert/frontrunner-af/platform_cfg.h | 24 +- src/mainboard/lippert/frontrunner/cmos.layout | 118 +- src/mainboard/lippert/frontrunner/devicetree.cb | 10 +- src/mainboard/lippert/frontrunner/irq_tables.c | 10 +- src/mainboard/lippert/frontrunner/romstage.c | 12 +- src/mainboard/lippert/hurricane-lx/devicetree.cb | 114 +- src/mainboard/lippert/hurricane-lx/irq_tables.c | 10 +- src/mainboard/lippert/hurricane-lx/mainboard.c | 14 +- src/mainboard/lippert/literunner-lx/devicetree.cb | 114 +- src/mainboard/lippert/literunner-lx/irq_tables.c | 12 +- src/mainboard/lippert/literunner-lx/mainboard.c | 16 +- src/mainboard/lippert/roadrunner-lx/devicetree.cb | 114 +- src/mainboard/lippert/roadrunner-lx/irq_tables.c | 8 +- src/mainboard/lippert/roadrunner-lx/mainboard.c | 10 +- src/mainboard/lippert/spacerunner-lx/devicetree.cb | 116 +- src/mainboard/lippert/spacerunner-lx/irq_tables.c | 8 +- src/mainboard/lippert/spacerunner-lx/mainboard.c | 16 +- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 28 +- src/mainboard/lippert/toucan-af/OptionsIds.h | 6 +- src/mainboard/lippert/toucan-af/acpi/ide.asl | 8 +- src/mainboard/lippert/toucan-af/agesawrapper.c | 40 +- src/mainboard/lippert/toucan-af/cmos.layout | 160 +- src/mainboard/lippert/toucan-af/dsdt.asl | 126 +- src/mainboard/lippert/toucan-af/get_bus_conf.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 14 +- src/mainboard/lippert/toucan-af/platform_cfg.h | 24 +- src/mainboard/mitac/6513wu/devicetree.cb | 96 +- src/mainboard/mitac/6513wu/irq_tables.c | 26 +- src/mainboard/msi/ms6119/devicetree.cb | 68 +- src/mainboard/msi/ms6119/irq_tables.c | 2 +- src/mainboard/msi/ms6147/devicetree.cb | 68 +- src/mainboard/msi/ms6147/irq_tables.c | 2 +- src/mainboard/msi/ms6156/devicetree.cb | 68 +- src/mainboard/msi/ms6156/irq_tables.c | 2 +- src/mainboard/msi/ms6178/devicetree.cb | 78 +- src/mainboard/msi/ms6178/irq_tables.c | 2 +- src/mainboard/msi/ms7135/cmos.layout | 180 +- src/mainboard/msi/ms7135/devicetree.cb | 114 +- src/mainboard/msi/ms7260/cmos.layout | 160 +- src/mainboard/msi/ms7260/devicetree.cb | 248 +- src/mainboard/msi/ms7260/get_bus_conf.c | 30 +- src/mainboard/msi/ms7260/mptable.c | 20 +- src/mainboard/msi/ms7260/resourcemap.c | 190 +- src/mainboard/msi/ms7260/romstage.c | 12 +- src/mainboard/msi/ms9185/cmos.layout | 160 +- src/mainboard/msi/ms9185/devicetree.cb | 182 +- src/mainboard/msi/ms9185/get_bus_conf.c | 34 +- src/mainboard/msi/ms9185/irq_tables.c | 32 +- src/mainboard/msi/ms9185/mptable.c | 108 +- src/mainboard/msi/ms9185/resourcemap.c | 490 +- src/mainboard/msi/ms9185/romstage.c | 116 +- src/mainboard/msi/ms9282/cmos.layout | 160 +- src/mainboard/msi/ms9282/devicetree.cb | 326 +- src/mainboard/msi/ms9282/get_bus_conf.c | 30 +- src/mainboard/msi/ms9282/irq_tables.c | 66 +- src/mainboard/msi/ms9282/mb_sysconf.h | 4 +- src/mainboard/msi/ms9282/mptable.c | 74 +- src/mainboard/msi/ms9282/resourcemap.c | 490 +- src/mainboard/msi/ms9282/romstage.c | 78 +- src/mainboard/msi/ms9652_fam10/cmos.layout | 160 +- src/mainboard/msi/ms9652_fam10/devicetree.cb | 252 +- src/mainboard/msi/ms9652_fam10/dsdt.asl | 20 +- src/mainboard/msi/ms9652_fam10/resourcemap.c | 190 +- src/mainboard/msi/ms9652_fam10/romstage.c | 4 +- src/mainboard/nec/powermate2000/devicetree.cb | 58 +- src/mainboard/nec/powermate2000/irq_tables.c | 2 +- src/mainboard/newisys/khepri/cmos.layout | 160 +- src/mainboard/newisys/khepri/devicetree.cb | 48 +- src/mainboard/newisys/khepri/irq_tables.c | 20 +- src/mainboard/newisys/khepri/resourcemap.c | 4 +- src/mainboard/newisys/khepri/romstage.c | 44 +- src/mainboard/nokia/ip530/devicetree.cb | 114 +- src/mainboard/nokia/ip530/irq_tables.c | 2 +- src/mainboard/nvidia/l1_2pvv/cmos.layout | 160 +- src/mainboard/nvidia/l1_2pvv/devicetree.cb | 320 +- src/mainboard/nvidia/l1_2pvv/resourcemap.c | 190 +- src/mainboard/pcengines/alix1c/cmos.layout | 118 +- src/mainboard/pcengines/alix1c/devicetree.cb | 6 +- src/mainboard/pcengines/alix1c/irq_tables.c | 20 +- src/mainboard/pcengines/alix2d/cmos.layout | 118 +- src/mainboard/pcengines/alix2d/devicetree.cb | 4 +- src/mainboard/pcengines/alix2d/irq_tables.c | 22 +- src/mainboard/pcengines/alix2d/romstage.c | 18 +- src/mainboard/rca/rm4100/devicetree.cb | 62 +- src/mainboard/rca/rm4100/gpio.c | 2 +- src/mainboard/rca/rm4100/irq_tables.c | 8 +- src/mainboard/rca/rm4100/spd_table.h | 10 +- src/mainboard/roda/rk886ex/acpi/platform.asl | 14 +- src/mainboard/roda/rk886ex/cmos.layout | 166 +- src/mainboard/roda/rk886ex/devicetree.cb | 72 +- src/mainboard/roda/rk886ex/irq_tables.c | 6 +- src/mainboard/roda/rk886ex/m3885.c | 4 +- src/mainboard/roda/rk886ex/mptable.c | 8 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/roda/rk9/acpi/ec.asl | 32 +- src/mainboard/roda/rk9/acpi/platform.asl | 14 +- src/mainboard/roda/rk9/cmos.layout | 152 +- src/mainboard/roda/rk9/fadt.c | 2 +- src/mainboard/roda/rk9/hda_verb.h | 2 +- src/mainboard/roda/rk9/romstage.c | 8 +- src/mainboard/samsung/lumpy/acpi/superio.asl | 18 +- src/mainboard/samsung/lumpy/acpi_tables.c | 2 +- src/mainboard/samsung/lumpy/cmos.layout | 150 +- src/mainboard/samsung/lumpy/devicetree.cb | 10 +- src/mainboard/samsung/lumpy/dsdt.asl | 2 +- src/mainboard/samsung/lumpy/ec.h | 46 +- src/mainboard/samsung/lumpy/gpio.h | 6 +- src/mainboard/samsung/lumpy/mainboard.c | 18 +- src/mainboard/samsung/lumpy/onboard.h | 10 +- src/mainboard/samsung/lumpy/romstage.c | 26 +- src/mainboard/samsung/stumpy/acpi/superio.asl | 20 +- src/mainboard/samsung/stumpy/acpi_tables.c | 2 +- src/mainboard/samsung/stumpy/cmos.layout | 150 +- src/mainboard/samsung/stumpy/gpio.h | 6 +- src/mainboard/samsung/stumpy/mainboard.c | 4 +- src/mainboard/samsung/stumpy/romstage.c | 22 +- src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl | 8 +- src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl | 44 +- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 2 +- src/mainboard/siemens/sitemp_g1p1/cmos.layout | 234 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 220 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +- src/mainboard/siemens/sitemp_g1p1/int15_func.c | 42 +- src/mainboard/siemens/sitemp_g1p1/int15_func.h | 6 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 174 +- src/mainboard/siemens/sitemp_g1p1/mptable.c | 6 +- src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb | 54 +- src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c | 2 +- src/mainboard/sunw/ultra40/cmos.layout | 160 +- src/mainboard/sunw/ultra40/devicetree.cb | 246 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 70 +- src/mainboard/sunw/ultra40/irq_tables.c | 110 +- src/mainboard/sunw/ultra40/mptable.c | 114 +- src/mainboard/sunw/ultra40/resourcemap.c | 190 +- src/mainboard/sunw/ultra40/romstage.c | 92 +- src/mainboard/supermicro/Kconfig | 2 +- src/mainboard/supermicro/h8dme/cmos.layout | 160 +- src/mainboard/supermicro/h8dme/devicetree.cb | 214 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 34 +- src/mainboard/supermicro/h8dme/irq_tables.c | 50 +- src/mainboard/supermicro/h8dme/mptable.c | 56 +- src/mainboard/supermicro/h8dme/resourcemap.c | 190 +- src/mainboard/supermicro/h8dme/romstage.c | 12 +- src/mainboard/supermicro/h8dmr/cmos.layout | 160 +- src/mainboard/supermicro/h8dmr/devicetree.cb | 254 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 34 +- src/mainboard/supermicro/h8dmr/irq_tables.c | 50 +- src/mainboard/supermicro/h8dmr/mptable.c | 58 +- src/mainboard/supermicro/h8dmr/resourcemap.c | 190 +- src/mainboard/supermicro/h8dmr/romstage.c | 122 +- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 160 +- src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 254 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/resourcemap.c | 190 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 58 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 16 +- src/mainboard/supermicro/h8qgi/OptionsIds.h | 8 +- src/mainboard/supermicro/h8qgi/acpi/ide.asl | 8 +- src/mainboard/supermicro/h8qgi/agesawrapper.c | 36 +- src/mainboard/supermicro/h8qgi/agesawrapper.h | 22 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 256 +- src/mainboard/supermicro/h8qgi/cmos.layout | 160 +- src/mainboard/supermicro/h8qgi/devicetree.cb | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 142 +- src/mainboard/supermicro/h8qgi/fadt.c | 2 +- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 4 +- src/mainboard/supermicro/h8qgi/rd890_cfg.h | 36 +- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 4 +- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 64 +- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 160 +- src/mainboard/supermicro/h8qme_fam10/devicetree.cb | 174 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/resourcemap.c | 190 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 52 +- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 44 +- src/mainboard/supermicro/h8scm/OptionsIds.h | 8 +- src/mainboard/supermicro/h8scm/acpi/ide.asl | 8 +- src/mainboard/supermicro/h8scm/agesawrapper.c | 36 +- src/mainboard/supermicro/h8scm/agesawrapper.h | 22 +- src/mainboard/supermicro/h8scm/buildOpts.c | 250 +- src/mainboard/supermicro/h8scm/cmos.layout | 160 +- src/mainboard/supermicro/h8scm/devicetree.cb | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 142 +- src/mainboard/supermicro/h8scm/fadt.c | 2 +- src/mainboard/supermicro/h8scm/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 4 +- src/mainboard/supermicro/h8scm/platform_oem.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.c | 4 +- src/mainboard/supermicro/h8scm/rd890_cfg.h | 36 +- src/mainboard/supermicro/h8scm/sb700_cfg.c | 4 +- src/mainboard/supermicro/h8scm/sb700_cfg.h | 64 +- src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl | 8 +- src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 4 +- src/mainboard/supermicro/h8scm_fam10/cmos.layout | 160 +- src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 50 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 86 +- .../supermicro/h8scm_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 8 +- src/mainboard/supermicro/h8scm_fam10/resourcemap.c | 190 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 4 +- src/mainboard/supermicro/x6dai_g/cmos.layout | 124 +- src/mainboard/supermicro/x6dai_g/debug.c | 186 +- src/mainboard/supermicro/x6dai_g/irq_tables.c | 8 +- src/mainboard/supermicro/x6dai_g/romstage.c | 12 +- src/mainboard/supermicro/x6dhe_g/cmos.layout | 124 +- src/mainboard/supermicro/x6dhe_g/debug.c | 186 +- src/mainboard/supermicro/x6dhe_g/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 12 +- src/mainboard/supermicro/x6dhe_g2/cmos.layout | 124 +- src/mainboard/supermicro/x6dhe_g2/debug.c | 186 +- src/mainboard/supermicro/x6dhe_g2/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhe_g2/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig/cmos.layout | 124 +- src/mainboard/supermicro/x6dhr_ig/debug.c | 186 +- src/mainboard/supermicro/x6dhr_ig/devicetree.cb | 6 +- src/mainboard/supermicro/x6dhr_ig/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig2/cmos.layout | 124 +- src/mainboard/supermicro/x6dhr_ig2/debug.c | 186 +- src/mainboard/supermicro/x6dhr_ig2/devicetree.cb | 6 +- src/mainboard/supermicro/x6dhr_ig2/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 12 +- src/mainboard/supermicro/x7db8/cmos.layout | 154 +- src/mainboard/supermicro/x7db8/devicetree.cb | 24 +- src/mainboard/supermicro/x7db8/irq_tables.c | 4 +- src/mainboard/supermicro/x7db8/romstage.c | 2 +- src/mainboard/technexion/tim5690/acpi/ide.asl | 8 +- src/mainboard/technexion/tim5690/acpi_tables.c | 2 +- src/mainboard/technexion/tim5690/cmos.layout | 160 +- src/mainboard/technexion/tim5690/devicetree.cb | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 80 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 64 +- src/mainboard/technexion/tim5690/mptable.c | 6 +- src/mainboard/technexion/tim5690/tn_post_code.h | 6 +- src/mainboard/technexion/tim5690/vgabios.c | 48 +- src/mainboard/technexion/tim5690/vgabios.h | 6 +- src/mainboard/technexion/tim8690/acpi/ide.asl | 8 +- src/mainboard/technexion/tim8690/acpi_tables.c | 2 +- src/mainboard/technexion/tim8690/cmos.layout | 160 +- src/mainboard/technexion/tim8690/devicetree.cb | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 80 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 4 +- src/mainboard/technexion/tim8690/mptable.c | 6 +- src/mainboard/technologic/ts5300/cmos.layout | 118 +- src/mainboard/technologic/ts5300/irq_tables.c | 10 +- src/mainboard/technologic/ts5300/mainboard.c | 2 +- src/mainboard/technologic/ts5300/romstage.c | 10 +- src/mainboard/televideo/tc7020/devicetree.cb | 74 +- src/mainboard/thomson/ip1000/devicetree.cb | 62 +- src/mainboard/thomson/ip1000/gpio.c | 2 +- src/mainboard/thomson/ip1000/irq_tables.c | 8 +- src/mainboard/thomson/ip1000/mainboard.c | 4 +- src/mainboard/thomson/ip1000/spd_table.h | 10 +- src/mainboard/ti/beaglebone/Kconfig | 4 +- src/mainboard/traverse/geos/Kconfig | 4 +- src/mainboard/traverse/geos/cmos.layout | 120 +- src/mainboard/traverse/geos/irq_tables.c | 6 +- src/mainboard/tyan/Kconfig | 2 +- src/mainboard/tyan/s1846/devicetree.cb | 58 +- src/mainboard/tyan/s2735/cmos.layout | 132 +- src/mainboard/tyan/s2735/devicetree.cb | 150 +- src/mainboard/tyan/s2735/irq_tables.c | 10 +- src/mainboard/tyan/s2735/mptable.c | 56 +- src/mainboard/tyan/s2735/romstage.c | 20 +- src/mainboard/tyan/s2850/cmos.layout | 160 +- src/mainboard/tyan/s2850/devicetree.cb | 108 +- src/mainboard/tyan/s2850/irq_tables.c | 20 +- src/mainboard/tyan/s2850/mptable.c | 176 +- src/mainboard/tyan/s2850/romstage.c | 28 +- src/mainboard/tyan/s2875/cmos.layout | 160 +- src/mainboard/tyan/s2875/devicetree.cb | 16 +- src/mainboard/tyan/s2875/irq_tables.c | 20 +- src/mainboard/tyan/s2875/mptable.c | 184 +- src/mainboard/tyan/s2875/romstage.c | 28 +- src/mainboard/tyan/s2880/cmos.layout | 160 +- src/mainboard/tyan/s2880/devicetree.cb | 96 +- src/mainboard/tyan/s2880/irq_tables.c | 18 +- src/mainboard/tyan/s2880/mptable.c | 242 +- src/mainboard/tyan/s2880/romstage.c | 30 +- src/mainboard/tyan/s2881/cmos.layout | 160 +- src/mainboard/tyan/s2881/devicetree.cb | 220 +- src/mainboard/tyan/s2881/get_bus_conf.c | 40 +- src/mainboard/tyan/s2881/irq_tables.c | 54 +- src/mainboard/tyan/s2881/mptable.c | 74 +- src/mainboard/tyan/s2881/resourcemap.c | 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src/southbridge/nvidia/mcp55/early_smbus.c | 2 +- src/southbridge/nvidia/mcp55/ht.c | 8 +- src/southbridge/nvidia/mcp55/ide.c | 10 +- src/southbridge/nvidia/mcp55/lpc.c | 22 +- src/southbridge/nvidia/mcp55/nic.c | 2 +- src/southbridge/rdc/r8610/bootblock.c | 2 +- src/southbridge/rdc/r8610/r8610.c | 6 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 14 +- src/southbridge/sis/sis966/aza.c | 66 +- src/southbridge/sis/sis966/early_smbus.c | 118 +- src/southbridge/sis/sis966/ide.c | 44 +- src/southbridge/sis/sis966/lpc.c | 60 +- src/southbridge/sis/sis966/nic.c | 160 +- src/southbridge/sis/sis966/sata.c | 50 +- src/southbridge/sis/sis966/sis761.c | 10 +- src/southbridge/sis/sis966/usb.c | 34 +- src/southbridge/sis/sis966/usb2.c | 70 +- src/southbridge/ti/pci1x2x/pci1x2x.c | 16 +- src/southbridge/ti/pci7420/cardbus.c | 12 +- src/southbridge/ti/pci7420/firewire.c | 8 +- src/southbridge/ti/pci7420/pci7420.h | 28 +- src/southbridge/ti/pcixx12/pcixx12.c | 10 +- .../via/common/early_smbus_print_error.c | 2 +- src/southbridge/via/k8t890/Kconfig | 4 +- src/southbridge/via/k8t890/chrome.c | 14 +- src/southbridge/via/k8t890/dram.c | 6 +- src/southbridge/via/k8t890/pcie.c | 4 +- src/southbridge/via/vt8231/acpi.c | 6 +- src/southbridge/via/vt8231/enable_rom.c | 2 +- src/southbridge/via/vt8231/ide.c | 6 +- src/southbridge/via/vt8231/lpc.c | 10 +- src/southbridge/via/vt8231/nic.c | 6 +- src/southbridge/via/vt8235/early_smbus.c | 6 +- src/southbridge/via/vt8235/ide.c | 10 +- src/southbridge/via/vt8235/lpc.c | 16 +- src/southbridge/via/vt8235/nic.c | 10 +- src/southbridge/via/vt8235/usb.c | 10 +- src/southbridge/via/vt8237r/ctrl.c | 10 +- src/southbridge/via/vt8237r/early_smbus.c | 18 +- src/southbridge/via/vt8237r/ide.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 18 +- src/southbridge/via/vt8237r/nvs.h | 2 +- src/southbridge/via/vt8237r/usb.c | 4 +- src/southbridge/via/vt8237r/vt8237r.h | 36 +- src/superio/acpi/pnp_generic.asl | 2 +- src/superio/acpi/pnp_uart.asl | 2 +- src/superio/fintek/f71805f/superio.c | 8 +- src/superio/fintek/f71859/superio.c | 8 +- src/superio/fintek/f71863fg/superio.c | 10 +- src/superio/fintek/f71872/superio.c | 8 +- src/superio/fintek/f71889/superio.c | 8 +- src/superio/fintek/f81865f/superio.c | 8 +- src/superio/intel/i3100/superio.c | 8 +- src/superio/ite/it8661f/it8661f.h | 4 +- src/superio/ite/it8661f/superio.c | 6 +- src/superio/ite/it8671f/early_serial.c | 16 +- src/superio/ite/it8671f/superio.c | 6 +- src/superio/ite/it8673f/early_serial.c | 10 +- src/superio/ite/it8673f/superio.c | 6 +- src/superio/ite/it8705f/early_serial.c | 10 +- src/superio/ite/it8705f/superio.c | 6 +- src/superio/ite/it8712f/early_serial.c | 12 +- src/superio/ite/it8712f/superio.c | 8 +- src/superio/ite/it8716f/early_serial.c | 10 +- src/superio/ite/it8716f/superio.c | 12 +- src/superio/ite/it8718f/early_serial.c | 10 +- src/superio/ite/it8718f/superio.c | 6 +- src/superio/ite/it8721f/early_serial.c | 10 +- src/superio/ite/it8721f/superio.c | 6 +- src/superio/ite/it8728f/it8728f.h | 4 +- src/superio/ite/it8772f/early_serial.c | 12 +- src/superio/ite/it8772f/superio.c | 8 +- src/superio/nsc/pc8374/superio.c | 6 +- src/superio/nsc/pc87309/superio.c | 6 +- src/superio/nsc/pc87351/superio.c | 6 +- src/superio/nsc/pc87360/superio.c | 6 +- src/superio/nsc/pc87366/superio.c | 6 +- src/superio/nsc/pc87382/superio.c | 6 +- src/superio/nsc/pc87384/superio.c | 4 +- src/superio/nsc/pc87392/superio.c | 6 +- src/superio/nsc/pc87417/superio.c | 6 +- src/superio/nsc/pc87427/superio.c | 6 +- src/superio/nsc/pc97307/chip.h | 4 +- src/superio/nsc/pc97307/superio.c | 6 +- src/superio/nsc/pc97317/chip.h | 4 +- src/superio/nsc/pc97317/superio.c | 6 +- src/superio/nuvoton/nct5104d/superio.c | 8 +- src/superio/nuvoton/wpcm450/superio.c | 6 +- src/superio/renesas/m3885x/superio.c | 4 +- src/superio/smsc/fdc37m60x/early_serial.c | 10 +- src/superio/smsc/fdc37m60x/superio.c | 6 +- src/superio/smsc/fdc37n972/fdc37n972.c | 6 +- src/superio/smsc/kbc1100/kbc1100.h | 20 +- src/superio/smsc/kbc1100/kbc1100_early_init.c | 2 +- src/superio/smsc/kbc1100/superio.c | 6 +- src/superio/smsc/lpc47b272/lpc47b272.h | 12 +- src/superio/smsc/lpc47b272/superio.c | 8 +- src/superio/smsc/lpc47b397/superio.c | 20 +- src/superio/smsc/lpc47m10x/lpc47m10x.h | 16 +- src/superio/smsc/lpc47m10x/superio.c | 8 +- src/superio/smsc/lpc47m15x/lpc47m15x.h | 16 +- src/superio/smsc/lpc47m15x/superio.c | 8 +- src/superio/smsc/lpc47n207/early_serial.c | 4 +- src/superio/smsc/lpc47n217/lpc47n217.h | 6 +- src/superio/smsc/lpc47n217/superio.c | 12 +- src/superio/smsc/lpc47n227/lpc47n227.h | 8 +- src/superio/smsc/lpc47n227/superio.c | 10 +- src/superio/smsc/mec1308/superio.c | 8 +- src/superio/smsc/sch4037/sch4037.h | 18 +- src/superio/smsc/sch4037/superio.c | 8 +- src/superio/smsc/sio1036/superio.c | 8 +- src/superio/smsc/sio10n268/sio10n268.c | 6 +- src/superio/smsc/smscsuperio/superio.c | 26 +- src/superio/via/vt1211/vt1211.c | 14 +- src/superio/winbond/w83627dhg/acpi/superio.asl | 2 +- src/superio/winbond/w83627dhg/superio.c | 8 +- src/superio/winbond/w83627dhg/w83627dhg.h | 24 +- src/superio/winbond/w83627ehg/superio.c | 12 +- src/superio/winbond/w83627ehg/w83627ehg.h | 20 +- src/superio/winbond/w83627hf/acpi/superio.asl | 156 +- src/superio/winbond/w83627hf/superio.c | 14 +- src/superio/winbond/w83627hf/w83627hf.h | 20 +- src/superio/winbond/w83627thg/superio.c | 20 +- src/superio/winbond/w83627thg/w83627thg.h | 18 +- src/superio/winbond/w83627uhg/superio.c | 10 +- src/superio/winbond/w83627uhg/w83627uhg.h | 2 +- src/superio/winbond/w83697hf/superio.c | 10 +- src/superio/winbond/w83697hf/w83697hf.h | 20 +- src/superio/winbond/w83977f/superio.c | 8 +- src/superio/winbond/w83977tf/superio.c | 10 +- src/superio/winbond/w83977tf/w83977tf.h | 18 +- 2342 files changed, 71350 insertions(+), 71350 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 1c80b8c..e0c0d02 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,16 +159,16 @@ config INCLUDE_CONFIG_FILE $ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, - offset 0x0 + offset 0x0 Alignment: 64 bytes - Name Offset Type Size - cmos_layout.bin 0x0 cmos layout 1159 - fallback/romstage 0x4c0 stage 339756 - fallback/coreboot_ram 0x53440 stage 186664 - fallback/payload 0x80dc0 payload 51526 - config 0x8d740 raw 3324 - (empty) 0x8e480 null 3610440 + Name Offset Type Size + cmos_layout.bin 0x0 cmos layout 1159 + fallback/romstage 0x4c0 stage 339756 + fallback/coreboot_ram 0x53440 stage 186664 + fallback/payload 0x80dc0 payload 51526 + config 0x8d740 raw 3324 + (empty) 0x8e480 null 3610440 config EARLY_CBMEM_INIT bool diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4b1c591..235f1cb 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -52,7 +52,7 @@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuil -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ -o $(CONFIG_CBFS_ROM_OFFSET) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" $(CBFSTOOL) $@.tmp add-stage \ -f $(objcbfs)/romstage.elf -b 0 \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none @@ -66,18 +66,18 @@ $(obj)/coreboot.pre: $(CBFSTOOL) endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" + @printf " PAYLOAD none (as specified by user)\n" endif ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" + @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ @@ -97,11 +97,11 @@ bootsplash.jpg-type := bootsplash # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -O binary $< $@ $(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp $(NM) -n $@.tmp | sort > $(basename $(a)).map $(OBJCOPY) --strip-debug $@.tmp @@ -112,7 +112,7 @@ stages_c = $(src)/arch/armv7/stages.c stages_o = $(obj)/arch/armv7/stages.o $(stages_o): $(stages_c) $(obj)/config.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I. $(INCLUDES) -c -o $@ $< -marm @@ -120,7 +120,7 @@ $(stages_o): $(stages_c) $(obj)/config.h # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/armv7/coreboot_ram.ld - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/coreboot_ram.ld else @@ -128,7 +128,7 @@ else endif $(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else @@ -156,7 +156,7 @@ crt0s += $(cpu_incs) crt0s += $(cpu_incs-y) $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" + @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ # Things that appear in every board @@ -235,19 +235,19 @@ bootblock_custom = $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_CPU_INIT)) bootblock_custom += $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_MAINBOARD_INIT)) $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) $(obj)/config.h @@ -258,7 +258,7 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_S $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else @@ -269,7 +269,7 @@ endif # Build the romstage $(objcbfs)/romstage.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld else @@ -277,20 +277,20 @@ else endif $(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@ $(objgenerated)/crt0.romstage.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index b2c993a..919b3d7 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -11,7 +11,7 @@ * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> - * Copyright (c) 2013 The Chromium OS Authors + * Copyright (c) 2013 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c index 04eaa88..cc88c98 100644 --- a/src/arch/armv7/cache.c +++ b/src/arch/armv7/cache.c @@ -123,9 +123,9 @@ static void dcache_op_set_way(enum dcache_op op) * S: Log2(num_sets) * * The bits are packed as follows: - * 31 31-A B B-1 L L-1 4 3 1 0 + * 31 31-A B B-1 L L-1 4 3 1 0 * |---|-------------|--------|-------|-----|-| - * |Way| zeros | Set | zeros |level|0| + * |Way| zeros | Set | zeros |level|0| * |---|-------------|--------|-------|-----|-| */ for (way = 0; way < associativity; way++) { diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 38eaca3..756d8b4 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -15,7 +15,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */ @@ -107,13 +107,13 @@ SECTIONS * this line. */ - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; _stack = CONFIG_STACK_BOTTOM; _estack = CONFIG_STACK_TOP; diff --git a/src/arch/armv7/id.inc b/src/arch/armv7/id.inc index ffe547d..476fa3d 100644 --- a/src/arch/armv7/id.inc +++ b/src/arch/armv7/id.inc @@ -10,8 +10,8 @@ part: .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end - ver /* Reverse offset to the vendor id */ .long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end __id_end: diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5166af3..6abd0b8 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -54,7 +54,7 @@ /* Bits 20:19 reserved virtualization not supported */ #define SCTLR_WXN (1 << 19) /* Write permission implies XN */ #define SCTLR_UWXN (1 << 20) /* Unprivileged write permission - implies PL1 XN */ + implies PL1 XN */ #define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ #define SCTLR_U (1 << 22) /* Unaligned access behavior */ #define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index f8b3005..113711f 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -41,9 +41,9 @@ struct cpu_info { }; struct cpuinfo_arm { - uint8_t arm; /* CPU family */ - uint8_t arm_vendor; /* CPU vendor */ - uint8_t arm_model; + uint8_t arm; /* CPU family */ + uint8_t arm_vendor; /* CPU vendor */ + uint8_t arm_model; }; #endif diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 10363c4..33ae227 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -34,11 +34,11 @@ #define get_byte_0 lsr #24 #define get_byte_1 lsr #16 #define get_byte_2 lsr #8 -#define get_byte_3 lsl #0 +#define get_byte_3 lsl #0 #define put_byte_0 lsl #24 #define put_byte_1 lsl #16 #define put_byte_2 lsl #8 -#define put_byte_3 lsl #0 +#define put_byte_3 lsl #0 #endif /* diff --git a/src/arch/armv7/include/stdint.h b/src/arch/armv7/include/stdint.h index a8a0230..b805139 100644 --- a/src/arch/armv7/include/stdint.h +++ b/src/arch/armv7/include/stdint.h @@ -8,14 +8,14 @@ #endif /* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed char int8_t; -typedef unsigned short uint16_t; -typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed short int16_t; -typedef unsigned int uint32_t; -typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef signed int int32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint64_t; @@ -23,14 +23,14 @@ typedef signed long long int64_t; #endif /* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t; -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t; -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_least64_t; @@ -38,14 +38,14 @@ typedef signed long long int_least64_t; #endif /* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t; -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t; -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; @@ -53,15 +53,15 @@ typedef signed long long int_fast64_t; #endif /* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef int intptr_t; +typedef unsigned int uintptr_t; /* Largest integral types */ #if __HAVE_LONG_LONG__ -typedef long long int intmax_t; +typedef long long int intmax_t; typedef unsigned long long uintmax_t; #else -typedef long int intmax_t; +typedef long int intmax_t; typedef unsigned long int uintmax_t; #endif diff --git a/src/arch/armv7/interrupts.c b/src/arch/armv7/interrupts.c index 7508c69..e8cb834 100644 --- a/src/arch/armv7/interrupts.c +++ b/src/arch/armv7/interrupts.c @@ -57,11 +57,11 @@ void enable_interrupts (void) { unsigned long temp; __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); } @@ -73,11 +73,11 @@ int disable_interrupts (void) { unsigned long old,temp; __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); return (old & 0x80) == 0; } #else diff --git a/src/arch/armv7/memmove.S b/src/arch/armv7/memmove.S index a2f9ea1..a593d44 100644 --- a/src/arch/armv7/memmove.S +++ b/src/arch/armv7/memmove.S @@ -147,25 +147,25 @@ memmove: 12: PLD( pld [r1, #-128] ) 13: ldmdb r1!, {r7, r8, r9, ip} - mov lr, r3, push #\push - subs r2, r2, #32 - ldmdb r1!, {r3, r4, r5, r6} - orr lr, lr, ip, pull #\pull - mov ip, ip, push #\push - orr ip, ip, r9, pull #\pull - mov r9, r9, push #\push - orr r9, r9, r8, pull #\pull - mov r8, r8, push #\push - orr r8, r8, r7, pull #\pull - mov r7, r7, push #\push - orr r7, r7, r6, pull #\pull - mov r6, r6, push #\push - orr r6, r6, r5, pull #\pull - mov r5, r5, push #\push - orr r5, r5, r4, pull #\pull - mov r4, r4, push #\push - orr r4, r4, r3, pull #\pull - stmdb r0!, {r4 - r9, ip, lr} + mov lr, r3, push #\push + subs r2, r2, #32 + ldmdb r1!, {r3, r4, r5, r6} + orr lr, lr, ip, pull #\pull + mov ip, ip, push #\push + orr ip, ip, r9, pull #\pull + mov r9, r9, push #\push + orr r9, r9, r8, pull #\pull + mov r8, r8, push #\push + orr r8, r8, r7, pull #\pull + mov r7, r7, push #\push + orr r7, r7, r6, pull #\pull + mov r6, r6, push #\push + orr r6, r6, r5, pull #\pull + mov r5, r5, push #\push + orr r5, r5, r4, pull #\pull + mov r4, r4, push #\push + orr r4, r4, r3, pull #\pull + stmdb r0!, {r4 - r9, ip, lr} bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c index 7d6d46a..f51ab57 100644 --- a/src/arch/armv7/mmu.c +++ b/src/arch/armv7/mmu.c @@ -73,11 +73,11 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, * 15 - APX, 0 for full access * 14:12 - TEX, 0b000 for outer and inner write-back * 11:10 - AP, 0b11 for full access - * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 9 - P, ? (FIXME: not described or possibly obsolete?) * 8: 5 - Domain - * 4 - XN, 1 to set execute-never (and also avoid prefetches) - * 3 - C, 1 for cacheable - * 2 - B, 1 for bufferable + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable * 1: 0 - 0b10 to indicate section entry */ diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0555fc4..81b0a60 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -15,7 +15,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e54645..8308bb3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -88,46 +88,46 @@ endif endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB_ELF) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" + @printf " PAYLOAD none (as specified by user)\n" endif ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) endif ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) - @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif endif ifeq ($(CONFIG_PAYLOAD_FILO),y) - @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_PAYLOAD_GRUB2),y) - @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) - @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" + @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ @@ -167,22 +167,22 @@ bootsplash.jpg-type := bootsplash NVRAMTOOL:=$(objutil)/nvramtool/nvramtool $(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" + @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" + @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ ################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -O binary $< $@ $(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp $(NM) -n $@.tmp | sort > $(basename $(a)).map $(OBJCOPY) --strip-debug $@.tmp @@ -199,7 +199,7 @@ $(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/corebo else $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld else @@ -209,7 +209,7 @@ endif endif $(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else @@ -251,16 +251,16 @@ else endif $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - printf " ROMCC romstage.inc\n" + printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" + @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" + @printf " POST romstage.inc\n" sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp mv $@.tmp $@ @@ -312,7 +312,7 @@ endif # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/romstage_xip.elf \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ @@ -353,29 +353,29 @@ bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ endif $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) - @printf " ROMCC $(subst $(obj)/,,$(@))\n" + @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else @@ -386,7 +386,7 @@ endif # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld else @@ -398,7 +398,7 @@ endif else true; fi $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld else @@ -406,14 +406,14 @@ else endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp sed -e '/ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp @@ -426,15 +426,15 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin mv $@.tmp $@ $(objgenerated)/crt0.romstage.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ seabios: diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl index d9f1f83..0c155d5 100644 --- a/src/arch/x86/acpi/statdef.asl +++ b/src/arch/x86/acpi/statdef.asl @@ -20,26 +20,26 @@ /* Status and notification definitions */ -#define STA_MISSING 0x00 -#define STA_PRESENT 0x01 -#define STA_ENABLED 0x03 -#define STA_DISABLED 0x09 -#define STA_INVISIBLE 0x0B +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B #define STA_UNAVAILABLE 0x0D -#define STA_VISIBLE 0x0F +#define STA_VISIBLE 0x0F /* SMBus status codes */ -#define SMB_OK 0x00 -#define SMB_UnknownFail 0x07 -#define SMB_DevAddrNAK 0x10 -#define SMB_DeviceError 0x11 -#define SMB_DevCmdDenied 0x12 -#define SMB_UnknownErr 0x13 -#define SMB_DevAccDenied 0x17 -#define SMB_Timeout 0x18 -#define SMB_HstUnsuppProtocol 0x19 -#define SMB_Busy 0x1A -#define SMB_PktChkError 0x1F +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F /* Device Object Notification Values */ #define NOTIFY_BUS_CHECK 0x00 @@ -57,14 +57,14 @@ /* Battery Device Notification Values */ #define NOTIFY_BAT_STATUSCHG 0x80 #define NOTIFY_BAT_INFOCHG 0x81 -#define NOTIFY_BAT_MAINTDATA 0x82 +#define NOTIFY_BAT_MAINTDATA 0x82 /* Power Source Object Notification Values */ #define NOTIFY_PWR_STATUSCHG 0x80 /* Thermal Zone Object Notification Values */ -#define NOTIFY_TZ_STATUSCHG 0x80 -#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 #define NOTIFY_TZ_DEVLISTCHG 0x82 #define NOTIFY_TZ_RELTBLCHG 0x83 @@ -80,7 +80,7 @@ /* Processor Device Notification Values */ #define NOTIFY_CPU_PPCCHG 0x80 #define NOTIFY_CPU_CSTATECHG 0x81 -#define NOTIFY_CPU_THROTLCHG 0x82 +#define NOTIFY_CPU_THROTLCHG 0x82 /* User Presence Device Notification Values */ #define NOTIFY_USR_PRESNCECHG 0x80 @@ -88,6 +88,6 @@ /* Battery Device Notification Values */ #define NOTIFY_ALS_ILLUMCHG 0x80 #define NOTIFY_ALS_COLORTMPCHG 0x81 -#define NOTIFY_ALS_RESPCHG 0x82 +#define NOTIFY_ALS_RESPCHG 0x82 diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96cb270..3e60f90 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -629,7 +629,7 @@ void acpi_resume(void *wake_vec) /* Restore GNVS pointer in SMM if found */ if (gnvs_address && *gnvs_address) { printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); + *gnvs_address); smm_setup_structures((void *)*gnvs_address, NULL, NULL); } #endif @@ -723,7 +723,7 @@ void *acpi_find_wakeup_vector(void) if (facs == NULL) { printk(BIOS_DEBUG, "No FACS found, wake up from S3 not " - "possible.\n"); + "possible.\n"); return NULL; } @@ -757,7 +757,7 @@ void acpi_jump_to_wakeup(void *vector) if (!acpi_backup_memory) { printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); + "No S3 resume.\n"); return; } #endif @@ -779,7 +779,7 @@ void acpi_jump_to_wakeup(void *vector) #endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + HIGH_MEMORY_SAVE); } #endif diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..c706813 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -264,8 +264,8 @@ int acpigen_write_scope(const char *name) int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* - Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) - { + Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) + { */ char pscope[16]; int len; @@ -290,32 +290,32 @@ int acpigen_write_empty_PCT(void) /* Name (_PCT, Package (0x02) { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } }) */ static char stream[] = { - 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */ - 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */ - 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */ - 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */ - 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ + 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */ + 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */ + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */ + 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ 0x00, 0x79, 0x00 }; return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); @@ -326,23 +326,23 @@ int acpigen_write_empty_PTC(void) /* Name (_PTC, Package (0x02) { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } }) */ int len, nlen, rlen; @@ -384,7 +384,7 @@ int acpigen_write_PPC(u8 nr) /* Method (_PPC, 0, NotSerialized) { - Return (nr) + Return (nr) } */ int len; @@ -413,7 +413,7 @@ int acpigen_write_PPC_NVS(void) /* Method (_PPC, 0, NotSerialized) { - Return (PPCM) + Return (PPCM) } */ int len; @@ -439,7 +439,7 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) // Sample _TPC method Method (_TPC, 0, NotSerialized) { - Return (\TLVL) + Return (\TLVL) } */ int len; @@ -455,7 +455,7 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) } int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, - u32 busmLat, u32 control, u32 status) + u32 busmLat, u32 control, u32 status) { int len; len = acpigen_write_package(6); @@ -469,7 +469,7 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, acpigen_patch_len(len - 1); printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", - coreFreq, power, control, status); + coreFreq, power, control, status); return len; } @@ -532,8 +532,8 @@ int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) Sample _TSS package with 100% and 50% duty cycles Name (_TSS, Package (0x02) { - Package(){100, 1000, 0, 0x00, 0) - Package(){50, 520, 0, 0x18, 0) + Package(){100, 1000, 0, 0x00, 0) + Package(){50, 520, 0, 0x18, 0) }) */ int i, len, plen, nlen; diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 1b28a4c..f36099f 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -49,7 +49,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) " pushl %%ebx\n\t" /* Save the parameters I was passed */ " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ + " pushl %0\n\t" /* 16 lb_start */ " pushl %1\n\t" /* 12 buffer */ " pushl %2\n\t" /* 8 lb_size */ " pushl %3\n\t" /* 4 entry */ diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 8c380e5..e9c5598 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -56,26 +56,26 @@ static unsigned char smp_compute_checksum(void *v, int len) static void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr, unsigned int virtualwire) { - struct intel_mp_floating *mf; - void *v; + struct intel_mp_floating *mf; + void *v; v = (void *)addr; - mf = v; - mf->mpf_signature[0] = '_'; - mf->mpf_signature[1] = 'M'; - mf->mpf_signature[2] = 'P'; - mf->mpf_signature[3] = '_'; - mf->mpf_physptr = mpf_physptr; - mf->mpf_length = 1; - mf->mpf_specification = 4; - mf->mpf_checksum = 0; - mf->mpf_feature1 = 0; - mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0; - mf->mpf_feature3 = 0; - mf->mpf_feature4 = 0; - mf->mpf_feature5 = 0; - mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); - return v; + mf = v; + mf->mpf_signature[0] = '_'; + mf->mpf_signature[1] = 'M'; + mf->mpf_signature[2] = 'P'; + mf->mpf_signature[3] = '_'; + mf->mpf_physptr = mpf_physptr; + mf->mpf_length = 1; + mf->mpf_specification = 4; + mf->mpf_checksum = 0; + mf->mpf_feature1 = 0; + mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0; + mf->mpf_feature3 = 0; + mf->mpf_feature4 = 0; + mf->mpf_feature5 = 0; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); + return v; } void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire) @@ -170,7 +170,7 @@ void smp_write_processors(struct mp_config_table *mc) ); break; } - } + } } } @@ -351,12 +351,12 @@ void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa) void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external_int2) { -/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ +/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT, - MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0); + MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid, 0x1); smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT, - MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2); + MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid, 0x6); @@ -415,14 +415,14 @@ void *mptable_finalize(struct mp_config_table *mc) unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) { struct drivers_generic_ioapic_config *ioapic_config; - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; v = smp_write_floating_table(addr, 0); - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -439,8 +439,8 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) continue; } smp_write_ioapic(mc, dev->path.ioapic.ioapic_id, - ioapic_config->version, - ioapic_config->base); + ioapic_config->version, + ioapic_config->base); if (ioapic_config->have_isa_interrupts) { if (isaioapic >= 0) @@ -465,9 +465,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) for (pin = 0; pin < 4; pin++) { if (dev->pci_irq_info[pin].ioapic_dst_id) { printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); smp_write_intsrc(mc, mp_INT, dev->pci_irq_info[pin].ioapic_flags, dev->bus->secondary, @@ -489,9 +489,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (parent->pci_irq_info[parentpin].ioapic_dst_id) { printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); smp_write_intsrc(mc, mp_INT, parent->pci_irq_info[parentpin].ioapic_flags, dev->bus->secondary, diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index 86af63f..7586e85 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -33,8 +33,8 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) if (sizeof(struct irq_routing_table) != rt->size) { printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", - (unsigned int) sizeof(struct irq_routing_table), - rt->size + (unsigned int) sizeof(struct irq_routing_table), + rt->size ); rt->size=sizeof(struct irq_routing_table); } @@ -50,7 +50,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) if (sum != rt->checksum) { printk(BIOS_WARNING, "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n", - rt->checksum, sum); + rt->checksum, sum); rt->checksum = sum; } diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..02a46f5 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -138,7 +138,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); #else #define SPACES \ - " " + " " t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); u32 version_offset = (u32)smbios_string_table_len(t->eos); t->bios_version = smbios_add_string(t->eos, SPACES); @@ -396,7 +396,7 @@ unsigned long smbios_write_tables(unsigned long current) se->struct_table_length = len; se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, - sizeof(struct smbios_entry) - 0x10); + sizeof(struct smbios_entry) - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); return current; } diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index eea9bf1..f3eeb5a 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -139,7 +139,7 @@ struct lb_memory *write_tables(void) if (new_high_table_pointer > ( high_table_pointer + MAX_ACPI_SIZE)) { printk(BIOS_ERR, "ERROR: Increase ACPI size\n"); } - printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", + printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); /* Now we need to create a low table copy of the RSDP. */ @@ -157,7 +157,7 @@ struct lb_memory *write_tables(void) */ if (acpi_start < new_high_table_pointer) { acpi_rsdp_t *low_rsdp = (acpi_rsdp_t *)rom_table_end, - *high_rsdp = (acpi_rsdp_t *)acpi_start; + *high_rsdp = (acpi_rsdp_t *)acpi_start; acpi_write_rsdp(low_rsdp, (acpi_rsdt_t *)(high_rsdp->rsdt_address), @@ -186,7 +186,7 @@ struct lb_memory *write_tables(void) if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) { printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n"); } - printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", + printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { unsigned long new_rom_table_end = smbios_write_tables(rom_table_end); @@ -238,13 +238,13 @@ struct lb_memory *write_tables(void) __func__, new_high_table_pointer - high_table_pointer); - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { /* The coreboot table must be in 0-4K or 960K-1M */ rom_table_end = write_coreboot_table( - low_table_start, low_table_end, - rom_table_start, rom_table_end); + low_table_start, low_table_end, + rom_table_start, rom_table_end); } #if CONFIG_MULTIBOOT diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld index ea32837..e5a8498 100644 --- a/src/arch/x86/coreboot_ram.ld +++ b/src/arch/x86/coreboot_ram.ld @@ -15,7 +15,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */ @@ -101,13 +101,13 @@ SECTIONS } _ebss = .; - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 306f7da..6c24e24 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -34,7 +34,7 @@ #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "CORE " /* Must be exactly 6 bytes long! */ -#define ASLC "CORE" /* Must be exactly 4 bytes long! */ +#define ASLC "CORE" /* Must be exactly 4 bytes long! */ /* RSDP (Root System Description Pointer) */ typedef struct acpi_rsdp { @@ -64,9 +64,9 @@ typedef struct acpi_gen_regaddr { } __attribute__ ((packed)) acpi_addr_t; #define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ #define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ #define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ @@ -74,7 +74,7 @@ typedef struct acpi_gen_regaddr { #define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ #define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ #define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ #define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ @@ -88,13 +88,13 @@ typedef struct acpi_gen_regaddr { /* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ char asl_compiler_id[4]; /* ASL compiler vendor ID */ u32 asl_compiler_revision; /* ASL compiler revision number */ } __attribute__ ((packed)) acpi_header_t; @@ -491,7 +491,7 @@ unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); unsigned long acpi_fill_slit(unsigned long current); unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id); + const char *oem_table_id); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); @@ -509,7 +509,7 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, @@ -519,7 +519,7 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat); @@ -533,10 +533,10 @@ void acpi_create_facs(acpi_facs_t *facs); void acpi_create_dmar(acpi_dmar_t *dmar); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u32 bar); + u16 segment, u32 bar); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, - u8 dev, u8 fn); + u8 dev, u8 fn); unsigned long acpi_fill_dmar(unsigned long); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3e50be4..e749908 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -131,15 +131,15 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_INVALID 0 #define X86_VENDOR_INTEL 1 #define X86_VENDOR_CYRIX 2 -#define X86_VENDOR_AMD 3 -#define X86_VENDOR_UMC 4 +#define X86_VENDOR_AMD 3 +#define X86_VENDOR_UMC 4 #define X86_VENDOR_NEXGEN 5 #define X86_VENDOR_CENTAUR 6 -#define X86_VENDOR_RISE 7 +#define X86_VENDOR_RISE 7 #define X86_VENDOR_TRANSMETA 8 -#define X86_VENDOR_NSC 9 -#define X86_VENDOR_SIS 10 -#define X86_VENDOR_ANY 0xfe +#define X86_VENDOR_NSC 9 +#define X86_VENDOR_SIS 10 +#define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff int cpu_phys_address_size(void); @@ -194,21 +194,21 @@ static inline unsigned long cpu_index(void) #ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { - uint8_t x86; /* CPU family */ - uint8_t x86_vendor; /* CPU vendor */ - uint8_t x86_model; - uint8_t x86_mask; + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; }; static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) { - c->x86 = (tfms >> 8) & 0xf; - c->x86_model = (tfms >> 4) & 0xf; - c->x86_mask = tfms & 0xf; - if (c->x86 == 0xf) - c->x86 += (tfms >> 20) & 0xff; - if (c->x86 >= 0x6) - c->x86_model += ((tfms >> 16) & 0xF) << 4; + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; } #endif diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 955d8e2..4f29bc6 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -170,26 +170,26 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui #if defined(__PRE_RAM__) || defined(__SMM__) static inline int log2(int value) { - unsigned int r = 0; - __asm__ volatile ( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; + unsigned int r = 0; + __asm__ volatile ( + "bsrl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; } static inline int log2f(int value) { - unsigned int r = 0; - __asm__ volatile ( - "bsfl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; + unsigned int r = 0; + __asm__ volatile ( + "bsfl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; } #endif @@ -197,15 +197,15 @@ static inline int log2f(int value) #ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF)) #define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) @@ -248,14 +248,14 @@ void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; } static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) @@ -274,17 +274,17 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus { pci_devfn_t dev, last; - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for(; dev <=last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for(; dev <=last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; } /* Generic functions for pnp devices */ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 63e1ac9..e5dea8f 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -38,9 +38,9 @@ uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); @@ -51,9 +51,9 @@ uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); @@ -64,9 +64,9 @@ void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); @@ -75,14 +75,14 @@ void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) static inline __attribute__((always_inline)) void pci_io_write_config16(pci_devfn_t dev, unsigned where, uint16_t value) { - unsigned addr; + unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); } static inline __attribute__((always_inline)) @@ -90,9 +90,9 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index e5e6195..49fdb9b 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -34,7 +34,7 @@ struct intel_mp_floating unsigned char mpf_feature1; /* Standard or configuration ? */ unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ #define MP_FEATURE_VIRTUALWIRE (1 << 7) -#define MP_FEATURE_PIC (0 << 7) +#define MP_FEATURE_PIC (0 << 7) unsigned char mpf_feature3; /* Unused (0) */ unsigned char mpf_feature4; /* Unused (0) */ unsigned char mpf_feature5; /* Unused (0) */ @@ -128,11 +128,11 @@ enum mp_irq_source_types { #define MP_IRQ_POLARITY_DEFAULT 0x0 #define MP_IRQ_POLARITY_HIGH 0x1 #define MP_IRQ_POLARITY_LOW 0x3 -#define MP_IRQ_POLARITY_MASK 0x3 +#define MP_IRQ_POLARITY_MASK 0x3 #define MP_IRQ_TRIGGER_DEFAULT 0x0 #define MP_IRQ_TRIGGER_EDGE 0x4 #define MP_IRQ_TRIGGER_LEVEL 0xc -#define MP_IRQ_TRIGGER_MASK 0xc +#define MP_IRQ_TRIGGER_MASK 0xc struct mpc_config_lintsrc @@ -186,7 +186,7 @@ struct mp_exten_system_address_space { unsigned char mpe_length; unsigned char mpe_busid; unsigned char mpe_address_type; -#define ADDRESS_TYPE_IO 0 +#define ADDRESS_TYPE_IO 0 #define ADDRESS_TYPE_MEM 1 #define ADDRESS_TYPE_PREFETCH 2 unsigned int mpe_address_base_low; diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index c491f4b..7bfb844 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -8,14 +8,14 @@ #endif /* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed char int8_t; -typedef unsigned short uint16_t; -typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed short int16_t; -typedef unsigned int uint32_t; -typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef signed int int32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint64_t; @@ -23,14 +23,14 @@ typedef signed long long int64_t; #endif /* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t; -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t; -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_least64_t; @@ -38,14 +38,14 @@ typedef signed long long int_least64_t; #endif /* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t; -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t; -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; @@ -53,15 +53,15 @@ typedef signed long long int_fast64_t; #endif /* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef int intptr_t; +typedef unsigned int uintptr_t; /* Largest integral types */ #if __HAVE_LONG_LONG__ -typedef long long int intmax_t; +typedef long long int intmax_t; typedef unsigned long long uintmax_t; #else -typedef long int intmax_t; +typedef long int intmax_t; typedef unsigned long int uintmax_t; #endif diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 01ffa7c..27ff6b7 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -42,7 +42,7 @@ _start: leal _stack, %edi movl $_estack, %ecx subl %edi, %ecx - shrl $2, %ecx /* it is 32 bit aligned, right? */ + shrl $2, %ecx /* it is 32 bit aligned, right? */ movl $0xDEADBEEF, %eax rep stosl @@ -293,12 +293,12 @@ gdt: /* The next two entries are used for executing VGA option ROMs */ /* selgdt 0x28 16 bit 64k code at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x9a, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x9a, 0, 0 /* selgdt 0x30 16 bit 64k data at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x92, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x92, 0, 0 /* The next two entries are used for ACPI S3 RESUME */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 4a3bd96..2526306 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -92,30 +92,30 @@ static struct { int vendor; const char *name; } x86_vendors[] = { - { X86_VENDOR_INTEL, "GenuineIntel", }, - { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, - { X86_VENDOR_UMC, "UMC UMC UMC ", }, - { X86_VENDOR_NEXGEN, "NexGenDriven", }, - { X86_VENDOR_CENTAUR, "CentaurHauls", }, - { X86_VENDOR_RISE, "RiseRiseRise", }, - { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, - { X86_VENDOR_NSC, "Geode by NSC", }, - { X86_VENDOR_SIS, "SiS SiS SiS ", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, }; static const char *x86_vendor_name[] = { - [X86_VENDOR_INTEL] = "Intel", - [X86_VENDOR_CYRIX] = "Cyrix", - [X86_VENDOR_AMD] = "AMD", - [X86_VENDOR_UMC] = "UMC", - [X86_VENDOR_NEXGEN] = "NexGen", - [X86_VENDOR_CENTAUR] = "Centaur", - [X86_VENDOR_RISE] = "Rise", + [X86_VENDOR_INTEL] = "Intel", + [X86_VENDOR_CYRIX] = "Cyrix", + [X86_VENDOR_AMD] = "AMD", + [X86_VENDOR_UMC] = "UMC", + [X86_VENDOR_NEXGEN] = "NexGen", + [X86_VENDOR_CENTAUR] = "Centaur", + [X86_VENDOR_RISE] = "Rise", [X86_VENDOR_TRANSMETA] = "Transmeta", - [X86_VENDOR_NSC] = "NSC", - [X86_VENDOR_SIS] = "SiS", + [X86_VENDOR_NSC] = "NSC", + [X86_VENDOR_SIS] = "SiS", }; static const char *cpu_vendor_name(int vendor) @@ -178,7 +178,7 @@ static void identify_cpu(struct device *cpu) int cpuid_level; struct cpuid_result result; result = cpuid(0x00000000); - cpuid_level = result.eax; + cpuid_level = result.eax; vendor_name[ 0] = (result.ebx >> 0) & 0xff; vendor_name[ 1] = (result.ebx >> 8) & 0xff; vendor_name[ 2] = (result.ebx >> 16) & 0xff; diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..0216911 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -17,152 +17,152 @@ enum regnames { static uint32_t gdb_stub_registers[NUM_REGS]; -#define GDB_SIG0 0 /* Signal 0 */ -#define GDB_SIGHUP 1 /* Hangup */ -#define GDB_SIGINT 2 /* Interrupt */ -#define GDB_SIGQUIT 3 /* Quit */ -#define GDB_SIGILL 4 /* Illegal instruction */ -#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ -#define GDB_SIGABRT 6 /* Aborted */ -#define GDB_SIGEMT 7 /* Emulation trap */ -#define GDB_SIGFPE 8 /* Arithmetic exception */ -#define GDB_SIGKILL 9 /* Killed */ -#define GDB_SIGBUS 10 /* Bus error */ -#define GDB_SIGSEGV 11 /* Segmentation fault */ -#define GDB_SIGSYS 12 /* Bad system call */ -#define GDB_SIGPIPE 13 /* Broken pipe */ -#define GDB_SIGALRM 14 /* Alarm clock */ -#define GDB_SIGTERM 15 /* Terminated */ -#define GDB_SIGURG 16 /* Urgent I/O condition */ -#define GDB_SIGSTOP 17 /* Stopped (signal) */ -#define GDB_SIGTSTP 18 /* Stopped (user) */ -#define GDB_SIGCONT 19 /* Continued */ -#define GDB_SIGCHLD 20 /* Child status changed */ -#define GDB_SIGTTIN 21 /* Stopped (tty input) */ -#define GDB_SIGTTOU 22 /* Stopped (tty output) */ -#define GDB_SIGIO 23 /* I/O possible */ -#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ -#define GDB_SIGXFSZ 25 /* File size limit exceeded */ -#define GDB_SIGVTALRM 26 /* Virtual timer expired */ -#define GDB_SIGPROF 27 /* Profiling timer expired */ -#define GDB_SIGWINCH 28 /* Window size changed */ -#define GDB_SIGLOST 29 /* Resource lost */ -#define GDB_SIGUSR1 30 /* User defined signal 1 */ -#define GDB_SUGUSR2 31 /* User defined signal 2 */ -#define GDB_SIGPWR 32 /* Power fail/restart */ -#define GDB_SIGPOLL 33 /* Pollable event occurred */ -#define GDB_SIGWIND 34 /* SIGWIND */ -#define GDB_SIGPHONE 35 /* SIGPHONE */ -#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ -#define GDB_SIGLWP 37 /* Signal LWP */ -#define GDB_SIGDANGER 38 /* Swap space dangerously low */ -#define GDB_SIGGRANT 39 /* Monitor mode granted */ -#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ -#define GDB_SIGMSG 41 /* Monitor mode data available */ -#define GDB_SIGSOUND 42 /* Sound completed */ -#define GDB_SIGSAK 43 /* Secure attention */ -#define GDB_SIGPRIO 44 /* SIGPRIO */ - -#define GDB_SIG33 45 /* Real-time event 33 */ -#define GDB_SIG34 46 /* Real-time event 34 */ -#define GDB_SIG35 47 /* Real-time event 35 */ -#define GDB_SIG36 48 /* Real-time event 36 */ -#define GDB_SIG37 49 /* Real-time event 37 */ -#define GDB_SIG38 50 /* Real-time event 38 */ -#define GDB_SIG39 51 /* Real-time event 39 */ -#define GDB_SIG40 52 /* Real-time event 40 */ -#define GDB_SIG41 53 /* Real-time event 41 */ -#define GDB_SIG42 54 /* Real-time event 42 */ -#define GDB_SIG43 55 /* Real-time event 43 */ -#define GDB_SIG44 56 /* Real-time event 44 */ -#define GDB_SIG45 57 /* Real-time event 45 */ -#define GDB_SIG46 58 /* Real-time event 46 */ -#define GDB_SIG47 59 /* Real-time event 47 */ -#define GDB_SIG48 60 /* Real-time event 48 */ -#define GDB_SIG49 61 /* Real-time event 49 */ -#define GDB_SIG50 62 /* Real-time event 50 */ -#define GDB_SIG51 63 /* Real-time event 51 */ -#define GDB_SIG52 64 /* Real-time event 52 */ -#define GDB_SIG53 65 /* Real-time event 53 */ -#define GDB_SIG54 66 /* Real-time event 54 */ -#define GDB_SIG55 67 /* Real-time event 55 */ -#define GDB_SIG56 68 /* Real-time event 56 */ -#define GDB_SIG57 69 /* Real-time event 57 */ -#define GDB_SIG58 70 /* Real-time event 58 */ -#define GDB_SIG59 71 /* Real-time event 59 */ -#define GDB_SIG60 72 /* Real-time event 60 */ -#define GDB_SIG61 73 /* Real-time event 61 */ -#define GDB_SIG62 74 /* Real-time event 62 */ -#define GDB_SIG63 75 /* Real-time event 63 */ -#define GDB_SIGCANCEL 76 /* LWP internal signal */ -#define GDB_SIG32 77 /* Real-time event 32 */ -#define GDB_SIG64 78 /* Real-time event 64 */ -#define GDB_SIG65 79 /* Real-time event 65 */ -#define GDB_SIG66 80 /* Real-time event 66 */ -#define GDB_SIG67 81 /* Real-time event 67 */ -#define GDB_SIG68 82 /* Real-time event 68 */ -#define GDB_SIG69 83 /* Real-time event 69 */ -#define GDB_SIG70 84 /* Real-time event 70 */ -#define GDB_SIG71 85 /* Real-time event 71 */ -#define GDB_SIG72 86 /* Real-time event 72 */ -#define GDB_SIG73 87 /* Real-time event 73 */ -#define GDB_SIG74 88 /* Real-time event 74 */ -#define GDB_SIG75 89 /* Real-time event 75 */ -#define GDB_SIG76 90 /* Real-time event 76 */ -#define GDB_SIG77 91 /* Real-time event 77 */ -#define GDB_SIG78 92 /* Real-time event 78 */ -#define GDB_SIG79 93 /* Real-time event 79 */ -#define GDB_SIG80 94 /* Real-time event 80 */ -#define GDB_SIG81 95 /* Real-time event 81 */ -#define GDB_SIG82 96 /* Real-time event 82 */ -#define GDB_SIG83 97 /* Real-time event 83 */ -#define GDB_SIG84 98 /* Real-time event 84 */ -#define GDB_SIG85 99 /* Real-time event 85 */ -#define GDB_SIG86 100 /* Real-time event 86 */ -#define GDB_SIG87 101 /* Real-time event 87 */ -#define GDB_SIG88 102 /* Real-time event 88 */ -#define GDB_SIG89 103 /* Real-time event 89 */ -#define GDB_SIG90 104 /* Real-time event 90 */ -#define GDB_SIG91 105 /* Real-time event 91 */ -#define GDB_SIG92 106 /* Real-time event 92 */ -#define GDB_SIG93 107 /* Real-time event 93 */ -#define GDB_SIG94 108 /* Real-time event 94 */ -#define GDB_SIG95 109 /* Real-time event 95 */ -#define GDB_SIG96 110 /* Real-time event 96 */ -#define GDB_SIG97 111 /* Real-time event 97 */ -#define GDB_SIG98 112 /* Real-time event 98 */ -#define GDB_SIG99 113 /* Real-time event 99 */ -#define GDB_SIG100 114 /* Real-time event 100 */ -#define GDB_SIG101 115 /* Real-time event 101 */ -#define GDB_SIG102 116 /* Real-time event 102 */ -#define GDB_SIG103 117 /* Real-time event 103 */ -#define GDB_SIG104 118 /* Real-time event 104 */ -#define GDB_SIG105 119 /* Real-time event 105 */ -#define GDB_SIG106 120 /* Real-time event 106 */ -#define GDB_SIG107 121 /* Real-time event 107 */ -#define GDB_SIG108 122 /* Real-time event 108 */ -#define GDB_SIG109 123 /* Real-time event 109 */ -#define GDB_SIG110 124 /* Real-time event 110 */ -#define GDB_SIG111 125 /* Real-time event 111 */ -#define GDB_SIG112 126 /* Real-time event 112 */ -#define GDB_SIG113 127 /* Real-time event 113 */ -#define GDB_SIG114 128 /* Real-time event 114 */ -#define GDB_SIG115 129 /* Real-time event 115 */ -#define GDB_SIG116 130 /* Real-time event 116 */ -#define GDB_SIG117 131 /* Real-time event 117 */ -#define GDB_SIG118 132 /* Real-time event 118 */ -#define GDB_SIG119 133 /* Real-time event 119 */ -#define GDB_SIG120 134 /* Real-time event 120 */ -#define GDB_SIG121 135 /* Real-time event 121 */ -#define GDB_SIG122 136 /* Real-time event 122 */ -#define GDB_SIG123 137 /* Real-time event 123 */ -#define GDB_SIG124 138 /* Real-time event 124 */ -#define GDB_SIG125 139 /* Real-time event 125 */ -#define GDB_SIG126 140 /* Real-time event 126 */ -#define GDB_SIG127 141 /* Real-time event 127 */ -#define GDB_SIGINFO 142 /* Information request */ -#define GDB_UNKNOWN 143 /* Unknown signal */ -#define GDB_DEFAULT 144 /* error: default signal */ +#define GDB_SIG0 0 /* Signal 0 */ +#define GDB_SIGHUP 1 /* Hangup */ +#define GDB_SIGINT 2 /* Interrupt */ +#define GDB_SIGQUIT 3 /* Quit */ +#define GDB_SIGILL 4 /* Illegal instruction */ +#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ +#define GDB_SIGABRT 6 /* Aborted */ +#define GDB_SIGEMT 7 /* Emulation trap */ +#define GDB_SIGFPE 8 /* Arithmetic exception */ +#define GDB_SIGKILL 9 /* Killed */ +#define GDB_SIGBUS 10 /* Bus error */ +#define GDB_SIGSEGV 11 /* Segmentation fault */ +#define GDB_SIGSYS 12 /* Bad system call */ +#define GDB_SIGPIPE 13 /* Broken pipe */ +#define GDB_SIGALRM 14 /* Alarm clock */ +#define GDB_SIGTERM 15 /* Terminated */ +#define GDB_SIGURG 16 /* Urgent I/O condition */ +#define GDB_SIGSTOP 17 /* Stopped (signal) */ +#define GDB_SIGTSTP 18 /* Stopped (user) */ +#define GDB_SIGCONT 19 /* Continued */ +#define GDB_SIGCHLD 20 /* Child status changed */ +#define GDB_SIGTTIN 21 /* Stopped (tty input) */ +#define GDB_SIGTTOU 22 /* Stopped (tty output) */ +#define GDB_SIGIO 23 /* I/O possible */ +#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ +#define GDB_SIGXFSZ 25 /* File size limit exceeded */ +#define GDB_SIGVTALRM 26 /* Virtual timer expired */ +#define GDB_SIGPROF 27 /* Profiling timer expired */ +#define GDB_SIGWINCH 28 /* Window size changed */ +#define GDB_SIGLOST 29 /* Resource lost */ +#define GDB_SIGUSR1 30 /* User defined signal 1 */ +#define GDB_SUGUSR2 31 /* User defined signal 2 */ +#define GDB_SIGPWR 32 /* Power fail/restart */ +#define GDB_SIGPOLL 33 /* Pollable event occurred */ +#define GDB_SIGWIND 34 /* SIGWIND */ +#define GDB_SIGPHONE 35 /* SIGPHONE */ +#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ +#define GDB_SIGLWP 37 /* Signal LWP */ +#define GDB_SIGDANGER 38 /* Swap space dangerously low */ +#define GDB_SIGGRANT 39 /* Monitor mode granted */ +#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ +#define GDB_SIGMSG 41 /* Monitor mode data available */ +#define GDB_SIGSOUND 42 /* Sound completed */ +#define GDB_SIGSAK 43 /* Secure attention */ +#define GDB_SIGPRIO 44 /* SIGPRIO */ + +#define GDB_SIG33 45 /* Real-time event 33 */ +#define GDB_SIG34 46 /* Real-time event 34 */ +#define GDB_SIG35 47 /* Real-time event 35 */ +#define GDB_SIG36 48 /* Real-time event 36 */ +#define GDB_SIG37 49 /* Real-time event 37 */ +#define GDB_SIG38 50 /* Real-time event 38 */ +#define GDB_SIG39 51 /* Real-time event 39 */ +#define GDB_SIG40 52 /* Real-time event 40 */ +#define GDB_SIG41 53 /* Real-time event 41 */ +#define GDB_SIG42 54 /* Real-time event 42 */ +#define GDB_SIG43 55 /* Real-time event 43 */ +#define GDB_SIG44 56 /* Real-time event 44 */ +#define GDB_SIG45 57 /* Real-time event 45 */ +#define GDB_SIG46 58 /* Real-time event 46 */ +#define GDB_SIG47 59 /* Real-time event 47 */ +#define GDB_SIG48 60 /* Real-time event 48 */ +#define GDB_SIG49 61 /* Real-time event 49 */ +#define GDB_SIG50 62 /* Real-time event 50 */ +#define GDB_SIG51 63 /* Real-time event 51 */ +#define GDB_SIG52 64 /* Real-time event 52 */ +#define GDB_SIG53 65 /* Real-time event 53 */ +#define GDB_SIG54 66 /* Real-time event 54 */ +#define GDB_SIG55 67 /* Real-time event 55 */ +#define GDB_SIG56 68 /* Real-time event 56 */ +#define GDB_SIG57 69 /* Real-time event 57 */ +#define GDB_SIG58 70 /* Real-time event 58 */ +#define GDB_SIG59 71 /* Real-time event 59 */ +#define GDB_SIG60 72 /* Real-time event 60 */ +#define GDB_SIG61 73 /* Real-time event 61 */ +#define GDB_SIG62 74 /* Real-time event 62 */ +#define GDB_SIG63 75 /* Real-time event 63 */ +#define GDB_SIGCANCEL 76 /* LWP internal signal */ +#define GDB_SIG32 77 /* Real-time event 32 */ +#define GDB_SIG64 78 /* Real-time event 64 */ +#define GDB_SIG65 79 /* Real-time event 65 */ +#define GDB_SIG66 80 /* Real-time event 66 */ +#define GDB_SIG67 81 /* Real-time event 67 */ +#define GDB_SIG68 82 /* Real-time event 68 */ +#define GDB_SIG69 83 /* Real-time event 69 */ +#define GDB_SIG70 84 /* Real-time event 70 */ +#define GDB_SIG71 85 /* Real-time event 71 */ +#define GDB_SIG72 86 /* Real-time event 72 */ +#define GDB_SIG73 87 /* Real-time event 73 */ +#define GDB_SIG74 88 /* Real-time event 74 */ +#define GDB_SIG75 89 /* Real-time event 75 */ +#define GDB_SIG76 90 /* Real-time event 76 */ +#define GDB_SIG77 91 /* Real-time event 77 */ +#define GDB_SIG78 92 /* Real-time event 78 */ +#define GDB_SIG79 93 /* Real-time event 79 */ +#define GDB_SIG80 94 /* Real-time event 80 */ +#define GDB_SIG81 95 /* Real-time event 81 */ +#define GDB_SIG82 96 /* Real-time event 82 */ +#define GDB_SIG83 97 /* Real-time event 83 */ +#define GDB_SIG84 98 /* Real-time event 84 */ +#define GDB_SIG85 99 /* Real-time event 85 */ +#define GDB_SIG86 100 /* Real-time event 86 */ +#define GDB_SIG87 101 /* Real-time event 87 */ +#define GDB_SIG88 102 /* Real-time event 88 */ +#define GDB_SIG89 103 /* Real-time event 89 */ +#define GDB_SIG90 104 /* Real-time event 90 */ +#define GDB_SIG91 105 /* Real-time event 91 */ +#define GDB_SIG92 106 /* Real-time event 92 */ +#define GDB_SIG93 107 /* Real-time event 93 */ +#define GDB_SIG94 108 /* Real-time event 94 */ +#define GDB_SIG95 109 /* Real-time event 95 */ +#define GDB_SIG96 110 /* Real-time event 96 */ +#define GDB_SIG97 111 /* Real-time event 97 */ +#define GDB_SIG98 112 /* Real-time event 98 */ +#define GDB_SIG99 113 /* Real-time event 99 */ +#define GDB_SIG100 114 /* Real-time event 100 */ +#define GDB_SIG101 115 /* Real-time event 101 */ +#define GDB_SIG102 116 /* Real-time event 102 */ +#define GDB_SIG103 117 /* Real-time event 103 */ +#define GDB_SIG104 118 /* Real-time event 104 */ +#define GDB_SIG105 119 /* Real-time event 105 */ +#define GDB_SIG106 120 /* Real-time event 106 */ +#define GDB_SIG107 121 /* Real-time event 107 */ +#define GDB_SIG108 122 /* Real-time event 108 */ +#define GDB_SIG109 123 /* Real-time event 109 */ +#define GDB_SIG110 124 /* Real-time event 110 */ +#define GDB_SIG111 125 /* Real-time event 111 */ +#define GDB_SIG112 126 /* Real-time event 112 */ +#define GDB_SIG113 127 /* Real-time event 113 */ +#define GDB_SIG114 128 /* Real-time event 114 */ +#define GDB_SIG115 129 /* Real-time event 115 */ +#define GDB_SIG116 130 /* Real-time event 116 */ +#define GDB_SIG117 131 /* Real-time event 117 */ +#define GDB_SIG118 132 /* Real-time event 118 */ +#define GDB_SIG119 133 /* Real-time event 119 */ +#define GDB_SIG120 134 /* Real-time event 120 */ +#define GDB_SIG121 135 /* Real-time event 121 */ +#define GDB_SIG122 136 /* Real-time event 122 */ +#define GDB_SIG123 137 /* Real-time event 123 */ +#define GDB_SIG124 138 /* Real-time event 124 */ +#define GDB_SIG125 139 /* Real-time event 125 */ +#define GDB_SIG126 140 /* Real-time event 126 */ +#define GDB_SIG127 141 /* Real-time event 127 */ +#define GDB_SIGINFO 142 /* Information request */ +#define GDB_UNKNOWN 143 /* Unknown signal */ +#define GDB_DEFAULT 144 /* error: default signal */ /* Mach exceptions */ #define GDB_EXC_BAD_ACCESS 145 /* Could not access memory */ #define GDB_EXC_BAD_INSTRCTION 146 /* Illegal instruction/operand */ @@ -404,8 +404,8 @@ void x86_exception(struct eregs *info) case 'G': /* set the value of the CPU registers - return OK */ copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers)); memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); - info->eip = gdb_stub_registers[PC]; - info->cs = gdb_stub_registers[CS]; + info->eip = gdb_stub_registers[PC]; + info->cs = gdb_stub_registers[CS]; info->eflags = gdb_stub_registers[PS]; memcpy(out_buffer, "OK",3); break; @@ -436,8 +436,8 @@ void x86_exception(struct eregs *info) break; case 's': case 'c': - /* cAA..AA Continue at address AA..AA(optional) */ - /* sAA..AA Step one instruction from AA..AA(optional) */ + /* cAA..AA Continue at address AA..AA(optional) */ + /* sAA..AA Step one instruction from AA..AA(optional) */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr)) { info->eip = addr; diff --git a/src/arch/x86/lib/id.inc b/src/arch/x86/lib/id.inc index f8aba0b..389edd8 100644 --- a/src/arch/x86/lib/id.inc +++ b/src/arch/x86/lib/id.inc @@ -11,7 +11,7 @@ part: .long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end __id_end: diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 7fb25ba..93500f3 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -65,7 +65,7 @@ void clear_ioapic(u32 ioapic_base) io_apic_write(ioapic_base, i * 2 + 0x11, high); printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); + i, high, low); } if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { @@ -80,9 +80,9 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) int i; printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); + ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + bsp_lapicid); if (ioapic_id) { printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); @@ -95,7 +95,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); for (i = 0; i < 3; i++) printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); + io_apic_read(ioapic_base, i)); } @@ -114,7 +114,7 @@ static void load_vectors(u32 ioapic_base) */ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); + io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); @@ -134,7 +134,7 @@ static void load_vectors(u32 ioapic_base) } printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - 0, high, low); + 0, high, low); low = DISABLED; high = NONE; for (i = 1; i < ioapic_interrupts; i++) { @@ -142,7 +142,7 @@ static void load_vectors(u32 ioapic_base) io_apic_write(ioapic_base, i * 2 + 0x11, high); printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); + i, high, low); } } diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c index 77df4b3..7402c7e 100644 --- a/src/arch/x86/lib/pci_ops_conf1.c +++ b/src/arch/x86/lib/pci_ops_conf1.c @@ -18,7 +18,7 @@ #endif static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, - int where) + int where) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); return inb(0xCFC + (where & 3)); @@ -39,21 +39,21 @@ static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, } static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, uint8_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outb(value, 0xCFC + (where & 3)); } static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, uint16_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outw(value, 0xCFC + (where & 2)); } static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, uint32_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(value, 0xCFC); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4eaf297..1ab069d 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -16,7 +16,7 @@ ((WHERE) & 0xFFF)) static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, - int where) + int where) { return (read8(PCI_MMIO_ADDR(bus, devfn, where))); } @@ -34,19 +34,19 @@ static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, } static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, uint8_t value) { write8(PCI_MMIO_ADDR(bus, devfn, where), value); } static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, uint16_t value) { write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); } static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, uint32_t value) { write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); } diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c index ed2122c..0fd3251 100644 --- a/src/arch/x86/lib/rom_media.c +++ b/src/arch/x86/lib/rom_media.c @@ -85,7 +85,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { #if defined(CONFIG_ROM_SIZE) if (CONFIG_ROM_SIZE != romsize) printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_ROM_SIZE, romsize); + CONFIG_ROM_SIZE, romsize); #endif } media->open = x86_rom_open; diff --git a/src/arch/x86/lib/thread.c b/src/arch/x86/lib/thread.c index 06f8a15..36f2fd7 100644 --- a/src/arch/x86/lib/thread.c +++ b/src/arch/x86/lib/thread.c @@ -42,7 +42,7 @@ static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value) } void arch_prepare_thread(struct thread *t, - void asmlinkage (*thread_entry)(void *), void *arg) + void asmlinkage (*thread_entry)(void *), void *arg) { uintptr_t stack = t->stack_current; diff --git a/src/arch/x86/lib/thread_switch.S b/src/arch/x86/lib/thread_switch.S index 8de1948..61a3965 100644 --- a/src/arch/x86/lib/thread_switch.S +++ b/src/arch/x86/lib/thread_switch.S @@ -28,21 +28,21 @@ * +------------+ * | ret addr | <-- esp + 0x20 * +------------+ - * | eax | <-- esp + 0x1c + * | eax | <-- esp + 0x1c * +------------+ - * | ecx | <-- esp + 0x18 + * | ecx | <-- esp + 0x18 * +------------+ - * | edx | <-- esp + 0x14 + * | edx | <-- esp + 0x14 * +------------+ - * | ebx | <-- esp + 0x10 + * | ebx | <-- esp + 0x10 * +------------+ * | orig esp | <-- esp + 0x0c * +------------+ - * | ebp | <-- esp + 0x08 + * | ebp | <-- esp + 0x08 * +------------+ - * | esi | <-- esp + 0x04 + * | esi | <-- esp + 0x04 * +------------+ - * | edi | <-- esp + 0x00 + * | edi | <-- esp + 0x00 * +------------+ */ .globl switch_to_thread diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c index 2c43f5c..b2d42e6 100644 --- a/src/console/cbmem_console.c +++ b/src/console/cbmem_console.c @@ -30,6 +30,6 @@ static void cbmemc_tx_byte_(unsigned char data) } static const struct console_driver cbmem_console __console = { - .init = cbmemc_init_, + .init = cbmemc_init_, .tx_byte = cbmemc_tx_byte_, }; diff --git a/src/console/console.c b/src/console/console.c index 39a30b5..fe9ef3f 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -97,7 +97,7 @@ int console_tst_byte(void) return 0; } -#else // __PRE_RAM__ ^^^ NOT defined vvv defined +#else // __PRE_RAM__ ^^^ NOT defined vvv defined void console_init(void) { diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c index a76791d..fb1dd48 100644 --- a/src/console/logbuf_console.c +++ b/src/console/logbuf_console.c @@ -14,7 +14,7 @@ static void logbuf_tx_byte(unsigned char byte) } static const struct console_driver __console = { - .init = 0, + .init = 0, .tx_byte = logbuf_tx_byte, .rx_byte = 0, .tst_byte = 0, diff --git a/src/console/post.c b/src/console/post.c index 35cc0e8..35c92ba 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -87,7 +87,7 @@ void cmos_post_log(void) break; default: printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); + "in previous boot: 0x%02x\n", code); #if CONFIG_ELOG elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); #if CONFIG_CMOS_POST_EXTRA diff --git a/src/console/qemu_debugcon_console.c b/src/console/qemu_debugcon_console.c index 1d66d87..ee633e9 100644 --- a/src/console/qemu_debugcon_console.c +++ b/src/console/qemu_debugcon_console.c @@ -27,8 +27,8 @@ static void debugcon_init(void) { readback = inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", - (readback == 0xe9) ? "detected" : "not found", - CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); + (readback == 0xe9) ? "detected" : "not found", + CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); } static void debugcon_tx_byte(unsigned char data) diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c index 814a1ac..812cd2e 100644 --- a/src/console/spkmodem_console.c +++ b/src/console/spkmodem_console.c @@ -37,7 +37,7 @@ static int spkmodem_tst_byte(void) static const struct console_driver spkmodem_console __console = { - .init = spkmodem_init, + .init = spkmodem_init, .tx_byte = spkmodem_tx_byte, .tx_flush = spkmodem_tx_flush, .rx_byte = spkmodem_rx_byte, diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..f7dd64c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -47,7 +47,7 @@ static int ttyS0_tst_byte(void) } static const struct console_driver uart8250_console __console = { - .init = ttyS0_init, + .init = ttyS0_init, .tx_byte = ttyS0_tx_byte, .tx_flush = ttyS0_tx_flush, .rx_byte = ttyS0_rx_byte, diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..340e0b3 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -63,7 +63,7 @@ static int uartmem_tst_byte(void) } static const struct console_driver uart8250mem_console __console = { - .init = uartmem_init, + .init = uartmem_init, .tx_byte = uartmem_tx_byte, .tx_flush = uartmem_tx_flush, .rx_byte = uartmem_rx_byte, diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index 8df6417..d14ea70 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -53,7 +53,7 @@ static int dbgp_tst_byte(void) } static const struct console_driver usbdebug_direct_console __console = { - .init = dbgp_init, + .init = dbgp_init, .tx_byte = dbgp_tx_byte, .tx_flush = dbgp_tx_flush, .rx_byte = dbgp_rx_byte, diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index a860f67..b8dc0a9 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -34,13 +34,13 @@ endif # The --entry=0 is just here to suppress the LD warning. It does not affect the # final microcode file. $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) - @printf " LD $(subst $(obj)/,,$(@))\n" + @printf " LD $(subst $(obj)/,,$(@))\n" $(LD) -static --entry=0 $< -o $@ # We have a lot of useless data in the large blob, and we are only interested in # the data section, so we only copy that part to the final microcode file $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o - @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@ ifeq ($(cbfs_include_ucode),y) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..c9006ef 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -50,11 +50,11 @@ config HAVE_INIT_TIMER default y config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code. endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 899a3c4..e929593 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -100,14 +100,14 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ { 0, 0 }, }; static const struct cpu_driver model_10 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 10d64dd..26b5d20 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -6,13 +6,13 @@ # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. +# notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. # * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED @@ -32,7 +32,7 @@ ramstage-y += model_12_init.c AGESA_ROOT = ../../../../vendorcode/amd/agesa/f12 -agesa_lib_src = $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src = $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 0dae912..fde555e 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -106,14 +106,14 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */ - { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */ - { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */ - { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */ + { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */ + { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */ + { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */ + { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */ { 0, 0 }, }; static const struct cpu_driver model_12 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 7ae2b24..f3aa6b4 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -126,14 +126,14 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..63b7656 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -71,11 +71,11 @@ config HAVE_INIT_TIMER default y config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code. endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index ea7e663..19a2550 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -107,21 +107,21 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ - { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ - { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ - { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ - { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ { 0, 0 }, }; static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index aebc27b..2baee00 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -128,6 +128,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2964b78..041f841 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -128,6 +128,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ef19b53..223c323 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -118,7 +118,7 @@ inline void *backup_resume(void) if (((u32) resume_backup_memory == 0) || ((u32) resume_backup_memory == -1)) { printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", - (u32) resume_backup_memory); + (u32) resume_backup_memory); for (;;) ; } @@ -135,8 +135,8 @@ void move_stack_high_mem(void) __asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); + (high_stack - BSP_STACK_BASE_ADDR) + :); } #ifndef __PRE_RAM__ diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 5ee4f38..f0d2e28 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -35,8 +35,8 @@ #endif typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile ///< Volatile Data Type + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type } S3_DATA_TYPE; void restore_mtrr(void); diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..575eca9 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -194,7 +194,7 @@ clear_fixed_var_mtrr_out: * 0x06 is the WB IO type for a given 4k segment. * 0x1e is the MEM IO type for a given 4k segment (K10 and above). * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. + * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..7ea4d22 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -85,7 +85,7 @@ static void post_cache_as_ram(void) /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ unsigned v_esp; __asm__ volatile ( - "movl %%esp, %0\n\t" + "movl %%esp, %0\n\t" : "=a" (v_esp) ); print_debug_pcar("v_esp=", v_esp); @@ -115,7 +115,7 @@ static void post_cache_as_ram(void) __asm__ volatile ( /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%esp\n\t" + "subl %0, %%esp\n\t" ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) /* discard all registers (eax is used for %0), so gcc redoes everything after the stack is moved */ diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index b3df0a3..fb85e8e 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -38,17 +38,17 @@ static int get_max_siblings(int nodes) static void enable_apic_ext_id(int nodes) { - device_t dev; - int nodeid; - - //enable APIC_EXIT_ID all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ - uint32_t val; - dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); - val = pci_read_config32(dev, 0x68); + device_t dev; + int nodeid; + + //enable APIC_EXIT_ID all the nodes + for(nodeid=0; nodeid<nodes; nodeid++){ + uint32_t val; + dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); + val = pci_read_config32(dev, 0x68); val |= (1<<17)|(1<<18); pci_write_config32(dev, 0x68, val); - } + } } @@ -59,13 +59,13 @@ unsigned get_apicid_base(unsigned ioapic_num) unsigned apicid_base; int siblings; unsigned nb_cfg_54; - int bsp_apic_id = lapicid(); // bsp apicid + int bsp_apic_id = lapicid(); // bsp apicid - get_option(&disable_siblings, "multi_core"); + get_option(&disable_siblings, "multi_core"); - //get the nodes number - dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; + //get the nodes number + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; siblings = get_max_siblings(nodes); @@ -98,9 +98,9 @@ unsigned get_apicid_base(unsigned ioapic_num) and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */ - //4:10 for two way 8:12 for four way 16:16 for eight way + //4:10 for two way 8:12 for four way 16:16 for eight way //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; + apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; } else { diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 69ce56a..7404625 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -18,16 +18,16 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { #if !CONFIG_K8_REV_F_SUPPORT - if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set + if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif - // set the NB_CFG[54]=1; why the OS will be happy with that ??? - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); + // set the NB_CFG[54]=1; why the OS will be happy with that ??? + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo + wrmsr(NB_CFG_MSR, msr); - return 1; + return 1; } static inline void real_start_other_core(unsigned nodeid) @@ -53,9 +53,9 @@ static inline void start_other_cores(void) return; // disable multi_core } - nodes = get_nodes(); + nodes = get_nodes(); - for(nodeid=0; nodeid<nodes; nodeid++) { + for(nodeid=0; nodeid<nodes; nodeid++) { if( get_core_num_in_bsp(nodeid) > 0) { real_start_other_core(nodeid); } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 5674c49..5924bd8 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -9,9 +9,9 @@ //called by bus_cpu_scan too unsigned int read_nb_cfg_54(void) { - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return ( ( msr.hi >> (54-32)) & 1); + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return ( ( msr.hi >> (54-32)) & 1); } u32 get_initial_apicid(void) @@ -27,17 +27,17 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) struct node_core_id id; // get the apicid via cpuid(1) ebx[27:24] if( nb_cfg_54) { - // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] - id.coreid = (cpuid_ebx(1) >> 24) & 0xf; - id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<<CORE_ID_BIT)-1); - } + // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] + id.coreid = (cpuid_ebx(1) >> 24) & 0xf; + id.nodeid = (id.coreid>>CORE_ID_BIT); + id.coreid &= ((1<<CORE_ID_BIT)-1); + } else { - // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] - id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; - id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1<<NODE_ID_BIT)-1); + // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] + id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; + id.coreid = (id.nodeid>>NODE_ID_BIT); + id.nodeid &= ((1<<NODE_ID_BIT)-1); } return id; } diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..7e3849c 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -39,7 +39,7 @@ /***************************************************************************/ DCacheSetup: /* Save the BIST result */ - movl %eax, %ebx + movl %eax, %ebx invd /* set cache properties */ @@ -165,22 +165,22 @@ done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi cld rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi + pop %esi + pop %edi /* Clear the cache out to ram */ wbinvd /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 __main: post_code(POST_PREPARE_RAMSTAGE) diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..9441934 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -36,7 +36,7 @@ /***************************************************************************/ DCacheSetup: /* Save the BIST result */ - movl %eax, %ebx + movl %eax, %ebx invd /* set cache properties */ @@ -189,24 +189,24 @@ DCacheSetupGood: call main done_cache_as_ram_main: - /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi /* Clear the cache out to ram */ wbinvd - /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 __main: post_code(POST_PREPARE_RAMSTAGE) diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c index 30d9595..2d2c1c8 100644 --- a/src/cpu/amd/geode_lx/cpureginit.c +++ b/src/cpu/amd/geode_lx/cpureginit.c @@ -49,15 +49,15 @@ static const struct delay_controls { u32 fast_hi; u32 fast_low; } delay_control_table[] = { - /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ - { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, - { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, - { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, - { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, - { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, - { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, + /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ + { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, + { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, + { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, + { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, + { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, + { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, }; /* @@ -120,7 +120,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated) /* Delay Controls based on DIMM loading. UGH! * Number of devices = module width (SPD 6) / device width (SPD 13) - * * physical banks (SPD 5) + * * physical banks (SPD 5) * * Note: We only support a module width of 64. */ @@ -180,7 +180,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) msr_t msr; /* Castle 2.0 BTM periodic sync period. */ - /* [40:37] 1 sync record per 256 bytes */ + /* [40:37] 1 sync record per 256 bytes */ print_debug("Castle 2.0 BTM periodic sync period.\n"); msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index 3d33dda..29edf93 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -210,14 +210,14 @@ static const struct { { 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, - [27] NbMcaToMstCpuEn = 1, - [25] DisPciCfgCpuErrRsp = 1, - [21] SyncOnAnyErrEn = 1, - [20] SyncOnWDTEn = 1, - [6] CpuErrDis = 1, - [4] SyncPktPropDis = 1, - [3] SyncPktGenDis = 1, - [2] SyncOnUcEccEn = 1 */ + [27] NbMcaToMstCpuEn = 1, + [25] DisPciCfgCpuErrRsp = 1, + [21] SyncOnAnyErrEn = 1, + [20] SyncOnWDTEn = 1, + [6] CpuErrDis = 1, + [4] SyncPktPropDis = 1, + [3] SyncPktGenDis = 1, + [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL, @@ -306,12 +306,12 @@ static const struct { /* Extended NB MCA Config Register */ { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, - [9] SyncOnUncNbAryEn = 1 , - [8] SyncOnProtEn = 1, - [7] SyncFloodOnTgtAbtErr = 1, - [6] SyncFloodOnDatErr = 1, - [5] DisPciCfgCpuMstAbtRsp = 1, - [1] SyncFloodOnUsPwDataErr = 1 */ + [9] SyncOnUncNbAryEn = 1 , + [8] SyncOnProtEn = 1, + [7] SyncFloodOnTgtAbtErr = 1, + [6] SyncFloodOnDatErr = 1, + [5] DisPciCfgCpuMstAbtRsp = 1, + [1] SyncFloodOnUsPwDataErr = 1 */ /* errata 346 - Fam10 C2, C3 * System software should set F3x188[22] to 1b. */ @@ -444,11 +444,11 @@ static const struct { { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + completeness */ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + completeness */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ @@ -459,19 +459,19 @@ static const struct { /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ + [21:14] LfcMin = 10h */ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ + [21:14] LfcMin = 10h */ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ + [21:14] LfcMin = 08h */ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ + [21:14] LfcMin = 08h */ { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4297c90..e93e9c8 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -31,15 +31,15 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 2.- COF/VID : 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply - fixPsNbVidBeforeWR(...) + fixPsNbVidBeforeWR(...) 2.4.2.9.1 Step 8 enable_fid_change - We do this for all nodes, I don't understand BKDG 100% on - whether this is or isn't meant by "on the local - processor". Must be OK. + We do this for all nodes, I don't understand BKDG 100% on + whether this is or isn't meant by "on the local + processor". Must be OK. 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ? 2.4.2.9.1 Steps 11-12 init_fidvid_stage2 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, - needs specific circuitry. + needs specific circuitry. 3.- 2.4.2.7 dualPlaneOnly(dev) @@ -52,12 +52,12 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 b) setVSRamp(), called from prep_fid_change c) prep_fid_change d) improperly, for lack of voltage regulator details?, - F3xA0[PsiVidEn] in defaults.h - F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change) + F3xA0[PsiVidEn] in defaults.h + F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change) 7.- TODO (Core Performance Boost is only available in revision E cpus, and we - don't seem to support those yet, at least they don't have any - constant in amddefs.h ) + don't seem to support those yet, at least they don't have any + constant in amddefs.h ) 8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required @@ -147,7 +147,7 @@ static void enable_fid_change(u8 fid) dword |= 1 << 5; // enable pci_write_config32(dev, 0xd4, dword); printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, - dword); + dword); } } @@ -161,7 +161,7 @@ static void applyBoostFIDOffset( device_t dev ) { msr_t msr = rdmsr(PS_REG_BASE); u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; - msr.lo &= ~PS_CPU_FID_MASK; + msr.lo &= ~PS_CPU_FID_MASK; msr.lo |= cpuFid ; wrmsr(PS_REG_BASE , msr); @@ -176,10 +176,10 @@ static void enableNbPState1( device_t dev ) { u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; u32 i; for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; msr.lo |= ( nbVid1 << NB_VID_POS); wrmsr(PS_REG_BASE + i, msr); } @@ -191,12 +191,12 @@ static void enableNbPState1( device_t dev ) { static u8 setPStateMaxVal( device_t dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_IDD_VALUE_MASK) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { msr.hi |= PS_EN_MASK ; wrmsr(PS_REG_BASE + i, msr); } - if (msr.hi | PS_EN_MASK) { + if (msr.hi | PS_EN_MASK) { maxpstate = i; } } @@ -217,15 +217,15 @@ static void dualPlaneOnly( device_t dev ) { if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ if (cpuid_edx(0x80000007) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068) ); - wrmsr(0xC0010068,minPstate); + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068) ); + wrmsr(0xC0010068,minPstate); } else { msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr ); + msr.lo=0; msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068) ); + wrmsr(0xC0010068, msr ); } //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? @@ -254,13 +254,13 @@ static int vidTo100uV(u8 vid) static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." - * (20 us) ? - * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ - u32 dword; + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." + * (20 us) ? + * Shouldn't it depend on the voltage regulators, mainboard + * or something ? + */ + u32 dword; dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; dword |= VSRAMP_VALUE; @@ -278,12 +278,12 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() + * (after set AMD MSRs and init ht ) */ - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid @@ -299,16 +299,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pviModeFlag = 0; /* Get P0's voltage */ - /* MSRC001_00[68:64] are not programmed yet when called from + /* MSRC001_00[68:64] are not programmed yet when called from prep_fid_change, one might use F4x1[F0:E0] instead, but theoretically MSRC001_00[68:64] are equal to them after reset. */ msr = rdmsr(0xC0010064); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { + if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) - >> PS_CPU_VID_SHFT) & 0x7F); + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) + >> PS_CPU_VID_SHFT) & 0x7F); } /* If SVI, we only care about CPU VID. @@ -327,15 +327,15 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue); lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { + if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue); - lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) - >> PS_CPU_VID_SHFT) & 0x7F); + lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) + >> PS_CPU_VID_SHFT) & 0x7F); } /* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU - * BKDG 2.4.1.7 (a) + * BKDG 2.4.1.7 (a) */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); @@ -351,7 +351,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) if (lowVoltageVid < bValue) lowVoltageVid = bValue; - u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ @@ -372,50 +372,50 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) } static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { - u8 link0isGen3 = 0; - u8 offset; - if (AMD_CpuFindCapability(node, 0, &offset)) { + u8 link0isGen3 = 0; + u8 offset; + if (AMD_CpuFindCapability(node, 0, &offset)) { link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + S1g3 in link Gen3 mode, but I don't know how to tell + package S1g3 from S1g4 */ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) - && link0isGen3) { + && link0isGen3) { return 5 ; /* divide clk by 128*/ - } else { + } else { return 4 ; /* divide clk by 16 */ - } + } } static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); - if (singleLinkFlag) { + if (singleLinkFlag) { /* - * PowerStepUp=01000b - 50nS + * PowerStepUp=01000b - 50nS * PowerStepDown=01000b - 50ns */ dword |= PW_STP_UP50 | PW_STP_DN50; } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; + u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + u32 isocEn = 0; + int j; for(j=0 ; (j<4) && (!isocEn) ; j++ ) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; } - } + } - if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { + if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b 2 cores - 200nS - 0010b @@ -439,7 +439,7 @@ static u32 power_up_down(int node, u8 procPkg) { } } } - return dword; + return dword; } static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { @@ -454,14 +454,14 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { * PowerStepDown= "platform dependent" * LinkPllLink=01b * ClkRampHystCtl=HW default - * ClkRampHystSel=1111b + * ClkRampHystSel=1111b */ - u32 dword= pci_read_config32(dev, 0xd4); + u32 dword= pci_read_config32(dev, 0xd4); dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; - dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT); + dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; + dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT); - dword |= power_up_down(node, procPkg); + dword |= power_up_down(node, procPkg); pci_write_config32(dev, 0xd4, dword); @@ -471,32 +471,32 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ - /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ + /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ dword &= VID_SLAM_OFF ; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword |= VID_SLAM_ON; - } - /* set the rest of A0 since we're at it... */ + } + /* set the rest of A0 since we're at it... */ - if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { dword |= NB_PSTATE_FORCE_ON; } // else should we clear it ? - if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { + if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { dword |= BP_INS_TRI_EN_ON ; } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG_SVI_HIGH_FREQ + #if CONFIG_SVI_HIGH_FREQ if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; - } - #endif + } + #endif pci_write_config32(dev, 0xA0, dword); } @@ -504,46 +504,46 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ + /* adjust FIFO between nb and core clocks to max allowed + values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; - u8 nbSynPtrAdj; + u8 nbSynPtrAdj; if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { nbSynPtrAdj = 5; } else { - nbSynPtrAdj = 6; + nbSynPtrAdj = 6; } u32 dword = pci_read_config32(dev, 0xDc); - dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword &= ~ NB_SYN_PTR_ADJ_MASK; dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; - /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); } static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ - u32 dword; + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + u32 dword; u32 c1= 1; - if (cpuRev & (AMD_DR_Bx)) { - // will coreboot ever enable cache scrubbing ? - // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? - dword = pci_read_config32(dev, 0x58); - u32 scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub + if (cpuRev & (AMD_DR_Bx)) { + // will coreboot ever enable cache scrubbing ? + // if it does, will it be enough to check the current state + // or should we configure for what we'll set up later ? + dword = pci_read_config32(dev, 0x58); + u32 scrubbingCache = dword & + ( (0x1F << 16) // DCacheScrub + | (0x1F << 8) ); // L2Scrub if (scrubbingCache) { - c1 = 0x80; + c1 = 0x80; } else { - c1 = 0xA0; + c1 = 0xA0; } } else { // rev C or later // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xDC); - u32 cacheFlushOnHalt = dword & (7 << 16); - if (!cacheFlushOnHalt) { + dword = pci_read_config32(dev, 0xDC); + u32 cacheFlushOnHalt = dword & (7 << 16); + if (!cacheFlushOnHalt) { c1 = 0x80; } } @@ -551,36 +551,36 @@ static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg pci_write_config32(dev, 0x84, dword); - /* FIXME: BKDG Table 100 says if the link is at a Gen1 + /* FIXME: BKDG Table 100 says if the link is at a Gen1 frequency and the chipset does not support a 10us minimum LDTSTOP assertion time, then { If ASB2 && SVI then smaf001 = F6h else smaf001=87h. } else ... I hardly know what it means or how to check it from here, so I bluntly assume it is false and code here the else, which is easier */ - u32 smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { + u32 smaf001 = 0xE6; + if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; - } else { - #if CONFIG_SVI_HIGH_FREQ - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; - } - #endif - } - u32 fidvidChange = 0; - if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) + } else { + #if CONFIG_SVI_HIGH_FREQ + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; + } + #endif + } + u32 fidvidChange = 0; + if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) || (cpuRev & AMD_RB_C3) ) { - fidvidChange=0x0B; - } + fidvidChange=0x0B; + } dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; + | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); } static void prep_fid_change(void) { - u32 dword; + u32 dword; u32 nodes; device_t dev; int i; @@ -592,20 +592,20 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); - u32 cpuRev = mctGetLogicalCPUID(0xFF) ; - u8 procPkg = mctGetProcessorPackageType(); + u32 cpuRev = mctGetLogicalCPUID(0xFF) ; + u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); - config_clk_power_ctrl_reg0(i,cpuRev,procPkg); + config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev,cpuRev,procPkg); + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev); - config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); + config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword); @@ -636,7 +636,7 @@ static void waitCurrentPstate(u32 target_pstate){ */ u32 corrected_timeout = ( (pstate_msr.lo==1) && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; + WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; msr_t timeout; timeout.lo = initial_msr.lo + corrected_timeout ; @@ -650,7 +650,7 @@ static void waitCurrentPstate(u32 target_pstate){ pstate_msr = rdmsr(CUR_PSTATE_MSR); tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); + || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; if (pstate_msr.lo != target_pstate) { @@ -673,7 +673,7 @@ static void set_pstate(u32 nonBoostedPState) { wrmsr(0xC0010062, msr); /* Wait for P0 to set. */ - waitCurrentPstate(nonBoostedPState); + waitCurrentPstate(nonBoostedPState); } @@ -709,15 +709,15 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) u8 startup_pstate; /* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. - * Read Pstate register pointed by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems + * Get StartupPstate from MSRC001_0071. + * Read Pstate register pointed by [StartupPstate]. + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. + * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems */ msr = rdmsr(0xc0010071); @@ -731,12 +731,12 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); - /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take - * synchronization between cores and we don't think - * PstatMaxVal is going to be 0 on cold reset anyway ? + /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = + * max(1,F3xDC[PstateMaxVal] ) because it would take + * synchronization between cores and we don't think + * PstatMaxVal is going to be 0 on cold reset anyway ? */ - if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); }; @@ -746,13 +746,13 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) if (pviMode) { /* single plane*/ UpdateSinglePlaneNbVid(); - } + } // Transition to P1 for all APs and P0 for core0. - set_pstate(1); + set_pstate(1); if (coreid == 0) { - set_pstate(0); + set_pstate(0); } /* missing step 7 (restore PstateMax to 0 if needed) because @@ -771,11 +771,11 @@ static u32 needs_NB_COF_VID_update(void) nodes = get_nodes(); nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - u32 cpuRev = mctGetLogicalCPUID(i) ; - u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); + u32 cpuRev = mctGetLogicalCPUID(i) ; + u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); if (nbCofVidUpdateDefined - && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) - & NB_COF_VID_UPDATE_MASK)) { + && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) + & NB_COF_VID_UPDATE_MASK)) { nb_cof_vid_update = 1; break; } @@ -801,11 +801,11 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; - if (!pvimode) { /* SVI, dual power plane */ - vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); + if (!pvimode) { /* SVI, dual power plane */ + vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); } /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ @@ -829,7 +829,7 @@ static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); - send = init_fidvid_core(nodeid,coreid); + send = init_fidvid_core(nodeid,coreid); send |= (apicid << 24); // ap apicid // Send signal to BSP about this AP max fid @@ -879,7 +879,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) if (timeout) { printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", - __func__, ap_apicid); + __func__, ap_apicid); return; } @@ -898,7 +898,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) u8 StartupPstate; /* BKDG 2.4.2.9.1 11-12 - * This function copies newNbVid to NbVid bits in P-state + * This function copies newNbVid to NbVid bits in P-state * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in * P-state Registers[4:0] if its IddValue!=0 in case of @@ -909,27 +909,27 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ( (msr.hi & PS_IDD_VALUE_MASK) - && (msr.hi & PS_EN_MASK) - &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { + if ( (msr.hi & PS_IDD_VALUE_MASK) + && (msr.hi & PS_EN_MASK) + &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { msr.lo &= PS_NB_VID_M_OFF; msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT; wrmsr(0xC0010064 + i, msr); } } - /* Not documented. Would overwrite Nb_Vids just copied - * should we just update cpu_vid or nothing at all ? + /* Not documented. Would overwrite Nb_Vids just copied + * should we just update cpu_vid or nothing at all ? */ if (pviMode) { //single plane - UpdateSinglePlaneNbVid(); + UpdateSinglePlaneNbVid(); } /* For each core in the system, transition all cores to StartupPstate */ msr = rdmsr(0xC0010071); StartupPstate = msr.hi & 0x07; /* Set and wait for StartupPstate to set. */ - set_pstate(StartupPstate); + set_pstate(StartupPstate); } @@ -979,9 +979,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); - dualPlaneOnly(dev); - applyBoostFIDOffset(dev); - enableNbPState1(dev); + dualPlaneOnly(dev); + applyBoostFIDOffset(dev); + enableNbPState1(dev); finalPstateChange(); diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index eb047b8..fd72881 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -165,8 +165,8 @@ void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { printk(BIOS_DEBUG, - "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, - apicid, id.nodeid, id.coreid); + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); } static u32 wait_cpu_state(u32 apicid, u32 state) @@ -308,7 +308,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) if (cpu_init_detectedx) { print_apicid_nodeid_coreid(apicid, id, - "\n\n\nINIT detected from "); + "\n\n\nINIT detected from "); printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); } @@ -339,13 +339,13 @@ static u32 init_cpus(u32 cpu_init_detectedx) // check warm(bios) reset to call stage2 otherwise do stage1 if (warm_reset_detect(id.nodeid)) { printk(BIOS_DEBUG, - "init_fidvid_stage2 apicid: %02x\n", - apicid); + "init_fidvid_stage2 apicid: %02x\n", + apicid); init_fidvid_stage2(apicid, id.nodeid); } else { printk(BIOS_DEBUG, - "init_fidvid_ap(stage1) apicid: %02x\n", - apicid); + "init_fidvid_ap(stage1) apicid: %02x\n", + apicid); init_fidvid_ap(apicid, id.nodeid, id.coreid); } } @@ -357,8 +357,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) STOP_CAR_AND_CPU(); printk(BIOS_DEBUG, - "\nAP %02x should be halted but you are reading this....\n", - apicid); + "\nAP %02x should be halted but you are reading this....\n", + apicid); } return bsp_apicid; @@ -480,7 +480,7 @@ static void AMD_Errata281(u8 node, u32 revision, u32 platform) if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { for (i = 0; i < nodes; i++) { if (mctGetLogicalCPUID(i) & - (AMD_DR_B0 | AMD_DR_B1)) { + (AMD_DR_B0 | AMD_DR_B1)) { mixed = 1; break; } @@ -822,9 +822,9 @@ static void cpuSetAMDPCI(u8 node) val &= ~fam10_pci_default[i].mask; val |= fam10_pci_default[i].data; pci_write_config32(NODE_PCI(node, - fam10_pci_default[i]. - function), - fam10_pci_default[i].offset, val); + fam10_pci_default[i]. + function), + fam10_pci_default[i].offset, val); } } @@ -839,7 +839,7 @@ static void cpuSetAMDPCI(u8 node) for (j = 0; j < 4; j++) { if (AMD_CpuFindCapability(node, j, &offset)) { if (AMD_checkLinkType(node, j, offset) - & fam10_htphy_default[i].linktype) { + & fam10_htphy_default[i].linktype) { AMD_SetHtPhyRegister(node, j, i); } diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000086.h b/src/cpu/amd/model_10xxx/mc_patch_01000086.h index d538036..f5f6f67 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000086.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000086.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000095.h b/src/cpu/amd/model_10xxx/mc_patch_01000095.h index bfb2e10..54f27e8 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000095.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000095.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000096.h b/src/cpu/amd/model_10xxx/mc_patch_01000096.h index e45bdf5..705e67b 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000096.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000096.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_0100009f.h b/src/cpu/amd/model_10xxx/mc_patch_0100009f.h index d59f138..f20d852 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_0100009f.h +++ b/src/cpu/amd/model_10xxx/mc_patch_0100009f.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000b6.h b/src/cpu/amd/model_10xxx/mc_patch_010000b6.h index 934ef16..e010789 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000b6.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000b6.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h index 9baaa9b..393eabb 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose. THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode. @@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000c4.h b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h index 1ff8aa1..3e9c343 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000c4.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h @@ -7,13 +7,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..18b333e 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -130,18 +130,18 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100f22 }, { X86_VENDOR_AMD, 0x100f23 }, { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ - { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ - { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ - { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ - { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ - { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ - { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ + { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ + { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ + { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ + { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ + { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ + { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ { 0, 0 }, }; static const struct cpu_driver model_10xxx __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c index b16e9ba..c7f1d3d 100644 --- a/src/cpu/amd/model_10xxx/processor_name.c +++ b/src/cpu/amd/model_10xxx/processor_name.c @@ -258,7 +258,7 @@ int init_processor_name(void) goto done; j = strcpymax(program_string, processor_name_string, - sizeof(program_string)); + sizeof(program_string)); /* Translate Model from 01-99 to ASCII and put it on the end. * Numbers less than 10 should include a leading zero, e.g., 09.*/ diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index cc08cdc..269876d 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -36,22 +36,22 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors * - * Installed Processor Equivalent Processor Patch Level - * Revision ID Revision ID - * 00100F00h 1000h 01000020h - * 00100F01h 1000h 01000020h - * 00100F02h 1000h 01000020h - * 00100F20h 1020h 01000096h - * 00100F21h (DR-B1) 1020h 01000096h - * 00100F2Ah (DR-BA) 1020h 01000096h - * 00100F22h (DR-B2) 1022h 01000095h - * 00100F23h (DR-B3) 1022h 01000095h - * 00100F42h (RB-C2) 1041h 01000086h - * 00100F43h (RB-C3) 1043h 010000b6h - * 00100F62h (DA-C2) 1062h 0100009Fh - * 00100F63h (DA-C3) 1043h 010000b6h - * 00100F81h (HY-D1) 1081h 010000c4h - * 00100FA0h (PH-E0) 10A0h 010000bfh + * Installed Processor Equivalent Processor Patch Level + * Revision ID Revision ID + * 00100F00h 1000h 01000020h + * 00100F01h 1000h 01000020h + * 00100F02h 1000h 01000020h + * 00100F20h 1020h 01000096h + * 00100F21h (DR-B1) 1020h 01000096h + * 00100F2Ah (DR-BA) 1020h 01000096h + * 00100F22h (DR-B2) 1022h 01000095h + * 00100F23h (DR-B3) 1022h 01000095h + * 00100F42h (RB-C2) 1041h 01000086h + * 00100F43h (RB-C3) 1043h 010000b6h + * 00100F62h (DA-C2) 1062h 0100009Fh + * 00100F63h (DA-C3) 1043h 010000b6h + * 00100F81h (HY-D1) 1081h 010000c4h + * 00100FA0h (PH-E0) 10A0h 010000bfh */ #include CONFIG_AMD_UCODE_PATCH_FILE diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index e68611b..8584fd3 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -60,7 +60,7 @@ static void enable_fid_change(void) #endif dword = 0x23070700; /* enable FID/VID change */ -// dword = 0x00070000; /* enable FID/VID change */ +// dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword); #if CONFIG_HAVE_ACPI_RESUME @@ -94,14 +94,14 @@ static unsigned set_fidvid_without_init(unsigned fidvid) static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) { -/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... - * -------------------------------------- +/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... + * -------------------------------------- * TargetFID | Next_FID, Next_FID, Next_FID, Next_FID ... - * | | Next_FID, Next_FID, Next_FID, Next_FID ... + * | | Next_FID, Next_FID, Next_FID, Next_FID ... * \|/ | Next_FID, Next_FID, Next_FID, Next_FID ... */ static const u8 next_fid_200[] = { -/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ +/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ /* x4 */ 0, -1, -1, -1, 0, 0, 9, 10, 11, 12, 13, 14, 15, /* 800 */ /* x5 */ -1, 0, -1, -1, -1, 5, 5, 5, 11, 12, 13, 14, 15, /* 1000 */ /* x6 */ -1, -1, 0, -1, -1, -1, -1, 6, 6, 6, 13, 14, 15, /* 1200 */ @@ -134,8 +134,8 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) if (apicid != apicidx) { printk(BIOS_ERR, - "wrong apicid, we want change %x, but it is %x\n", - apicid, apicidx); + "wrong apicid, we want change %x, but it is %x\n", + apicid, apicidx); return fidvid; } @@ -166,12 +166,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) /* TODO - make this more correct. Not a big deal for setting max... * BKDG figure 11 * if TargetFID > InitialFID - * TargetVID = FinalVID - RVO + * TargetVID = FinalVID - RVO * else - * if CurrentVID > FinalVID - * TargetVID = FinalVID - RVO - * else - * TargetVID = CurrentVIDD - RVO + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); @@ -205,7 +205,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) */ printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, - fid_max); + fid_max); printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new); step_limit = 8; /* max 8 steps just in case... */ @@ -262,7 +262,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) if (fid_temp > fid_max) { printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", - fid_temp, fid_max); + fid_temp, fid_max); break; } @@ -333,11 +333,11 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) if (showmessage) { if (vid_new != vid_cur) { printk(BIOS_ERR, "set vid failed for apicid =%02x\n", - apicidx); + apicidx); } if (fid_new != fid_cur) { printk(BIOS_ERR, "set fid failed for apicid =%02x\n", - apicidx); + apicidx); } } @@ -388,13 +388,13 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) timeout = wait_cpu_state(bsp_apicid, 1); if (timeout) { printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading" - " from BSP on %02x\n", apicid); + " from BSP on %02x\n", apicid); } /* send signal to BSP about this AP max fid and vid */ /* AP at state 1 that sent our fid and vid */ lapic_write(LAPIC_MSG_REG, send | 1); -// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ +// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ loop = 1000000; while (--loop > 0) { /* remote read BSP signal that include vid/fid that need to set */ @@ -417,7 +417,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) send = (apicid << 24) | (readback & 0x00ffff00); } else { printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", - __func__, apicid); + __func__, apicid); } lapic_write(LAPIC_MSG_REG, send | 2); @@ -425,7 +425,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) timeout = wait_cpu_state(bsp_apicid, 3); if (timeout) { printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", - __func__, apicid); + __func__, apicid); } } @@ -466,7 +466,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) if (timeout) { printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", - __func__, ap_apicid); + __func__, ap_apicid); return; } @@ -502,7 +502,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) if (timeout) { printk(BIOS_DEBUG, "%s: time out while reading from ap %02x", - __func__, ap_apicid); + __func__, ap_apicid); return; } diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 7121642..642785c 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -128,8 +128,8 @@ void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { printk(BIOS_DEBUG, - "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, - apicid, id.nodeid, id.coreid); + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); } static u32 wait_cpu_state(u32 apicid, u32 state) @@ -221,7 +221,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) } enable_lapic(); - // init_timer(); // We need TMICT to pass msg for FID/VID change + // init_timer(); // We need TMICT to pass msg for FID/VID change #if CONFIG_ENABLE_APIC_EXT_ID u32 initial_apicid = get_initial_apicid(); @@ -259,14 +259,14 @@ static u32 init_cpus(u32 cpu_init_detectedx) if (cpu_init_detectedx) { print_apicid_nodeid_coreid(apicid, id, - "\n\n\nINIT detected from "); + "\n\n\nINIT detected from "); printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); } if (id.coreid == 0) { distinguish_cpu_resets(id.nodeid); -// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set +// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started @@ -288,8 +288,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) } if (timeout) { printk(BIOS_DEBUG, - "while waiting for BSP signal to STOP, timeout in ap %02x\n", - apicid); + "while waiting for BSP signal to STOP, timeout in ap %02x\n", + apicid); } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 42c6f95..d74c3dc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,9 +32,9 @@ void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); - // wait for ap memory to trained - wait_all_core0_mem_trained(sysinfox); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); + // wait for ap memory to trained + wait_all_core0_mem_trained(sysinfox); #endif } #endif @@ -129,16 +129,16 @@ static void print_mtrr_state(struct mtrr_state *state) int i; for (i = 0; i < MTRR_COUNT; i++) { printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n", - i, - state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, - state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); + i, + state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, + state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); } printk(BIOS_DEBUG, "top_mem: %08x%08x\n", - state->top_mem.hi, state->top_mem.lo); + state->top_mem.hi, state->top_mem.lo); printk(BIOS_DEBUG, "top_mem2: %08x%08x\n", - state->top_mem2.hi, state->top_mem2.lo); + state->top_mem2.hi, state->top_mem2.lo); printk(BIOS_DEBUG, "def_type: %08x%08x\n", - state->def_type.hi, state->def_type.lo); + state->def_type.hi, state->def_type.lo); } #endif @@ -621,6 +621,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver model_fxx __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index f1747d9..082b706 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -36,36 +36,36 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { #if CONFIG_K8_REV_F_SUPPORT // #include "microcode_rev_f.h" #endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { #if !CONFIG_K8_REV_F_SUPPORT - 0x0f48, 0x0048, - 0x0f58, 0x0048, - - 0x0f4a, 0x004a, - 0x0f5a, 0x004a, - 0x0f7a, 0x004a, - 0x0f82, 0x004a, - 0x0fc0, 0x004a, - 0x0ff0, 0x004a, - - 0x10f50, 0x0150, - 0x10f70, 0x0150, - 0x10f80, 0x0150, - 0x10fc0, 0x0150, - 0x10ff0, 0x0150, - - 0x20f10, 0x0210, - 0x20f12, 0x0210, - 0x20f32, 0x0210, - 0x20fb1, 0x0210, + 0x0f48, 0x0048, + 0x0f58, 0x0048, + + 0x0f4a, 0x004a, + 0x0f5a, 0x004a, + 0x0f7a, 0x004a, + 0x0f82, 0x004a, + 0x0fc0, 0x004a, + 0x0ff0, 0x004a, + + 0x10f50, 0x0150, + 0x10f70, 0x0150, + 0x10f80, 0x0150, + 0x10fc0, 0x0150, + 0x10ff0, 0x0150, + + 0x20f10, 0x0210, + 0x20f12, 0x0210, + 0x20f32, 0x0210, + 0x20fb1, 0x0210, #endif #if CONFIG_K8_REV_F_SUPPORT @@ -93,8 +93,8 @@ void model_fxx_update_microcode(unsigned cpu_deviceid) { unsigned equivalent_processor_rev_id; - /* Update the microcode */ + /* Update the microcode */ equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); if(equivalent_processor_rev_id != 0) - amd_update_microcode(microcode_updates, equivalent_processor_rev_id); + amd_update_microcode(microcode_updates, equivalent_processor_rev_id); } diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index af1e24b..b5e5bf6 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -209,9 +209,9 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) fid_multiplier = 100; /* - * Formula1: CPUFreq = FID * fid_multiplier + 800 - * Formula2: CPUVolt = 1550 - VID * 25 (mv) - * Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2)) + * Formula1: CPUFreq = FID * fid_multiplier + 800 + * Formula2: CPUVolt = 1550 - VID * 25 (mv) + * Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2)) */ /* Construct P0(P[Max]) state */ @@ -310,8 +310,8 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * - Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0] * + Pstate_volt[0]); } Pstate_num++; } @@ -327,7 +327,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0]); Pstate_num++; } else { Pstate_fid[Pstate_num] = Start_fid; @@ -339,7 +339,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0]); Pstate_num++; } @@ -846,9 +846,9 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) for (i=0;i<Pstate_num;i++) printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, - Pstate_feq[i], - vid_from_reg(Pstate_vid[i]), - Pstate_power[i]); + Pstate_feq[i], + vid_from_reg(Pstate_vid[i]), + Pstate_power[i]); /* Loop over all CPU's */ for (dev = 0x18; dev < 0x1c; dev++) { diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index f3f7071..fb5d905 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -1,22 +1,22 @@ /* this setupcpu function comes from: */ /*==============================================================================*/ -/* FILE : start16.asm*/ +/* FILE : start16.asm*/ /**/ -/* DESC : A 16 bit mode assembly language startup program, intended for*/ -/* use with on Aspen SC520 platforms.*/ +/* DESC : A 16 bit mode assembly language startup program, intended for*/ +/* use with on Aspen SC520 platforms.*/ /**/ /* 11/16/2000 Added support for the NetSC520*/ /* 12/28/2000 Modified to boot linux image*/ /**/ /* =============================================================================*/ -/* */ -/* Copyright 2000 Advanced Micro Devices, Inc. */ -/* */ +/* */ +/* Copyright 2000 Advanced Micro Devices, Inc. */ +/* */ /* This software is the property of Advanced Micro Devices, Inc (AMD) which */ /* specifically grants the user the right to modify, use and distribute this */ /* software provided this COPYRIGHT NOTICE is not removed or altered. All */ -/* other rights are reserved by AMD. */ -/* */ +/* other rights are reserved by AMD. */ +/* */ /* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY */ /* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF */ /* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.*/ @@ -36,26 +36,26 @@ /* So that all may benefit from your experience, please report any problems */ /* or suggestions about this software back to AMD. Please include your name, */ /* company, telephone number, AMD product requiring support and question or */ -/* problem encountered. */ -/* */ -/* Advanced Micro Devices, Inc. Worldwide support and contact */ -/* Embedded Processor Division information available at: */ -/* Systems Engineering epd.support(a)amd.com*/ -/* 5204 E. Ben White Blvd. -or-*/ -/* Austin, TX 78741 http://www.amd.com/html/support/techsup.html*/ +/* problem encountered. */ +/* */ +/* Advanced Micro Devices, Inc. Worldwide support and contact */ +/* Embedded Processor Division information available at: */ +/* Systems Engineering epd.support(a)amd.com*/ +/* 5204 E. Ben White Blvd. -or-*/ +/* Austin, TX 78741 http://www.amd.com/html/support/techsup.html*/ /* ============================================================================*/ #define OUTC(addr, val) *(unsigned char *)(addr) = (val) /* sadly, romcc can't quite handle what we want, so we do this ugly thing */ -#define drcctl (( volatile unsigned char *)0xfffef010) -#define drcmctl (( volatile unsigned char *)0xfffef012) -#define drccfg (( volatile unsigned char *)0xfffef014) +#define drcctl (( volatile unsigned char *)0xfffef010) +#define drcmctl (( volatile unsigned char *)0xfffef012) +#define drccfg (( volatile unsigned char *)0xfffef014) #define drcbendadr (( volatile unsigned long *)0xfffef018) -#define eccctl (( volatile unsigned char *)0xfffef020) -#define dbctl (( volatile unsigned char *)0xfffef040) +#define eccctl (( volatile unsigned char *)0xfffef020) +#define dbctl (( volatile unsigned char *)0xfffef040) void setupsc520(void) { @@ -341,7 +341,7 @@ int sizemem(void) if (*lp != 0xdeadbeef) { print_err(" no memory at bank "); // print_err_hex8(bank); - // print_err(" value "); print_err_hex32(*lp); + // print_err(" value "); print_err_hex32(*lp); print_err("\n"); // continue; } diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 808c33c..6778fa9 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -37,13 +37,13 @@ static void sc520_enable_resources(struct device *dev) { unsigned char command; printk(BIOS_SPEW, "%s\n", __func__); - command = pci_read_config8(dev, PCI_COMMAND); - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); - command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); - pci_write_config8(dev, PCI_COMMAND, command); - command = pci_read_config8(dev, PCI_COMMAND); - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + command = pci_read_config8(dev, PCI_COMMAND); + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + pci_write_config8(dev, PCI_COMMAND, command); + command = pci_read_config8(dev, PCI_COMMAND); + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); /* */ @@ -70,11 +70,11 @@ static void sc520_read_resources(device_t dev) static struct device_operations cpu_operations = { .read_resources = sc520_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = sc520_enable_resources, - .init = cpu_init, - .enable = 0, - .ops_pci = 0, + .init = cpu_init, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver cpu_driver __pci_driver = { @@ -86,9 +86,9 @@ static const struct pci_driver cpu_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; @@ -150,18 +150,18 @@ void sc520_enable_resources(device_t dev) { #endif static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, /* * If enable_resources is set to the generic enable_resources * function the whole thing will hang in an endless loop on * the ts5300. If this is really needed on another platform, * something is conceptually wrong. */ - .enable_resources = 0, //enable_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .enable_resources = 0, //enable_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, }; #if 0 @@ -175,28 +175,28 @@ static void cpu_bus_noop(device_t dev) } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, }; #endif static void enable_dev(struct device *dev) { printk(BIOS_SPEW, "%s\n", __func__); - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } #if 0 /* This is never hit as none of the sc520 boards have * an APIC cluster defined */ - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } #endif } diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 2943b91..16047df 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -1,5 +1,5 @@ config CPU_AMD_SOCKET_S1G1 - bool + bool if CPU_AMD_SOCKET_S1G1 diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 055fffe..4d8c503 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -19,19 +19,19 @@ .section ".dmp_reserved", "a", @progbits - .skip 0x3c000 - 0x3bc00, 0xff + .skip 0x3c000 - 0x3bc00, 0xff .previous .section ".dmp_kbd_fw_part2", "a", @progbits - .skip 0x3d000 - 0x3c000, 0xff + .skip 0x3d000 - 0x3c000, 0xff .previous .section ".dmp_mtbf_low_cnt", "a", @progbits - .skip 0x3e000 - 0x3d000, 0xff + .skip 0x3e000 - 0x3d000, 0xff .previous @@ -43,42 +43,42 @@ .section ".dmp_spi_flash_disk_driver", "a", @progbits - .skip 0x3f800 - 0x3f000, 0xff + .skip 0x3f800 - 0x3f000, 0xff .previous .section ".dmp_frontdoor", "a", @progbits - .skip 0x3fd00 - 0x3f800, 0xff + .skip 0x3fd00 - 0x3f800, 0xff .previous .section ".dmp_isoinfo", "a", @progbits - .skip 26 * 16, 0xff + .skip 26 * 16, 0xff .previous .section ".dmp_isodata_checksum", "a", @progbits - .skip 8, 0xff + .skip 8, 0xff .previous .section ".dmp_mac", "a", @progbits - .skip 6, 0xff + .skip 6, 0xff .previous .section ".dmp_mtbf_limit", "a", @progbits - .skip 3, 0xff + .skip 3, 0xff .previous .section ".dmp_isodata", "a", @progbits - .skip 32, 0xff + .skip 32, 0xff .previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc index 4a2478e..02805fb 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc @@ -25,27 +25,27 @@ CPU Freq = PLL/(CPU_DIV+2) DRAM Freq = PLL/2(DRAM_DIV+1) DDR3 -CPU/DRAM/PCI B6 B7 BB BC BD BF -200/200/33 30 03 0F 02 8F 07 -300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable -300/300/100 48 03 23 02 7F 07 -400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing -400/200/100 60 43 23 02 4F 07 -400/400/33 60 03 0F 02 BF 09 -500/250/33 50 42 0F 02 DF 07 -500/500/33 78 03 0F 02 4F 09 -400/300/33 90 53 0F 02 3F 07 -400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable -400/300/100 90 53 23 02 9F 07 -444/333/33 A0 53 0F 02 5F 08 -466/350/33 A8 53 0F 02 DF 09 -500/375/33 B4 53 0F 02 AF 09 +CPU/DRAM/PCI B6 B7 BB BC BD BF +200/200/33 30 03 0F 02 8F 07 +300/300/33 48 03 0F 02 1F 07 +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable +300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/100 48 03 23 02 7F 07 +400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing +400/200/100 60 43 23 02 4F 07 +400/400/33 60 03 0F 02 BF 09 +500/250/33 50 42 0F 02 DF 07 +500/500/33 78 03 0F 02 4F 09 +400/300/33 90 53 0F 02 3F 07 +400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable +400/300/100 90 53 23 02 9F 07 +444/333/33 A0 53 0F 02 5F 08 +466/350/33 A8 53 0F 02 DF 09 +500/375/33 B4 53 0F 02 AF 09 */ #if CONFIG_PLL_200_200_33 - // 200/200/33 30 03 0F 02 8F 07 + // 200/200/33 30 03 0F 02 8F 07 byte_fffb6 = 0x30 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -53,7 +53,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_300_300_33 - // 300/300/33 48 03 0F 02 1F 07 + // 300/300/33 48 03 0F 02 1F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -61,7 +61,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_300_300_100 - // 300/300/100 48 03 23 02 7F 07 + // 300/300/100 48 03 23 02 7F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 byte_fffbb = 0x23 @@ -69,7 +69,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_200_33 - // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing + // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing byte_fffb6 = 0x60 byte_fffb7 = 0x43 byte_fffbb = 0x0f @@ -77,7 +77,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_200_100 - // 400/200/100 60 43 23 02 4F 07 + // 400/200/100 60 43 23 02 4F 07 byte_fffb6 = 0x60 byte_fffb7 = 0x43 byte_fffbb = 0x23 @@ -85,7 +85,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_400_33 - // 400/400/33 60 03 0F 02 BF 09 + // 400/400/33 60 03 0F 02 BF 09 byte_fffb6 = 0x60 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -93,7 +93,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_500_250_33 - // 500/250/33 50 42 0F 02 DF 07 + // 500/250/33 50 42 0F 02 DF 07 byte_fffb6 = 0x50 byte_fffb7 = 0x42 byte_fffbb = 0x0f @@ -101,7 +101,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_500_500_33 - // 500/500/33 78 03 0F 02 4F 09 + // 500/500/33 78 03 0F 02 4F 09 byte_fffb6 = 0x78 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -109,7 +109,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_400_300_33 - // 400/300/33 90 53 0F 02 3F 07 + // 400/300/33 90 53 0F 02 3F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -117,7 +117,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_300_100 - // 400/300/100 90 53 23 02 9F 07 + // 400/300/100 90 53 23 02 9F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 byte_fffbb = 0x23 @@ -125,7 +125,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_444_333_33 - // 444/333/33 A0 53 0F 02 5F 08 + // 444/333/33 A0 53 0F 02 5F 08 byte_fffb6 = 0xa0 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -133,7 +133,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x08 #elif CONFIG_PLL_466_350_33 - // 466/350/33 A8 53 0F 02 DF 09 + // 466/350/33 A8 53 0F 02 DF 09 byte_fffb6 = 0xa8 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -141,7 +141,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_500_375_33 - // 500/375/33 B4 53 0F 02 AF 09 + // 500/375/33 B4 53 0F 02 AF 09 byte_fffb6 = 0xb4 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -159,7 +159,7 @@ byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f .section ".a9123_crossbar_config", "a", @progbits - .skip 0x3fdf0 - 0x3fd00, 0xff + .skip 0x3fdf0 - 0x3fd00, 0xff .previous diff --git a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc index 486bf1b..0d9d64d 100644 --- a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +++ b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc @@ -17,515 +17,515 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - .byte 0x02, 0x04, 0xa3, 0x02, 0x0a, 0xfb, 0xef, 0x75 - .byte 0xf0, 0x03, 0xa4, 0xff, 0xae, 0x07, 0x1f, 0xee - .byte 0x70, 0xfa, 0x22, 0x02, 0x0a, 0xd5, 0x12, 0x09 - .byte 0x5e, 0x7f, 0x30, 0x12, 0x05, 0xfb, 0x90, 0xe0 - .byte 0x00, 0x74, 0x16, 0xf0, 0x12, 0x0d, 0xda, 0xc2 - .byte 0x92, 0xc2, 0x93, 0xc2, 0x90, 0xd2, 0x91, 0xd2 - .byte 0xb8, 0xd2, 0xba, 0xd2, 0x88, 0xd2, 0xa8, 0xd2 - .byte 0x8a, 0xd2, 0xaa, 0x7d, 0x44, 0xe4, 0xff, 0x12 - .byte 0x0e, 0x3a, 0x7d, 0x4d, 0x0f, 0x12, 0x0e, 0x3a - .byte 0x7d, 0x26, 0x0f, 0x12, 0x0e, 0x3a, 0x7d, 0x50 - .byte 0x0f, 0x12, 0x0e, 0x3a, 0x12, 0x0e, 0x59, 0xd2 - .byte 0xaf, 0x7f, 0xb1, 0x12, 0x0e, 0xf5, 0x90, 0x0f - .byte 0xfe, 0xe4, 0x93, 0xff, 0xb4, 0x55, 0x0a, 0xa3 - .byte 0xe4, 0x93, 0xb4, 0xaa, 0x04, 0xd2, 0x08, 0x80 - .byte 0x10, 0xef, 0xb4, 0x12, 0x0c, 0x90, 0x0f, 0xff - .byte 0xe4, 0x93, 0xb4, 0x34, 0x04, 0xc2, 0x08, 0xc2 - .byte 0x12, 0x12, 0x03, 0x6c, 0x12, 0x0d, 0xa6, 0x12 - .byte 0x01, 0x08, 0x30, 0x01, 0x27, 0x30, 0x12, 0x1f - .byte 0x20, 0x00, 0x1c, 0x30, 0x11, 0x19, 0x12, 0x0d - .byte 0x25, 0x12, 0x09, 0xc4, 0x30, 0x08, 0x05, 0xc2 - .byte 0x1a, 0x12, 0x0a, 0x26, 0x12, 0x0d, 0x92, 0xd2 - .byte 0x00, 0x12, 0x0d, 0x3b, 0x12, 0x07, 0xc2, 0x12 - .byte 0x0d, 0xda, 0xc2, 0x01, 0x12, 0x03, 0x6c, 0x12 - .byte 0x07, 0x2e, 0x30, 0x12, 0xc4, 0x30, 0x00, 0xc1 - .byte 0x90, 0xd0, 0x00, 0xe0, 0x30, 0xe0, 0xba, 0xc2 - .byte 0xaf, 0x12, 0x0e, 0x07, 0x50, 0x0e, 0x12, 0x0e - .byte 0xb6, 0x12, 0x0e, 0xbc, 0xd2, 0x1a, 0x12, 0x0a - .byte 0x26, 0x12, 0x0d, 0x3b, 0xd2, 0xaf, 0x80, 0xa1 - .byte 0xae, 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90 - .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e - .byte 0x33, 0x7f, 0x20, 0x12, 0x0d, 0x51, 0x43, 0x1a - .byte 0x10, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22 - .byte 0xda, 0x7e, 0x10, 0x09, 0x14, 0x12, 0x0d, 0xa6 - .byte 0x90, 0xe0, 0x00, 0xe0, 0xff, 0x20, 0xe1, 0x03 - .byte 0x02, 0x02, 0xc8, 0xc2, 0xa8, 0xc2, 0xaa, 0x20 - .byte 0x04, 0x03, 0x30, 0x07, 0x05, 0xd2, 0xa8, 0xd2 - .byte 0xaa, 0x22, 0xef, 0xa2, 0xe3, 0x92, 0x1c, 0x90 - .byte 0xf0, 0x00, 0xe0, 0xf5, 0x2c, 0x12, 0x0e, 0x2f - .byte 0xd2, 0xa8, 0xd2, 0xaa, 0x30, 0x1c, 0x03, 0x02 - .byte 0x01, 0xee, 0xc2, 0x1d, 0xc2, 0x1e, 0x20, 0x17 - .byte 0x03, 0x02, 0x01, 0xd4, 0xe5, 0x18, 0x24, 0xe1 - .byte 0x60, 0x3b, 0x24, 0x54, 0x70, 0x03, 0x02, 0x01 - .byte 0xd0, 0x24, 0xfa, 0x60, 0x14, 0x14, 0x60, 0x1e - .byte 0x14, 0x60, 0x1f, 0x14, 0x60, 0x23, 0x24, 0x74 - .byte 0x70, 0x6c, 0xaf, 0x2c, 0x12, 0x05, 0xfb, 0x80 - .byte 0x67, 0xe5, 0x2c, 0x30, 0xe1, 0x04, 0xd2, 0x90 - .byte 0x80, 0x5e, 0xc2, 0x90, 0x80, 0x5a, 0xc2, 0x1f - .byte 0x80, 0x02, 0xd2, 0x1f, 0x85, 0x2c, 0x2f, 0x80 - .byte 0x46, 0xd2, 0x1e, 0x80, 0x4b, 0xe5, 0x2c, 0x70 - .byte 0x1a, 0x12, 0x0c, 0xed, 0x12, 0x08, 0xf2, 0x85 - .byte 0x38, 0x12, 0x85, 0x39, 0x13, 0x85, 0x3a, 0x14 - .byte 0x85, 0x09, 0x15, 0x85, 0x0a, 0x16, 0x85, 0x0b - .byte 0x17, 0x80, 0x2d, 0xe5, 0x2c, 0xc3, 0x94, 0x01 - .byte 0x40, 0x13, 0xe5, 0x2c, 0xd3, 0x94, 0x06, 0x50 - .byte 0x0c, 0xc2, 0x1f, 0x74, 0x11, 0x25, 0x2c, 0xf8 - .byte 0xe6, 0xf5, 0x2f, 0x80, 0x0a, 0xe5, 0x2c, 0xb4 - .byte 0x07, 0x0e, 0xc2, 0x1f, 0x85, 0x3b, 0x2f, 0xd2 - .byte 0x20, 0x12, 0x0d, 0xb8, 0x80, 0x02, 0xd2, 0x1d - .byte 0xc2, 0x17, 0x80, 0x02, 0xd2, 0x1d, 0x30, 0x1d - .byte 0x07, 0xaf, 0x2c, 0x12, 0x05, 0x2f, 0x80, 0x08 - .byte 0x30, 0x1e, 0x05, 0xaf, 0x2c, 0x12, 0x05, 0x97 - .byte 0x12, 0x0e, 0x85, 0x02, 0x02, 0xc2, 0xc2, 0x1d - .byte 0xe5, 0x2c, 0x12, 0x0b, 0x21, 0x02, 0xb7, 0x1f - .byte 0x02, 0x35, 0x20, 0x02, 0xb7, 0x60, 0x02, 0x56 - .byte 0xa7, 0x02, 0x5d, 0xa8, 0x02, 0x64, 0xa9, 0x02 - .byte 0x48, 0xaa, 0x02, 0x64, 0xab, 0x02, 0x6d, 0xad - .byte 0x02, 0x74, 0xae, 0x02, 0x41, 0xc0, 0x02, 0xb7 - .byte 0xcb, 0x02, 0x7b, 0xd0, 0x02, 0xb7, 0xd1, 0x02 - .byte 0xb7, 0xd2, 0x02, 0xb7, 0xd3, 0x02, 0xb7, 0xd4 - .byte 0x02, 0x98, 0xdd, 0x02, 0x8d, 0xdf, 0x02, 0xa8 - .byte 0xfe, 0x00, 0x00, 0x02, 0xb5, 0x12, 0x0a, 0x83 - .byte 0x8f, 0x2d, 0xc2, 0x1f, 0x85, 0x2d, 0x2f, 0x80 - .byte 0x28, 0xc2, 0x1f, 0x75, 0x2f, 0xff, 0x80, 0x21 - .byte 0x7f, 0x30, 0x12, 0x05, 0xfb, 0xc2, 0x1f, 0x75 - .byte 0x2f, 0x55, 0xc2, 0x20, 0x80, 0x4b, 0x12, 0x0e - .byte 0x8d, 0xd2, 0x1d, 0x80, 0x5a, 0x12, 0x0e, 0xe6 - .byte 0xd2, 0x1d, 0x80, 0x53, 0xc2, 0x1f, 0xe4, 0xf5 - .byte 0x2f, 0xd2, 0x20, 0x80, 0x34, 0x12, 0x0e, 0x94 - .byte 0xd2, 0x1d, 0x80, 0x43, 0x12, 0x0e, 0xf0, 0xd2 - .byte 0x1d, 0x80, 0x3c, 0x75, 0x2e, 0x01, 0x30, 0x90 - .byte 0x03, 0x43, 0x2e, 0x02, 0xc2, 0x1f, 0x85, 0x2e - .byte 0x2f, 0xd2, 0x20, 0x80, 0x14, 0xd2, 0x90, 0xc2 - .byte 0x1f, 0x85, 0x0f, 0x2f, 0xd2, 0x20, 0x80, 0x09 - .byte 0xc2, 0x90, 0xc2, 0x1f, 0x85, 0x0f, 0x2f, 0xd2 - .byte 0x20, 0x12, 0x0d, 0xb8, 0xd2, 0x1d, 0x80, 0x0f - .byte 0xc2, 0x91, 0x7f, 0x05, 0x12, 0x00, 0x06, 0xd2 - .byte 0x91, 0xd2, 0x1d, 0x80, 0x02, 0xd2, 0x1d, 0x30 - .byte 0x1d, 0x03, 0x12, 0x0e, 0x85, 0xd2, 0x17, 0x85 - .byte 0x2c, 0x18, 0x20, 0x01, 0x03, 0x12, 0x0d, 0xda - .byte 0x22, 0x44, 0x4d, 0x26, 0x50, 0x00, 0xff, 0x43 - .byte 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44 - .byte 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38 - .byte 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71 - .byte 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, 0x67, 0x2e - .byte 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, 0x68, 0x39 - .byte 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31 - .byte 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72 - .byte 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33 - .byte 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, 0x6c, 0x34 - .byte 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, 0x6d, 0x73 - .byte 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36 - .byte 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56 - .byte 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f - .byte 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, 0x52, 0x53 - .byte 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, 0x57, 0x4e - .byte 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, 0x00, 0x00 - .byte 0x00, 0x41, 0x54, 0x00, 0x01, 0x01, 0x02, 0x01 - .byte 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02 - .byte 0x03, 0x03, 0x04, 0x14, 0x23, 0x14, 0x3a, 0x14 - .byte 0x4d, 0x42, 0x32, 0x23, 0x20, 0x0c, 0x03, 0x02 - .byte 0x04, 0x08, 0xc2, 0x1a, 0xc2, 0x1b, 0xe5, 0x10 - .byte 0x30, 0xe7, 0x57, 0xe5, 0x11, 0xae, 0x10, 0x78 - .byte 0x06, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9 - .byte 0xf5, 0x26, 0xff, 0x12, 0x0d, 0xca, 0x8f, 0x27 - .byte 0xe5, 0x10, 0xc4, 0x13, 0x13, 0x54, 0x03, 0xff - .byte 0xe5, 0x27, 0x54, 0x01, 0xb5, 0x07, 0x05, 0xe4 - .byte 0x7f, 0x01, 0x80, 0x02, 0x7f, 0x00, 0xef, 0x30 - .byte 0xe0, 0x04, 0xd2, 0x1b, 0x80, 0x24, 0x20, 0x13 - .byte 0x1f, 0xaf, 0x26, 0x12, 0x07, 0x79, 0xaf, 0x26 - .byte 0x12, 0x09, 0xf6, 0x8e, 0x28, 0x8f, 0x29, 0xe5 - .byte 0x29, 0xf4, 0x70, 0x03, 0xe5, 0x28, 0xf4, 0x60 - .byte 0x09, 0x85, 0x29, 0x26, 0xd2, 0x1a, 0x80, 0x02 - .byte 0xd2, 0x1a, 0x30, 0x1a, 0x1b, 0xc2, 0x27, 0x7f - .byte 0x07, 0x12, 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0x12, 0x06, 0x98, 0xd0, 0x07 + .byte 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0, 0xd0, 0xe0 + .byte 0x32, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93 + .byte 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3 + .byte 0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82 + .byte 0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68 + .byte 0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0xae + .byte 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e, 0x33 + .byte 0x7f, 0x02, 0x12, 0x0d, 0x51, 0xaf, 0x2f, 0x12 + .byte 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x22, 0x74, 0x01, 0xa8, 0x07 + .byte 0x08, 0x80, 0x02, 0xc3, 0x33, 0xd8, 0xfc, 0xff + .byte 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02, 0xfe, 0xef + .byte 0x30, 0x27, 0x04, 0x42, 0x06, 0x80, 0x03, 0xf4 + .byte 0x52, 0x06, 0x90, 0xe0, 0x00, 0xee, 0xf0, 0x22 + .byte 0x12, 0x0e, 0x07, 0x40, 0x05, 0x12, 0x01, 0x05 + .byte 0x80, 0xf6, 0x12, 0x0e, 0xc8, 0x12, 0x0e, 0xd4 + .byte 0xc2, 0x1f, 0x75, 0x2f, 0xee, 0xa2, 0x06, 0x92 + .byte 0x20, 0x12, 0x0d, 0xb8, 0x90, 0xd0, 0x00, 0xe0 + .byte 0x30, 0xe1, 0xf9, 0x22, 0xae, 0x03, 0xab, 0x05 + .byte 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a + .byte 0xf0, 0xad, 0x07, 0x8e, 0x33, 0x7f, 0x03, 0x12 + .byte 0x0d, 0x51, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10 + .byte 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0xe5 + .byte 0x1a, 0x54, 0x9f, 0xfd, 0x44, 0x20, 0xfe, 0x7c + .byte 0x08, 0xef, 0x25, 0xe0, 0xff, 0x90, 0xd0, 0x00 + .byte 0xed, 0xf0, 0xe0, 0x30, 0xe4, 0x03, 0x43, 0x07 + .byte 0x01, 0x90, 0xd0, 0x00, 0xee, 0xf0, 0xdc, 0xe9 + .byte 0x22, 0x90, 0xf0, 0x00, 0xe5, 0x32, 0xf0, 0xf5 + .byte 0x0f, 0xa2, 0x26, 0x92, 0x27, 0x7f, 0x05, 0x12 + .byte 0x0b, 0x6c, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02 + .byte 0x54, 0xfe, 0xfe, 0xf0, 0x44, 0x01, 0xf0, 0xee + .byte 0xf0, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x9f, 0x12, 0x0c, 0xd0 + .byte 0x12, 0x0b, 0xd7, 0x12, 0x0b, 0xd7, 0x12, 0x0b + .byte 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00, 0xe5 + .byte 0x1a, 0xf0, 0x22, 0x8f, 0x2b, 0x7f, 0xed, 0x12 + .byte 0x05, 0x2f, 0xaf, 0x2b, 0x12, 0x05, 0x2f, 0x75 + .byte 0x2c, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12, 0x0c + .byte 0x79, 0x12, 0x0e, 0x62, 0x50, 0xfb, 0xd5, 0x2c + .byte 0xf1, 0x22, 0x8f, 0x28, 0x8d, 0x29, 0x12, 0x0e + .byte 0x74, 0x12, 0x0e, 0xa2, 0xe5, 0x28, 0x24, 0xfe + .byte 0xfb, 0x85, 0x29, 0x2f, 0x7d, 0xef, 0xaf, 0x34 + .byte 0x12, 0x0b, 0x47, 0x12, 0x0e, 0xa9, 0x02, 0x0d + .byte 0xea, 0xad, 0x07, 0xac, 0x06, 0xc2, 0x8c, 0xed + .byte 0xf4, 0xff, 0xec, 0xf4, 0xfe, 0xef, 0x24, 0x01 + .byte 0xfd, 0xe4, 0x3e, 0xf5, 0x8c, 0xaf, 0x05, 0x8f + .byte 0x8a, 0xc2, 0x8d, 0xd2, 0x8c, 0x22, 0xad, 0x07 + .byte 0xac, 0x06, 0xc2, 0xca, 0xed, 0xf4, 0xff, 0xec + .byte 0xf4, 0xfe, 0xef, 0x24, 0x01, 0xfd, 0xe4, 0x3e + .byte 0xf5, 0xcd, 0xaf, 0x05, 0x8f, 0xcc, 0xc2, 0xcf + .byte 0xd2, 0xca, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c + .byte 0xd0, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90 + .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xef, 0x13, 0x22 + .byte 0xe5, 0x1a, 0x54, 0x9f, 0xfe, 0x44, 0x40, 0xfd + .byte 0x7c, 0x08, 0x90, 0xd0, 0x00, 0xef, 0x33, 0xff + .byte 0x50, 0x03, 0xed, 0x80, 0x01, 0xee, 0xf0, 0x44 + .byte 0x20, 0xf0, 0xdc, 0xf1, 0x22, 0x12, 0x0f, 0x04 + .byte 0x8e, 0x39, 0x8f, 0x3a, 0x12, 0x0f, 0x1d, 0x8f + .byte 0x38, 0xe5, 0x38, 0x30, 0xe1, 0x03, 0x43, 0x39 + .byte 0x80, 0xe5, 0x38, 0x13, 0x13, 0x54, 0x3f, 0xf5 + .byte 0x38, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c, 0xd0 + .byte 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0xc8 + .byte 0x12, 0x0e, 0xd4, 0x90, 0xd0, 0x00, 0xe0, 0x20 + .byte 0xe1, 0x08, 0x12, 0x03, 0x6c, 0x12, 0x01, 0x05 + .byte 0x80, 0xf1, 0x22, 0x12, 0x0c, 0xed, 0x12, 0x08 + .byte 0xf2, 0xe5, 0x09, 0x70, 0x0b, 0xe5, 0x0a, 0x70 + .byte 0x07, 0xe5, 0x0b, 0x70, 0x03, 0x12, 0x0e, 0xda + .byte 0x22, 0x8d, 0x31, 0x8b, 0x32, 0x12, 0x0c, 0xd0 + .byte 0xaf, 0x31, 0x12, 0x0c, 0xd0, 0xaf, 0x32, 0x12 + .byte 0x0c, 0xd0, 0xaf, 0x33, 0x02, 0x0c, 0xd0, 0x53 + .byte 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0 + .byte 0x12, 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0x74 + .byte 0x12, 0x0e, 0xa2, 0xe4, 0xfb, 0x7d, 0xd0, 0xaf + .byte 0x34, 0x12, 0x00, 0xe0, 0x12, 0x0e, 0xa9, 0x02 + .byte 0x0d, 0xea, 0x53, 0x1a, 0xfb, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x53, 0x1a, 0xfd, 0xe5, 0x1a + .byte 0xf0, 0x7f, 0x3c, 0x02, 0x00, 0x06, 0x30, 0x09 + .byte 0x0e, 0x12, 0x0e, 0xb0, 0x40, 0x09, 0xc2, 0x92 + .byte 0xc2, 0x93, 0xc2, 0x09, 0x12, 0x0e, 0x7d, 0x22 + .byte 0xa2, 0x1f, 0x92, 0x21, 0x85, 0x2f, 0x30, 0xa2 + .byte 0x20, 0x92, 0x22, 0xc2, 0x23, 0xc2, 0x24, 0x02 + .byte 0x06, 0xee, 0xef, 0xc4, 0x54, 0x0f, 0x90, 0x03 + .byte 0x53, 0x93, 0xfe, 0xef, 0x54, 0x0f, 0x93, 0x2e + .byte 0xff, 0x22, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02 + .byte 0x54, 0xfe, 0xfe, 0xf0, 0x54, 0xfd, 0xf0, 0xee + .byte 0xf0, 0x22, 0x12, 0x0e, 0xa2, 0x12, 0x0c, 0xb3 + .byte 0x92, 0x1b, 0x12, 0x0e, 0xa9, 0x20, 0x1b, 0xf2 + .byte 0x22, 0x30, 0x05, 0x09, 0x20, 0x0e, 0x06, 0x20 + .byte 0x02, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x22, 0x30 + .byte 0x03, 0x09, 0x20, 0x0a, 0x06, 0x20, 0x02, 0x03 + .byte 0xd3, 0x80, 0x01, 0xc3, 0x22, 0xaa, 0x06, 0xea + .byte 0x24, 0xd0, 0xfd, 0xef, 0xfb, 0xaf, 0x34, 0x12 + .byte 0x0b, 0xb4, 0x22, 0xef, 0x24, 0xfe, 0xfb, 0x7d + .byte 0xef, 0xaf, 0x34, 0x12, 0x0b, 0xb4, 0x22, 0xd2 + .byte 0x02, 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x10, 0xc2 + .byte 0x94, 0x22, 0xef, 0x90, 0x02, 0xc9, 0x93, 0x6d + .byte 0x60, 0x02, 0x80, 0xfe, 0x22, 0x12, 0x0d, 0xf9 + .byte 0x50, 0x04, 0xc2, 0x10, 0xd2, 0x94, 0x22, 0x12 + .byte 0x0e, 0x07, 0x50, 0x04, 0xc2, 0x0d, 0xd2, 0x96 + .byte 0x22, 0xe5, 0x89, 0x54, 0xf0, 0x44, 0x01, 0xf5 + .byte 0x89, 0x22, 0x30, 0x8d, 0x04, 0xc2, 0x8c, 0xd3 + .byte 0x22, 0xc3, 0x22, 0x30, 0xcf, 0x04, 0xc2, 0xca + .byte 0xd3, 0x22, 0xc3, 0x22, 0x12, 0x0e, 0xa2, 0x12 + .byte 0x0e, 0xfa, 0x02, 0x0e, 0xa9, 0x12, 0x0e, 0xeb + .byte 0xc2, 0x0e, 0x02, 0x0e, 0x45, 0xc2, 0x02, 0x12 + .byte 0x0e, 0x4f, 0x02, 0x0e, 0x45, 0xc2, 0x05, 0xd2 + .byte 0x10, 0xc2, 0x94, 0x22, 0xc2, 0x03, 0xd2, 0x0d + .byte 0xc2, 0x96, 0x22, 0x90, 0xd0, 0x00, 0xe5, 0x1a + .byte 0xf0, 0x22, 0x30, 0x28, 0x03, 0x12, 0x0b, 0x90 + .byte 0x22, 0x30, 0x28, 0x03, 0x12, 0x0d, 0x92, 0x22 + .byte 0x90, 0xe0, 0x00, 0xe0, 0x13, 0x22, 0x53, 0x1a + .byte 0xfe, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x01, 0x02 + .byte 0x0e, 0x9b, 0x53, 0x1a, 0xfd, 0x02, 0x0e, 0x9b + .byte 0x43, 0x1a, 0x02, 0x02, 0x0e, 0x9b, 0x53, 0x1a + .byte 0xfb, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x04, 0x02 + .byte 0x0e, 0x9b, 0x53, 0x1a, 0x7f, 0x02, 0x0e, 0x9b + .byte 0x43, 0x1a, 0x80, 0x02, 0x0e, 0x9b, 0xd2, 0x05 + .byte 0x02, 0x0e, 0x45, 0xc2, 0x0a, 0x02, 0x0e, 0x4f + .byte 0xd2, 0x03, 0x02, 0x0e, 0x4f, 0x8f, 0x1a, 0x02 + .byte 0x0e, 0x9b, 0x7f, 0x06, 0x02, 0x0d, 0x67, 0x7f + .byte 0x04, 0x02, 0x0d, 0x67, 0xae, 0x36, 0xaf, 0x37 + .byte 0x22, 0xe4, 0xf5, 0xc8, 0x22, 0x12, 0x0c, 0x1a + .byte 0x22, 0xc2, 0x0b, 0x22, 0xd2, 0x0b, 0x22, 0xc2 + .byte 0x06, 0x22, 0xd2, 0x06, 0x22, 0xaf, 0x35, 0x22 + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..e322df3 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -169,7 +169,7 @@ clear_fixed_var_mtrr_out: /* * 0x06 is the WB IO type for a given 4k segment. * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. + * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fe1e29a..0fffa39 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -205,7 +205,7 @@ ap_init: post_code(0x27) /* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 diff --git a/src/cpu/intel/fit/fit.inc b/src/cpu/intel/fit/fit.inc index e4595c0..f27d2c2 100644 --- a/src/cpu/intel/fit/fit.inc +++ b/src/cpu/intel/fit/fit.inc @@ -11,7 +11,7 @@ fit_pointer: .global fit_table .global fit_table_end fit_table: -/* Address for type 0 is '_FIT_ ' */ +/* Address for type 0 is '_FIT_ ' */ .long 0x5449465f .long 0x2020205f /* diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 60c061d..0001b1c 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -34,6 +34,6 @@ $(SIPI_BIN): $(SIPI_ELF) $(OBJCOPY) -O binary $< $@ $(SIPI_BIN).ramstage.o: $(SIPI_BIN) - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 9e10c75..5c0bd00 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -330,7 +330,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package); for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 2d1e86f..bd109a4 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -32,9 +32,9 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) #define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) @@ -102,16 +102,16 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr /* Clear the cache memory region. This will also fill up the cache */ @@ -123,9 +123,9 @@ clear_mtrrs: rep stosl /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr post_code(0x26) @@ -141,8 +141,8 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr @@ -208,16 +208,16 @@ before_romstage: post_code(0x31) /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr invd /* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr #if CONFIG_CACHE_MRC_BIN diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7dfba86..e281c82 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -190,7 +190,7 @@ struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Returns 0 on success. < 0 on failure. */ int setup_ap_init(struct bus *cpu_bus, int *max_cpus, - const void *microcode_patch); + const void *microcode_patch); /* Returns 0 on success, < 0 on failure. */ int start_aps(struct bus *cpu_bus, int max_cpus); void release_aps_for_smm_relocation(int do_parallel_relocation); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index b2e6eaf..e07d08b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -53,33 +53,33 @@ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) + (IRTL_1024_NS >> 10)) /* * List of supported C-states in this processor. Only the ULT parts support C8, * C9, and C10. */ enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ NUM_C_STATES }; -#define MWAIT_RES(state, sub_state) \ - { \ +#define MWAIT_RES(state, sub_state) \ + { \ .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ @@ -259,7 +259,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); + err_code); /* Read the calibrated value. */ MCHBAR32(BIOS_MAILBOX_INTERFACE) = @@ -271,7 +271,7 @@ static void calibrate_24mhz_bclk(void) } printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); + MCHBAR32(BIOS_MAILBOX_DATA)); } static u32 pcode_mailbox_read(u32 command) @@ -303,7 +303,7 @@ static void configure_pch_power_sharing(void) pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); + pch_power, pch_power_ext); pmsync = RCBA32(PMSYNC_CONFIG); pmsync2 = RCBA32(PMSYNC_CONFIG2); @@ -465,19 +465,19 @@ static void configure_c_states(void) /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); /* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); /* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } } @@ -567,7 +567,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "haswell: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); } static void set_energy_perf_bias(u8 policy) @@ -587,7 +587,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", - policy); + policy); } static void configure_mca(void) @@ -694,7 +694,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) * can be mirrored by the APs. */ if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { printk(BIOS_CRIT, "AP setup initialization failed. " - "No APs will be brought up.\n"); + "No APs will be brought up.\n"); return; } @@ -716,7 +716,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) } static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = haswell_init, }; static struct cpu_device_id cpu_table[] = { @@ -728,7 +728,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index c03a468..858670e 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -26,7 +26,7 @@ #include "microcode-M3240660_ffff000b.h" #endif /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..135127d 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -112,7 +112,7 @@ static void (*ap_initiate_smm_relocation)(void) = &smm_initiate_relocation; /* Returns 1 if timeout waiting for APs. 0 if target aps found. */ static int wait_for_aps(atomic_t *val, int target, int total_delay, - int delay_step) + int delay_step) { int timeout = 0; int delayed = 0; @@ -139,7 +139,7 @@ void release_aps_for_smm_relocation(int do_parallel) release_barrier(&smm_relocation_barrier_begin); /* Wait for CPUs to relocate their SMM handler up to 100ms. */ if (wait_for_aps(&num_aps_relocated_smm, atomic_read(&num_aps), - 100000 /* 100 ms */, 200 /* us */)) + 100000 /* 100 ms */, 200 /* us */)) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } @@ -304,7 +304,7 @@ static int load_sipi_vector(const void *microcode_patch) if (rmodule_load_alignment(&sipi_mod) != 4096) { printk(BIOS_CRIT, "SIPI module load alignment(%d) != 4096.\n", - rmodule_load_alignment(&sipi_mod)); + rmodule_load_alignment(&sipi_mod)); return -1; } @@ -316,7 +316,7 @@ static int load_sipi_vector(const void *microcode_patch) if (module_size > loc_size) { printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n", - module_size, loc_size); + module_size, loc_size); return -1; } @@ -374,13 +374,13 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); + num_cores, num_threads); max_cpus = num_threads; *total_hw_threads = num_threads; if (num_threads > CONFIG_MAX_CPUS) { printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n", - num_threads, CONFIG_MAX_CPUS); + num_threads, CONFIG_MAX_CPUS); max_cpus = CONFIG_MAX_CPUS; } @@ -411,7 +411,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) } int setup_ap_init(struct bus *cpu_bus, int *max_cpus, - const void *microcode_patch) + const void *microcode_patch) { int num_cpus; int hw_threads; @@ -427,8 +427,8 @@ int setup_ap_init(struct bus *cpu_bus, int *max_cpus, if (num_cpus < hw_threads) { printk(BIOS_CRIT, - "ERROR: More HW threads (%d) than support (%d).\n", - hw_threads, num_cpus); + "ERROR: More HW threads (%d) than support (%d).\n", + hw_threads, num_cpus); return -1; } @@ -465,7 +465,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) if (sipi_vector > 256) { printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n", - sipi_vector); + sipi_vector); return -1; } @@ -483,7 +483,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) /* Send INIT IPI to all but self. */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_INIT); + LAPIC_DM_INIT); printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); @@ -499,7 +499,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "timed out.\n"); @@ -522,7 +522,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "timed out.\n"); @@ -534,7 +534,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) /* Wait for CPUs to check in. */ if (wait_for_aps(&num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", - atomic_read(&num_aps), ap_count); + atomic_read(&num_aps), ap_count); return -1; } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 757cc34..e79163b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -81,7 +81,7 @@ static unsigned long choose_top_of_stack(void) #if CONFIG_DYNAMIC_CBMEM /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); + ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; #else stack_top = ROMSTAGE_STACK; @@ -172,8 +172,8 @@ void * asmlinkage romstage_main(unsigned long bist) const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); printk(BIOS_DEBUG, "Setting up stack guards.\n"); for (i = 0; i < num_guards; i++) @@ -316,8 +316,8 @@ void romstage_after_car(void) #if CONFIG_RELOCATABLE_RAMSTAGE void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, - void *entry_point) + const struct cbmem_entry *ramstage, + void *entry_point) { struct ramstage_cache *cache; uint32_t total_size; @@ -333,7 +333,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, total_size = sizeof(*cache) + ramstage_size; if (total_size > RESERVED_SMM_SIZE) { printk(BIOS_DEBUG, "0x%08x > RESERVED_SMM_SIZE (0x%08x)\n", - total_size, RESERVED_SMM_SIZE); + total_size, RESERVED_SMM_SIZE); /* Nuke whatever may be there now just in case. */ cache->magic = ~RAMSTAGE_CACHE_MAGIC; return; @@ -356,7 +356,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, } void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) + const struct cbmem_entry *ramstage) { struct ramstage_cache *cache; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3f4f45a..785a18a 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -37,10 +37,10 @@ #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 #define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) +#define SMM_CPU_SAVE_EN (1 << 1) /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 @@ -71,7 +71,7 @@ static struct smm_relocation_params smm_reloc_params; static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); } @@ -79,7 +79,7 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) static inline void write_emrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); + relo_params->emrr_base.lo, relo_params->emrr_mask.lo); wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); } @@ -87,16 +87,16 @@ static inline void write_emrr(struct smm_relocation_params *relo_params) static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, - struct smm_relocation_params *relo_params, - const struct smm_runtime *runtime) + struct smm_relocation_params *relo_params, + const struct smm_runtime *runtime) { u32 smbase; u32 iedbase; @@ -108,7 +108,7 @@ static void update_save_state(int cpu, iedbase = relo_params->ied_base; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); + smbase, iedbase); /* All threads need to set IEDBASE and SMBASE to the relocated * handler region. However, the save state location depends on the @@ -136,7 +136,7 @@ static void update_save_state(int cpu, em64t101_smm_state_save_area_t *save_state; save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); + runtime->save_state_size); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -172,7 +172,7 @@ cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime) if (cpu >= CONFIG_MAX_CPUS) { printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); + "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } @@ -230,7 +230,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) } static void fill_in_relocation_params(device_t dev, - struct smm_relocation_params *params) + struct smm_relocation_params *params) { u32 tseg_size; u32 tsegmb; @@ -282,7 +282,7 @@ static void fill_in_relocation_params(device_t dev, params->uncore_emrr_base.lo = emrr_base; params->uncore_emrr_base.hi = 0; params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRRphysMaskValid; + MTRRphysMaskValid; params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } @@ -303,7 +303,7 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params) } static int install_relocation_handler(int num_cpus, - struct smm_relocation_params *relo_params) + struct smm_relocation_params *relo_params) { /* The default SMM entry can happen in parallel or serially. If the * default SMM entry is done in parallel the BSP has already setup @@ -354,7 +354,7 @@ static void setup_ied_area(struct smm_relocation_params *params) } static int install_permanent_handler(int num_cpus, - struct smm_relocation_params *relo_params) + struct smm_relocation_params *relo_params) { /* There are num_cpus concurrent stacks and num_cpus concurrent save * state areas. Lastly, set the stack size to the save state size. */ @@ -367,9 +367,9 @@ static int install_permanent_handler(int num_cpus, }; printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); + relo_params->smram_base); if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) + relo_params->smram_size, &smm_params)) return -1; adjust_apic_id_map(&smm_params); @@ -395,8 +395,8 @@ static int cpu_smm_setup(void) num_cpus = msr.lo & 0xffff; if (num_cpus > CONFIG_MAX_CPUS) { printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); } if (install_relocation_handler(num_cpus, &smm_reloc_params)) { diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1991ed8..44179be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -127,8 +127,8 @@ const void *intel_microcode_find(void) microcode_updates = walkcbfs((char *) MICROCODE_CBFS_FILE); #else microcode_updates = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE); + MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE); #endif if (!microcode_updates) @@ -250,9 +250,9 @@ void intel_update_microcode(const void *microcode_updates) #if !defined(__ROMCC__) printk(BIOS_DEBUG, "microcode: updated to revision " - "0x%x date=%04x-%02x-%02x\n", new_rev, - m->date & 0xffff, (m->date >> 24) & 0xff, - (m->date >> 16) & 0xff); + "0x%x date=%04x-%02x-%02x\n", new_rev, + m->date & 0xffff, (m->date >> 24) & 0xff, + (m->date >> 16) & 0xff); #endif break; } diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh index febf6f9..17023ab 100755 --- a/src/cpu/intel/microcode/update-microcodes.sh +++ b/src/cpu/intel/microcode/update-microcodes.sh @@ -45,12 +45,12 @@ separate_microcode() { perl -pi -e 's,^,/,g' header.inc perl -pi -e 's,^//\*,/\*,' header.inc for i in xx????; do - name="`head -1 $i`" - name=${name%??} - name=${name:2} - name=$( echo $name ) - name=microcode-${name%.inc}.h - cat header.inc $i > $name + name="`head -1 $i`" + name=${name%??} + name=${name:2} + name=$( echo $name ) + name=microcode-${name%.inc}.h + cat header.inc $i > $name done rm -f xx???? header.inc } @@ -73,7 +73,7 @@ dump_cpuids() { move_microcode() { printf "Moving microcode...\n" dump_cpuids | sort | while read N; do - ID=$( echo $N | cut -d: -f1 ) + ID=$( echo $N | cut -d: -f1 ) F=$( echo $N | cut -d: -f2 ) if [ -d ../model_$ID ]; then @@ -82,15 +82,15 @@ move_microcode() { else ID2=${ID%?}x if [ -d ../model_$ID2 ]; then - echo "Model: $ID($ID2) Microcode: $F (copied)" + echo "Model: $ID($ID2) Microcode: $F (copied)" mv $F ../model_$ID2/$F - else - ID1=${ID%??}xx + else + ID1=${ID%??}xx if [ -d ../model_$ID1 ]; then - echo "Model: $ID($ID1) Microcode: $F (copied)" + echo "Model: $ID($ID1) Microcode: $F (copied)" mv $F ../model_$ID1/$F else - echo "Model: $ID Microcode: $F (erased)" + echo "Model: $ID Microcode: $F (erased)" rm -f $F fi fi diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 47d87de..f3ee2f7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -48,10 +48,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-mA01067AA0B.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void init_timer(void) @@ -375,7 +375,7 @@ static void model_1067x_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_1067x_init, + .init = model_1067x_init, }; static struct cpu_device_id cpu_table[] = { @@ -386,7 +386,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e0aa120..d4759d5 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -41,10 +41,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-M10106CA107.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; #define IA32_FEATURE_CONTROL 0x003a @@ -164,7 +164,7 @@ static void model_106cx_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_106cx_init, + .init = model_106cx_init, }; static struct cpu_device_id cpu_table[] = { @@ -173,7 +173,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index fa0dc95..9bf2b6f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -325,7 +325,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package); for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index dce0e39..7a689ed 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -107,16 +107,16 @@ clear_var_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr /* Clear the cache memory region. This will also fill up the cache */ @@ -128,9 +128,9 @@ clear_var_mtrrs: rep stosl /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr post_code(0x26) @@ -146,8 +146,8 @@ clear_var_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr @@ -198,16 +198,16 @@ before_romstage: post_code(0x31) /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr invd /* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr post_code(0x33) diff --git a/src/cpu/intel/model_2065x/microcode_blob.h b/src/cpu/intel/model_2065x/microcode_blob.h index 1da40d9..d1ddd39 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.h +++ b/src/cpu/intel/model_2065x/microcode_blob.h @@ -20,7 +20,7 @@ #include "microcode-m9220655_00000003.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 0fd1bf0..09bc42a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -311,7 +311,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); } static void set_energy_perf_bias(u8 policy) @@ -326,7 +326,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); + policy); #endif } @@ -362,8 +362,8 @@ static void intel_cores_init(device_t cpu) return; printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); + cpu->path.apic.apic_id, threads_per_package/threads_per_core, + threads_per_core); for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; @@ -384,15 +384,15 @@ static void intel_cores_init(device_t cpu) continue; printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); + cpu->path.apic.apic_id, + new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* Start the new cpu */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); + new->path.apic.apic_id); } #endif } @@ -452,7 +452,7 @@ static void model_2065x_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_2065x_init, + .init = model_2065x_init, }; static struct cpu_device_id cpu_table[] = { @@ -461,7 +461,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 80ed4ba..acee536 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -328,7 +328,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package); for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index b4119cc..88d224b 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -28,9 +28,9 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) @@ -97,16 +97,16 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr /* Clear the cache memory region. This will also fill up the cache */ @@ -118,9 +118,9 @@ clear_mtrrs: rep stosl /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr post_code(0x26) @@ -136,8 +136,8 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr @@ -200,16 +200,16 @@ before_romstage: post_code(0x31) /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr invd /* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr #if CONFIG_CACHE_MRC_BIN diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h index 10865ab..28a4264 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.h +++ b/src/cpu/intel/model_206ax/microcode_blob.h @@ -21,7 +21,7 @@ #include "microcode-m12306a9_00000017.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 6028801..f1e9efd 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -447,7 +447,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } static void set_energy_perf_bias(u8 policy) @@ -461,7 +461,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); + policy); } static void configure_mca(void) @@ -496,8 +496,8 @@ static void intel_cores_init(device_t cpu) return; printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); + cpu->path.apic.apic_id, threads_per_package/threads_per_core, + threads_per_core); for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; @@ -518,15 +518,15 @@ static void intel_cores_init(device_t cpu) continue; printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); + cpu->path.apic.apic_id, + new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* Start the new cpu */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); + new->path.apic.apic_id); } #endif } @@ -591,7 +591,7 @@ static void model_206ax_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_206ax_init, + .init = model_206ax_init, }; static struct cpu_device_id cpu_table[] = { @@ -609,7 +609,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 285bacd..90423f3 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -73,7 +73,7 @@ static void model_65x_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_65x_init, + .init = model_65x_init, }; /* @@ -95,6 +95,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_67x/microcode-293-MU267114.h b/src/cpu/intel/model_67x/microcode-293-MU267114.h index 39d6c88..838ee63 100644 --- a/src/cpu/intel/model_67x/microcode-293-MU267114.h +++ b/src/cpu/intel/model_67x/microcode-293-MU267114.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-530-MU16730e.h b/src/cpu/intel/model_67x/microcode-530-MU16730e.h index ae070ad..54bc965 100644 --- a/src/cpu/intel/model_67x/microcode-530-MU16730e.h +++ b/src/cpu/intel/model_67x/microcode-530-MU16730e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-531-MU26732e.h b/src/cpu/intel/model_67x/microcode-531-MU26732e.h index 40e7bd2..c6e690d 100644 --- a/src/cpu/intel/model_67x/microcode-531-MU26732e.h +++ b/src/cpu/intel/model_67x/microcode-531-MU26732e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-539-MU167210.h b/src/cpu/intel/model_67x/microcode-539-MU167210.h index 232ad7e..7b11bd9 100644 --- a/src/cpu/intel/model_67x/microcode-539-MU167210.h +++ b/src/cpu/intel/model_67x/microcode-539-MU167210.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-540-MU267238.h b/src/cpu/intel/model_67x/microcode-540-MU267238.h index aa30219..376828a 100644 --- a/src/cpu/intel/model_67x/microcode-540-MU267238.h +++ b/src/cpu/intel/model_67x/microcode-540-MU267238.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 3ebe361..a4e0a07 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -63,7 +63,7 @@ static void model_67x_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_67x_init, + .init = model_67x_init, }; /* @@ -82,6 +82,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_68x/microcode-534-MU16810d.h b/src/cpu/intel/model_68x/microcode-534-MU16810d.h index 8ecf059..6479ace 100644 --- a/src/cpu/intel/model_68x/microcode-534-MU16810d.h +++ b/src/cpu/intel/model_68x/microcode-534-MU16810d.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-535-MU16810e.h b/src/cpu/intel/model_68x/microcode-535-MU16810e.h index 02da11e..683b42e 100644 --- a/src/cpu/intel/model_68x/microcode-535-MU16810e.h +++ b/src/cpu/intel/model_68x/microcode-535-MU16810e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-536-MU16810f.h b/src/cpu/intel/model_68x/microcode-536-MU16810f.h index 9d31fc6..013b77d 100644 --- a/src/cpu/intel/model_68x/microcode-536-MU16810f.h +++ b/src/cpu/intel/model_68x/microcode-536-MU16810f.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-537-MU268110.h b/src/cpu/intel/model_68x/microcode-537-MU268110.h index 6acfe79..4490e62 100644 --- a/src/cpu/intel/model_68x/microcode-537-MU268110.h +++ b/src/cpu/intel/model_68x/microcode-537-MU268110.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-538-MU168111.h b/src/cpu/intel/model_68x/microcode-538-MU168111.h index 38558cb..912e6fc 100644 --- a/src/cpu/intel/model_68x/microcode-538-MU168111.h +++ b/src/cpu/intel/model_68x/microcode-538-MU168111.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-550-MU168307.h b/src/cpu/intel/model_68x/microcode-550-MU168307.h index 616c2ef..946a749 100644 --- a/src/cpu/intel/model_68x/microcode-550-MU168307.h +++ b/src/cpu/intel/model_68x/microcode-550-MU168307.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-551-MU168308.h b/src/cpu/intel/model_68x/microcode-551-MU168308.h index 5424136..4701269 100644 --- a/src/cpu/intel/model_68x/microcode-551-MU168308.h +++ b/src/cpu/intel/model_68x/microcode-551-MU168308.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-611-MU168607.h b/src/cpu/intel/model_68x/microcode-611-MU168607.h index 201561a..1202cbd 100644 --- a/src/cpu/intel/model_68x/microcode-611-MU168607.h +++ b/src/cpu/intel/model_68x/microcode-611-MU168607.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-612-MU168608.h b/src/cpu/intel/model_68x/microcode-612-MU168608.h index 905f38f..4aee463 100644 --- a/src/cpu/intel/model_68x/microcode-612-MU168608.h +++ b/src/cpu/intel/model_68x/microcode-612-MU168608.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-615-MU16860a.h b/src/cpu/intel/model_68x/microcode-615-MU16860a.h index a4d1cc2..913eae9 100644 --- a/src/cpu/intel/model_68x/microcode-615-MU16860a.h +++ b/src/cpu/intel/model_68x/microcode-615-MU16860a.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-617-MU16860c.h b/src/cpu/intel/model_68x/microcode-617-MU16860c.h index 09a4cb0..f07cdcf 100644 --- a/src/cpu/intel/model_68x/microcode-617-MU16860c.h +++ b/src/cpu/intel/model_68x/microcode-617-MU16860c.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-618-MU268602.h b/src/cpu/intel/model_68x/microcode-618-MU268602.h index d8a294a..7df8006 100644 --- a/src/cpu/intel/model_68x/microcode-618-MU268602.h +++ b/src/cpu/intel/model_68x/microcode-618-MU268602.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-662-MU168a01.h b/src/cpu/intel/model_68x/microcode-662-MU168a01.h index dd01df9..9d16f87 100644 --- a/src/cpu/intel/model_68x/microcode-662-MU168a01.h +++ b/src/cpu/intel/model_68x/microcode-662-MU168a01.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-691-MU168a04.h b/src/cpu/intel/model_68x/microcode-691-MU168a04.h index 0d0c055..975f181 100644 --- a/src/cpu/intel/model_68x/microcode-691-MU168a04.h +++ b/src/cpu/intel/model_68x/microcode-691-MU168a04.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-692-MU168a05.h b/src/cpu/intel/model_68x/microcode-692-MU168a05.h index d4e39bb..b001374 100644 --- a/src/cpu/intel/model_68x/microcode-692-MU168a05.h +++ b/src/cpu/intel/model_68x/microcode-692-MU168a05.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-727-MU168313.h b/src/cpu/intel/model_68x/microcode-727-MU168313.h index 7531eea..fd3a2d2 100644 --- a/src/cpu/intel/model_68x/microcode-727-MU168313.h +++ b/src/cpu/intel/model_68x/microcode-727-MU168313.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-728-MU168314.h b/src/cpu/intel/model_68x/microcode-728-MU168314.h index f6e4efb..35957f3 100644 --- a/src/cpu/intel/model_68x/microcode-728-MU168314.h +++ b/src/cpu/intel/model_68x/microcode-728-MU168314.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-729-MU268310.h b/src/cpu/intel/model_68x/microcode-729-MU268310.h index 3f63b40..10e6160 100644 --- a/src/cpu/intel/model_68x/microcode-729-MU268310.h +++ b/src/cpu/intel/model_68x/microcode-729-MU268310.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index c4bd7ac..ae18f59 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -52,10 +52,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-691-MU168a04.h" #include "microcode-692-MU168a05.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_68x_init(device_t cpu) @@ -81,7 +81,7 @@ static void model_68x_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_68x_init, + .init = model_68x_init, }; /* @@ -108,7 +108,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index cb805ae..394c9be 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -15,10 +15,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1374-m2069507.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_69x_init(device_t dev) @@ -36,7 +36,7 @@ static void model_69x_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_69x_init, + .init = model_69x_init, }; static struct cpu_device_id cpu_table[] = { @@ -46,6 +46,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b7affd9..4fb5196 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -38,10 +38,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-875-MU16b401.h" #include "microcode-885-MU16b402.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_6bx_init(device_t cpu) @@ -67,7 +67,7 @@ static void model_6bx_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_6bx_init, + .init = model_6bx_init, }; /* @@ -84,7 +84,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 19b351d..9f5479c 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -13,10 +13,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1355-m206d618.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_6dx_init(device_t dev) @@ -34,7 +34,7 @@ static void model_6dx_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_6dx_init, + .init = model_6dx_init, }; static struct cpu_device_id cpu_table[] = { @@ -44,6 +44,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index e9c63da..ed52af9 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -38,10 +38,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-1729-m206ec54.h" #include "microcode-1869-m806ec59.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; #define IA32_FEATURE_CONTROL 0x003a @@ -190,7 +190,7 @@ static void model_6ex_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_6ex_init, + .init = model_6ex_init, }; static struct cpu_device_id cpu_table[] = { @@ -201,7 +201,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index faf1277..c438412 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -54,10 +54,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-m806fda4.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; #define IA32_FEATURE_CONTROL 0x003a @@ -105,7 +105,7 @@ static void configure_c_states(void) msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 3); // Dynamic L2 - /* Number of supported C-States */ + /* Number of supported C-States */ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 @@ -230,7 +230,7 @@ static void model_6fx_init(device_t cpu) } static struct device_operations cpu_dev_ops = { - .init = model_6fx_init, + .init = model_6fx_init, }; static struct cpu_device_id cpu_table[] = { @@ -246,7 +246,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 5724add..795d5a4 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -37,10 +37,10 @@ static uint32_t microcode_updates[] = { #include "microcode-620-MU26a401.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_6xx_init(device_t dev) @@ -58,7 +58,7 @@ static void model_6xx_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_6xx_init, + .init = model_6xx_init, }; /* @@ -113,6 +113,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ed12b6e..042ffba 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -18,10 +18,10 @@ static uint32_t microcode_updates[] = { #include "microcode-966-m04f0a14.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_f0x_init(device_t dev) @@ -39,7 +39,7 @@ static void model_f0x_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_f0x_init, + .init = model_f0x_init, }; static struct cpu_device_id cpu_table[] = { @@ -49,6 +49,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index feb8410..ad44bff 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -21,10 +21,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1072-m04f1305.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_f1x_init(device_t dev) @@ -42,7 +42,7 @@ static void model_f1x_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_f1x_init, + .init = model_f1x_init, }; static struct cpu_device_id cpu_table[] = { @@ -52,6 +52,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 8fd8abc..acbf28f 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -38,10 +38,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1106-m02f241f.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_f2x_init(device_t cpu) @@ -66,7 +66,7 @@ static void model_f2x_init(device_t cpu) }; static struct device_operations cpu_dev_ops = { - .init = model_f2x_init, + .init = model_f2x_init, }; static struct cpu_device_id cpu_table[] = { @@ -80,6 +80,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9..e0882be 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -21,10 +21,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1468-m1df3417.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_f3x_init(device_t cpu) @@ -58,6 +58,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver model_f3x __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2a..71e6093 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -29,10 +29,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1498-m5df4a02.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; static void model_f4x_init(device_t cpu) @@ -66,6 +66,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver model_f4x __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index a974d24..7e3f45a 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -64,9 +64,9 @@ Cache latency to be written to L2 -----++++ control register |||| 0000 xx 00 -----> 000 cccc 0 -|||| 00 66MHz -|||| 10 100MHz -|||| 01 133MHz (Katmai "B" only) +|||| 00 66MHz +|||| 10 100MHz +|||| 01 133MHz (Katmai "B" only) ++++------ CPU frequency multiplier 0000 2x @@ -344,7 +344,7 @@ int test_l2_address_alias(u32 address1, u32 address2, /* Calculates the L2 cache size. * * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual - * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. + * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. * */ int calculate_l2_cache_size(void) @@ -696,7 +696,7 @@ int p6_configure_l2_cache(void) if (v >= 0 && (v & 0x20)) { bblctl3 = rdmsr(BBL_CR_CTL3); bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE | - BBLCR3_L2_CRTN_PARITY_ENABLE); + BBLCR3_L2_CRTN_PARITY_ENABLE); wrmsr(BBL_CR_CTL3, bblctl3); } @@ -756,7 +756,7 @@ int p6_configure_l2_cache(void) */ if (signal_l2(cache_size, 0, 0, v, L2CMD_TWW | L2CMD_MESI_I) != 0) { printk(BIOS_ERR, "Failed on signal_l2(%x, %x)\n", - cache_size, v); + cache_size, v); goto bad; } } diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 62bd17b..1df55e6 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,6 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool - select CPU_INTEL_MODEL_6FX + select CPU_INTEL_MODEL_6FX select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 483e813..9d6bb25 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -78,13 +78,13 @@ static int get_fsb(void) case 6: return 1200; /* / 3 == 400 */ } printk(BIOS_WARNING, - "Warning: No supported FSB frequency. Assuming 200MHz\n"); + "Warning: No supported FSB frequency. Assuming 200MHz\n"); return 600; } static int gen_pstate_entries(const sst_table_t *const pstates, - const int cpuID, const int cores_per_package, - const uint8_t coordination) + const int cpuID, const int cores_per_package, + const uint8_t coordination) { int i; int len, len_ps; @@ -100,13 +100,13 @@ static int gen_pstate_entries(const sst_table_t *const pstates, pstates->states[pstates->num_states - 1]); const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", - (min_ratio2 * fsb3) + (min_ratio2 * fsb3) / (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6), - (max_ratio2 * fsb3) / 6); + (max_ratio2 * fsb3) / 6); printk(BIOS_DEBUG, "adding %x P-States between " "busratio %x and %x, ""incl. P0\n", - pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); + pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); len_ps = acpigen_write_package(pstates->num_states); for (i = 0; i < pstates->num_states; ++i) { const sst_state_t *const pstate = &pstates->states[i]; @@ -144,15 +144,15 @@ void generate_cpu_entries(void) int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; int numcpus = totalcores/cores_per_package; /* This assumes that all - CPUs share the same - layout. */ + CPUs share the same + layout. */ int num_cstates; acpi_cstate_t *cstates; sst_table_t pstates; uint8_t coordination; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package); num_cstates = get_cst_entries(&cstates); speedstep_gen_pstates(&pstates); diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index f2cff04..caf4d33 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -171,9 +171,9 @@ void speedstep_gen_pstates(sst_table_t *const table) /* Now, add all other normal states based on LFM (min). */ const int power_step = (power_diff2 / states) / 2; const int vid_step = (vid_diff2 / states) / 2; - const int ratio_step = step2 / 2; + const int ratio_step = step2 / 2; int power = params.min.power + (states - 1) * power_step; - int vid = params.min.vid + (states - 1) * vid_step; + int vid = params.min.vid + (states - 1) * vid_step; int ratio = params.min.ratio + (states - 1) * ratio_step; for (; states > 0; --states) { table->states[table->num_states++] = diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index c27a1ee..607080b 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -28,7 +28,7 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 73fd3c5..797d69a 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -55,6 +55,6 @@ ramstage-y += fb.c ramstage-y += usb.c exynos5250_add_bl1: $(obj)/coreboot.pre - printf " DD Adding Samsung Exynos5250 BL1\n" + printf " DD Adding Samsung Exynos5250 BL1\n" dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 565cf2b..e82a494 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -43,7 +43,7 @@ enum pll_src_bit { * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { - s8 src_bit; /* offset in register to clock source field */ + s8 src_bit; /* offset in register to clock source field */ s8 n_src_bits; /* number of bits in 'src_bit' field */ s8 div_bit; s8 prediv_bit; diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 390fae3..ad1aaae 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -27,7 +27,7 @@ #include "periph.h" /* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_CLK_FREQ 24000000 static struct arm_clk_ratios arm_clk_ratios[] = { { @@ -435,7 +435,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -472,7 +472,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -559,7 +559,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return -1; } diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 61f937b..db759d1 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -116,7 +116,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); + "Initializing Exynos VGA, base %p\n", (void *)lcdbase); ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } @@ -144,10 +144,10 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, - .set_resources = cpu_noop, + .set_resources = cpu_noop, .enable_resources = cpu_enable, - .init = cpu_init, - .scan_bus = 0, + .init = cpu_init, + .scan_bus = 0, }; static void enable_exynos5250_dev(device_t dev) @@ -165,9 +165,9 @@ void exynos5250_config_l2_cache(void) uint32_t val; /* - * Bit 9 - L2 tag RAM setup (1 cycle) + * Bit 9 - L2 tag RAM setup (1 cycle) * Bits 8:6 - L2 tag RAM latency (3 cycles) - * Bit 5 - L2 data RAM setup (1 cycle) + * Bit 5 - L2 data RAM setup (1 cycle) * Bits 2:0 - L2 data RAM latency (3 cycles) */ val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 63f17e2..ba6cd8c 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -52,7 +52,7 @@ #define EXYNOS5_TZPC1_DECPROT1SET 0x10110810 #define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_GPIO_PART4_BASE 0x10D10000 /* V00..V37 */ diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index acd0abb..436252c 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -273,7 +273,7 @@ struct mem_timings { uint8_t bpll_mdiv; uint8_t bpll_pdiv; uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ uint8_t pclk_cdrex_ratio; unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index b506853..5696ced 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -134,14 +134,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + &dmc->directcmd); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + &dmc->directcmd); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 554f4c2..667edee 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -54,7 +54,7 @@ static void reset_phy_ctrl(void) } int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset) + int mem_reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -76,7 +76,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Set Impedance Output Driver */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n", - mem->impedance); + mem->impedance); val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | @@ -87,7 +87,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Set Read Latency and Burst Length for PHY0 and PHY1 */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set Read Latency and Burst Length for PHY0 and PHY1\n"); + "Set Read Latency and Burst Length for PHY0 and PHY1\n"); val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); writel(val, &phy0_ctrl->phy_con42); @@ -141,7 +141,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Memory Channel Interleaving Size */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Memory Channel Interleaving Size\n"); + "Memory Channel Interleaving Size\n"); writel(mem->iv_size, &dmc->ivcontrol); /* Set DMC MEMCONTROL register */ @@ -161,7 +161,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Power Down mode Configuration */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Power Down mode Configuration\n"); + "Power Down mode Configuration\n"); writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, &dmc->pwrdnconfig); @@ -170,7 +170,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, * values as per Memory AC parameters */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "TimingRow, TimingData, TimingPower and Timingaref\n"); + "TimingRow, TimingData, TimingPower and Timingaref\n"); writel(mem->timing_ref, &dmc->timingref); writel(mem->timing_row, &dmc->timingrow); writel(mem->timing_data, &dmc->timingdata); @@ -270,7 +270,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Set DMC Concontrol and enable auto-refresh counter */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set DMC Concontrol and enable auto-refresh counter\n"); + "Set DMC Concontrol and enable auto-refresh counter\n"); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); return 0; diff --git a/src/cpu/samsung/exynos5250/dp.h b/src/cpu/samsung/exynos5250/dp.h index 5c778ba..11b9d00 100644 --- a/src/cpu/samsung/exynos5250/dp.h +++ b/src/cpu/samsung/exynos5250/dp.h @@ -425,8 +425,8 @@ struct exynos5_dp { #define VIDEO_MODE_SLAVE_MODE (1 << 0) #define VIDEO_MODE_MASTER_MODE (0 << 0) -#define HW_TRAINING_ERROR_CODE (7<<4) -#define HW_TRAINING_EN (1<<0) +#define HW_TRAINING_ERROR_CODE (7<<4) +#define HW_TRAINING_EN (1<<0) /* I2C EDID Chip ID, Slave Address */ #define I2C_EDID_DEVICE_ADDR 0x50 diff --git a/src/cpu/samsung/exynos5250/dsim.h b/src/cpu/samsung/exynos5250/dsim.h index b9245d3..b2134a9 100644 --- a/src/cpu/samsung/exynos5250/dsim.h +++ b/src/cpu/samsung/exynos5250/dsim.h @@ -103,7 +103,7 @@ struct exynos5_dsim { #define PLL_STABLE (1 << 31) #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10) #endif diff --git a/src/cpu/samsung/exynos5250/fb.c b/src/cpu/samsung/exynos5250/fb.c index 760f5ee..06e6ae6 100644 --- a/src/cpu/samsung/exynos5250/fb.c +++ b/src/cpu/samsung/exynos5250/fb.c @@ -187,7 +187,7 @@ void exynos_fimd_disable(void) * return status */ static int s5p_dp_config_video(struct s5p_dp_device *dp, - struct video_info *video_info) + struct video_info *video_info) { int timeout = 0; struct exynos5_dp *base = dp->base; @@ -195,9 +195,9 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, s5p_dp_config_video_slave_mode(dp, video_info); s5p_dp_set_video_color_format(dp, video_info->color_depth, - video_info->color_space, - video_info->dynamic_range, - video_info->ycbcr_coeff); + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { printk(BIOS_DEBUG, "PLL is not locked yet.\n"); @@ -258,8 +258,8 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) return -ERR_DPCD_READ_ERROR1; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, - DPCD_ENHANCED_FRAME_EN | - (data & DPCD_LANE_COUNT_SET_MASK))) { + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR1; } @@ -280,13 +280,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - &data)) { + &data)) { printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR2; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR2; } @@ -334,7 +334,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) * return status */ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, - int pre_emphasis, int lane) + int pre_emphasis, int lane) { u32 reg; struct exynos5_dp *base = dp->base; @@ -439,7 +439,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) if (s5p_dp_set_lane_lane_pre_emphasis(dp, - PRE_EMPHASIS_LEVEL_0, lane)) { + PRE_EMPHASIS_LEVEL_0, lane)) { printk(BIOS_DEBUG, "Unable to set pre emphasis level\n"); return -ERR_PRE_EMPHASIS_LEVELS; } @@ -457,14 +457,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", - dp->link_train.link_rate); + dp->link_train.link_rate); /* Not Retrying */ return -ERR_LINK_RATE_ABNORMAL; } if (dp->link_train.lane_count == 0) { printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n", - dp->link_train.lane_count); + dp->link_train.lane_count); /* Not retrying */ return -ERR_MAX_LANE_COUNT_ABNORMAL; } @@ -529,7 +529,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) } ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + dp->video_info->link_rate); if (ret) { printk(BIOS_ERR, "unable to do link train\n"); return ret; diff --git a/src/cpu/samsung/exynos5250/gpio.c b/src/cpu/samsung/exynos5250/gpio.c index 2a93328..f58d002 100644 --- a/src/cpu/samsung/exynos5250/gpio.c +++ b/src/cpu/samsung/exynos5250/gpio.c @@ -53,7 +53,7 @@ static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { }; /* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) +#define GPIO_BIT(x) ((x) & 0x7) static struct gpio_bank *gpio_get_bank(unsigned int gpio) { diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h index 0b97526..0cd9e3d 100644 --- a/src/cpu/samsung/exynos5250/gpio.h +++ b/src/cpu/samsung/exynos5250/gpio.h @@ -493,7 +493,7 @@ void gpio_set_rate(int gpio, int mode); * * @param gpio GPIO to read * @return -1 if the value cannot be determined. Otherwise returns - * the corresponding MVL3 enum value. + * the corresponding MVL3 enum value. */ int gpio_read_mvl3(unsigned gpio); @@ -563,11 +563,11 @@ int gpio_set_value(unsigned gpio, int value); * * Vpd | Vpu | MVL * ----------------- - * 0 | 0 | 0 + * 0 | 0 | 0 * ----------------- - * 0 | 1 | Z <-- floating input will follow internal pull up/down + * 0 | 1 | Z <-- floating input will follow internal pull up/down * ----------------- - * 1 | 1 | 1 + * 1 | 1 | 1 */ enum mvl3 { LOGIC_0, diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h index f349e53..84a3b13 100644 --- a/src/cpu/samsung/exynos5250/power.h +++ b/src/cpu/samsung/exynos5250/power.h @@ -35,9 +35,9 @@ void power_enable_hw_thermal_trip(void); #define DPTX_PHY_ENABLE (1 << 0) /* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ -#define PMU_DEBUG_XXTI 0x1000 +#define PMU_DEBUG_XXTI 0x1000 /* Mask bit[12:8] for xxti clock selection */ -#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 /* Power Management Unit register map */ struct exynos5_power { @@ -55,7 +55,7 @@ struct exynos5_power { uint32_t inform1; /* 0x0804 */ uint8_t reserved6[0x1f8]; uint32_t pmu_debug; /* 0x0A00*/ - uint8_t reserved7[0x2908]; + uint8_t reserved7[0x2908]; uint32_t ps_hold_ctrl; /* 0x330c */ } __attribute__ ((__packed__)); diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 9f10786..fa258fc 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -42,7 +42,7 @@ struct exynos5_phy_control; #define APLL_CON1_VAL (0x00203800) /* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) +#define MPLL_CON1_VAL (0x00203800) /* CPLL_CON1 */ #define CPLL_CON1_VAL (0x00203800) @@ -66,11 +66,11 @@ struct exynos5_phy_control; /* CLK_SRC_CPU */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ | (MUX_CPU_SEL << 16) \ | (MUX_APLL_SEL)) @@ -81,46 +81,46 @@ struct exynos5_phy_control; #define DMC_MEMCONTROL_TP_DISABLE (0 << 4) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) -#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) +#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8) #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) -#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) -#define DMC_MEMCONTROL_BL_8 (3 << 20) -#define DMC_MEMCONTROL_BL_4 (2 << 20) +#define DMC_MEMCONTROL_BL_8 (3 << 20) +#define DMC_MEMCONTROL_BL_4 (2 << 20) -#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) +#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) -#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) /* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) - -#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) -#define DMC_MEMBASECONFIG_VAL(x) ( \ - DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ - DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ +#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) + +#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMBASECONFIG_VAL(x) ( \ + DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ + DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ ) #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) -#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF +#define DMC_PRECHCONFIG_VAL 0xFF000000 +#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 #define DFI_INIT_START (1 << 28) @@ -147,55 +147,55 @@ struct exynos5_phy_control; #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) /* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ +#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ + | (APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (ACP_RATIO << 8) \ + | (CPUD_RATIO << 4) \ | (ARM_RATIO)) /* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define CLK_SRC_FSYS0_VAL 0x66666 +#define CLK_DIV_FSYS0_VAL 0x0BB00000 /* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x2 -#define COPY_RATIO 0x0 +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0 /* CLK_DIV_CPU1 = 0x00000003 */ -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ | (COPY_RATIO)) /* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00000000 +#define CLK_SRC_CORE0_VAL 0x00000000 /* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 +#define CLK_SRC_CORE1_VAL 0x100 /* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x00120000 +#define CLK_DIV_CORE0_VAL 0x00120000 /* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 +#define CLK_DIV_CORE1_VAL 0x07070700 /* CLK_DIV_SYSRGT */ -#define CLK_DIV_SYSRGT_VAL 0x00000111 +#define CLK_DIV_SYSRGT_VAL 0x00000111 /* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 +#define CLK_DIV_ACP_VAL 0x12 /* CLK_DIV_SYSLFT */ -#define CLK_DIV_SYSLFT_VAL 0x00000311 +#define CLK_DIV_SYSLFT_VAL 0x00000311 /* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x1 +#define CLK_SRC_CDREX_VAL 0x1 /* CLK_DIV_CDREX */ -#define MCLK_CDREX2_RATIO 0x0 -#define ACLK_EFCON_RATIO 0x1 +#define MCLK_CDREX2_RATIO 0x0 +#define ACLK_EFCON_RATIO 0x1 #define MCLK_DPHY_RATIO 0x1 #define MCLK_CDREX_RATIO 0x1 #define ACLK_C2C_200_RATIO 0x1 @@ -203,20 +203,20 @@ struct exynos5_phy_control; #define PCLK_CDREX_RATIO 0x1 #define ACLK_CDREX_RATIO 0x1 -#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ +#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ | (C2C_CLK_400_RATIO << 6) \ | (PCLK_CDREX_RATIO << 4) \ | (ACLK_CDREX_RATIO)) /* CLK_SRC_TOP0 */ -#define MUX_ACLK_300_GSCL_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID_SEL 0x0 -#define MUX_ACLK_400_G3D_MID_SEL 0x0 -#define MUX_ACLK_333_SEL 0x0 -#define MUX_ACLK_300_DISP1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID_SEL 0x0 -#define MUX_ACLK_200_SEL 0x0 -#define MUX_ACLK_166_SEL 0x0 +#define MUX_ACLK_300_GSCL_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID_SEL 0x0 +#define MUX_ACLK_400_G3D_MID_SEL 0x0 +#define MUX_ACLK_333_SEL 0x0 +#define MUX_ACLK_300_DISP1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_ACLK_166_SEL 0x0 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ | (MUX_ACLK_400_G3D_MID_SEL << 20) \ @@ -227,50 +227,50 @@ struct exynos5_phy_control; | (MUX_ACLK_166_SEL << 8)) /* CLK_SRC_TOP1 */ -#define MUX_ACLK_400_G3D_SEL 0x1 -#define MUX_ACLK_400_ISP_SEL 0x0 -#define MUX_ACLK_400_IOP_SEL 0x0 -#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 -#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ - |(MUX_ACLK_400_ISP_SEL << 24) \ - |(MUX_ACLK_400_IOP_SEL << 20) \ +#define MUX_ACLK_400_G3D_SEL 0x1 +#define MUX_ACLK_400_ISP_SEL 0x0 +#define MUX_ACLK_400_IOP_SEL 0x0 +#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 +#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ + |(MUX_ACLK_400_ISP_SEL << 24) \ + |(MUX_ACLK_400_IOP_SEL << 20) \ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ - |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ + |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) /* CLK_SRC_TOP2 */ -#define MUX_GPLL_SEL 0x1 -#define MUX_BPLL_USER_SEL 0x0 -#define MUX_MPLL_USER_SEL 0x0 -#define MUX_VPLL_SEL 0x1 -#define MUX_EPLL_SEL 0x1 -#define MUX_CPLL_SEL 0x1 -#define VPLLSRC_SEL 0x0 +#define MUX_GPLL_SEL 0x1 +#define MUX_BPLL_USER_SEL 0x0 +#define MUX_MPLL_USER_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define MUX_CPLL_SEL 0x1 +#define VPLLSRC_SEL 0x0 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ | (MUX_BPLL_USER_SEL << 24) \ | (MUX_MPLL_USER_SEL << 20) \ - | (MUX_VPLL_SEL << 16) \ - | (MUX_EPLL_SEL << 12) \ - | (MUX_CPLL_SEL << 8) \ + | (MUX_VPLL_SEL << 16) \ + | (MUX_EPLL_SEL << 12) \ + | (MUX_CPLL_SEL << 8) \ | (VPLLSRC_SEL)) /* CLK_SRC_TOP3 */ -#define MUX_ACLK_333_SUB_SEL 0x1 -#define MUX_ACLK_400_SUB_SEL 0x1 -#define MUX_ACLK_266_ISP_SUB_SEL 0x1 -#define MUX_ACLK_266_GPS_SUB_SEL 0x0 -#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 -#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 -#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ - | (MUX_ACLK_400_SUB_SEL << 20) \ +#define MUX_ACLK_333_SUB_SEL 0x1 +#define MUX_ACLK_400_SUB_SEL 0x1 +#define MUX_ACLK_266_ISP_SUB_SEL 0x1 +#define MUX_ACLK_266_GPS_SUB_SEL 0x0 +#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 +#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 +#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ + | (MUX_ACLK_400_SUB_SEL << 20) \ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ - | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ - | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ - | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ - | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ + | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ + | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ + | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ + | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) /* CLK_DIV_TOP0 */ @@ -293,11 +293,11 @@ struct exynos5_phy_control; | (ACLK_66_RATIO)) /* CLK_DIV_TOP1 */ -#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 -#define ACLK_66_PRE_RATIO 0x1 -#define ACLK_400_ISP_RATIO 0x1 -#define ACLK_400_IOP_RATIO 0x1 -#define ACLK_300_GSCL_RATIO 0x2 +#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 +#define ACLK_66_PRE_RATIO 0x1 +#define ACLK_400_ISP_RATIO 0x1 +#define ACLK_400_IOP_RATIO 0x1 +#define ACLK_300_GSCL_RATIO 0x2 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ | (ACLK_66_PRE_RATIO << 24) \ @@ -352,10 +352,10 @@ struct exynos5_phy_control; #define UART1_SEL 6 #define UART0_SEL 6 /* SRC_CLOCK = SCLK_MPLL */ -#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ +#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ | (UART0_SEL)) /* CLK_SRC_PERIC1 */ @@ -387,7 +387,7 @@ struct exynos5_phy_control; #define UART1_RATIO 7 #define UART0_RATIO 7 -#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ +#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ | (UART2_RATIO << 8) \ | (UART1_RATIO << 4) \ | (UART0_RATIO)) @@ -424,25 +424,25 @@ struct exynos5_phy_control; #define MMC3_PRE_RATIO_OFFSET 24 /* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0 /* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10 /* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10 /* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10 /* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 +#define CLK_DIV_ISP0_VAL 0x31 /* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 +#define CLK_DIV_ISP1_VAL 0x0 /* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_DISP1_0 */ #define CLK_SRC_DISP1_0_VAL 0x6 @@ -701,7 +701,7 @@ void mem_ctrl_init(void); * @return 0 if ok, SETUP_ERR_... if there is a problem */ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset); + int mem_reset); /* * Configure ZQ I/O interface diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c index 1c365dc..9d5c4f7 100644 --- a/src/cpu/samsung/exynos5250/spi.c +++ b/src/cpu/samsung/exynos5250/spi.c @@ -36,7 +36,7 @@ #endif static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) + void *dinp, void const *doutp, int i) { int rx_lvl, tx_lvl; unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); @@ -195,8 +195,8 @@ static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, } int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size) { + void *buffer_address, + size_t buffer_size) { // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; DEBUG_SPI("initialize_exynos_spi_cbfs_media\n"); diff --git a/src/cpu/samsung/exynos5250/spi.h b/src/cpu/samsung/exynos5250/spi.h index 7ca3114..a59574d 100644 --- a/src/cpu/samsung/exynos5250/spi.h +++ b/src/cpu/samsung/exynos5250/spi.h @@ -93,6 +93,6 @@ int exynos_spi_close(struct exynos_spi *regs); /* Serve as CBFS media source */ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); + void *buffer_address, + size_t buffer_size); #endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dbf7202..f21f373 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -172,7 +172,7 @@ static void exynos5_uart_tx_flush(void) #if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, + .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, .tx_flush = exynos5_uart_tx_flush, .rx_byte = exynos5_uart_rx_byte, diff --git a/src/cpu/samsung/exynos5250/usb.h b/src/cpu/samsung/exynos5250/usb.h index 45a7b53..3a53bab 100644 --- a/src/cpu/samsung/exynos5250/usb.h +++ b/src/cpu/samsung/exynos5250/usb.h @@ -20,41 +20,41 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_USB_H #define CPU_SAMSUNG_EXYNOS5250_USB_H -#define CLK_24MHZ 5 +#define CLK_24MHZ 5 -#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) -#define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HOST_CTRL0_FSEL_MASK (7 << 16) -#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) /* Register map for PHY control */ struct usb_phy { - uint32_t usbphyctrl0; - uint32_t usbphytune0; - uint32_t reserved1[2]; - uint32_t hsicphyctrl1; - uint32_t hsicphytune1; - uint32_t reserved2[2]; - uint32_t hsicphyctrl2; - uint32_t hsicphytune2; - uint32_t reserved3[2]; - uint32_t ehcictrl; - uint32_t ohcictrl; - uint32_t usbotgsys; - uint32_t reserved4; - uint32_t usbotgtune; + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; }; void usb_init(device_t dev); diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 8540409..bce86ed 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -55,6 +55,6 @@ ramstage-y += fb.c ramstage-y += usb.c exynos5420_add_bl1: $(obj)/coreboot.pre - printf " DD Adding Samsung Exynos5420 BL1\n" + printf " DD Adding Samsung Exynos5420 BL1\n" dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index 8e2f9ed..12a9565 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -49,7 +49,7 @@ enum pll_src_bit { * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { - s8 src_bit; /* offset in register to clock source field */ + s8 src_bit; /* offset in register to clock source field */ s8 div_bit; s8 prediv_bit; }; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 8c4baf8..b860b72 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -27,7 +27,7 @@ #include "periph.h" /* input clock of PLL: SMDK5420 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_CLK_FREQ 24000000 /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { @@ -304,7 +304,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -340,7 +340,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -427,7 +427,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return -1; } diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 744f7ae..b62627c 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -115,7 +115,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); + "Initializing Exynos VGA, base %p\n", (void *)lcdbase); lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } @@ -143,10 +143,10 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, - .set_resources = cpu_noop, + .set_resources = cpu_noop, .enable_resources = cpu_enable, - .init = cpu_init, - .scan_bus = 0, + .init = cpu_init, + .scan_bus = 0, }; static void enable_exynos5420_dev(device_t dev) @@ -164,9 +164,9 @@ void exynos5420_config_l2_cache(void) uint32_t val; /* - * Bit 9 - L2 tag RAM setup (1 cycle) + * Bit 9 - L2 tag RAM setup (1 cycle) * Bits 8:6 - L2 tag RAM latency (3 cycles) - * Bit 5 - L2 data RAM setup (1 cycle) + * Bit 5 - L2 data RAM setup (1 cycle) * Bits 2:0 - L2 data RAM latency (3 cycles) */ val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 251abea..495f03c 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -52,7 +52,7 @@ #define EXYNOS5_TZPC1_DECPROT1SET 0x10110810 #define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index c974db2..c255132 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -323,7 +323,7 @@ struct mem_timings { uint8_t bpll_mdiv; uint8_t bpll_pdiv; uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ uint8_t pclk_cdrex_ratio; unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; diff --git a/src/cpu/samsung/exynos5420/dmc_common.c b/src/cpu/samsung/exynos5420/dmc_common.c index bef76d1..2e07ad0 100644 --- a/src/cpu/samsung/exynos5420/dmc_common.c +++ b/src/cpu/samsung/exynos5420/dmc_common.c @@ -133,14 +133,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + &dmc->directcmd); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + &dmc->directcmd); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have diff --git a/src/cpu/samsung/exynos5420/dp.h b/src/cpu/samsung/exynos5420/dp.h index 46579b3..e2fe715 100644 --- a/src/cpu/samsung/exynos5420/dp.h +++ b/src/cpu/samsung/exynos5420/dp.h @@ -425,8 +425,8 @@ struct exynos5_dp { #define VIDEO_MODE_SLAVE_MODE (1 << 0) #define VIDEO_MODE_MASTER_MODE (0 << 0) -#define HW_TRAINING_ERROR_CODE (7<<4) -#define HW_TRAINING_EN (1<<0) +#define HW_TRAINING_ERROR_CODE (7<<4) +#define HW_TRAINING_EN (1<<0) /* I2C EDID Chip ID, Slave Address */ #define I2C_EDID_DEVICE_ADDR 0x50 diff --git a/src/cpu/samsung/exynos5420/dsim.h b/src/cpu/samsung/exynos5420/dsim.h index 25015a2..b04f98f 100644 --- a/src/cpu/samsung/exynos5420/dsim.h +++ b/src/cpu/samsung/exynos5420/dsim.h @@ -103,7 +103,7 @@ struct exynos5_dsim { #define PLL_STABLE (1 << 31) #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10) #endif diff --git a/src/cpu/samsung/exynos5420/fb.c b/src/cpu/samsung/exynos5420/fb.c index 760f5ee..06e6ae6 100644 --- a/src/cpu/samsung/exynos5420/fb.c +++ b/src/cpu/samsung/exynos5420/fb.c @@ -187,7 +187,7 @@ void exynos_fimd_disable(void) * return status */ static int s5p_dp_config_video(struct s5p_dp_device *dp, - struct video_info *video_info) + struct video_info *video_info) { int timeout = 0; struct exynos5_dp *base = dp->base; @@ -195,9 +195,9 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, s5p_dp_config_video_slave_mode(dp, video_info); s5p_dp_set_video_color_format(dp, video_info->color_depth, - video_info->color_space, - video_info->dynamic_range, - video_info->ycbcr_coeff); + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { printk(BIOS_DEBUG, "PLL is not locked yet.\n"); @@ -258,8 +258,8 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) return -ERR_DPCD_READ_ERROR1; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, - DPCD_ENHANCED_FRAME_EN | - (data & DPCD_LANE_COUNT_SET_MASK))) { + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR1; } @@ -280,13 +280,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - &data)) { + &data)) { printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR2; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR2; } @@ -334,7 +334,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) * return status */ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, - int pre_emphasis, int lane) + int pre_emphasis, int lane) { u32 reg; struct exynos5_dp *base = dp->base; @@ -439,7 +439,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) if (s5p_dp_set_lane_lane_pre_emphasis(dp, - PRE_EMPHASIS_LEVEL_0, lane)) { + PRE_EMPHASIS_LEVEL_0, lane)) { printk(BIOS_DEBUG, "Unable to set pre emphasis level\n"); return -ERR_PRE_EMPHASIS_LEVELS; } @@ -457,14 +457,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", - dp->link_train.link_rate); + dp->link_train.link_rate); /* Not Retrying */ return -ERR_LINK_RATE_ABNORMAL; } if (dp->link_train.lane_count == 0) { printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n", - dp->link_train.lane_count); + dp->link_train.lane_count); /* Not retrying */ return -ERR_MAX_LANE_COUNT_ABNORMAL; } @@ -529,7 +529,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) } ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + dp->video_info->link_rate); if (ret) { printk(BIOS_ERR, "unable to do link train\n"); return ret; diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c index 2a93328..f58d002 100644 --- a/src/cpu/samsung/exynos5420/gpio.c +++ b/src/cpu/samsung/exynos5420/gpio.c @@ -53,7 +53,7 @@ static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { }; /* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) +#define GPIO_BIT(x) ((x) & 0x7) static struct gpio_bank *gpio_get_bank(unsigned int gpio) { diff --git a/src/cpu/samsung/exynos5420/gpio.h b/src/cpu/samsung/exynos5420/gpio.h index 0011904..d204cfc 100644 --- a/src/cpu/samsung/exynos5420/gpio.h +++ b/src/cpu/samsung/exynos5420/gpio.h @@ -479,7 +479,7 @@ void gpio_set_rate(int gpio, int mode); * * @param gpio GPIO to read * @return -1 if the value cannot be determined. Otherwise returns - * the corresponding MVL3 enum value. + * the corresponding MVL3 enum value. */ int gpio_read_mvl3(unsigned gpio); @@ -549,11 +549,11 @@ int gpio_set_value(unsigned gpio, int value); * * Vpd | Vpu | MVL * ----------------- - * 0 | 0 | 0 + * 0 | 0 | 0 * ----------------- - * 0 | 1 | Z <-- floating input will follow internal pull up/down + * 0 | 1 | Z <-- floating input will follow internal pull up/down * ----------------- - * 1 | 1 | 1 + * 1 | 1 | 1 */ enum mvl3 { LOGIC_0, diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index 2268628..7d40b1b 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -186,8 +186,8 @@ static struct s3c24x0_i2c_bus i2c_buses[] = { * * @param i2c- pointer to the appropriate i2c register bank. * @return I2C_OK, if transmission was ACKED - * I2C_NACK, if transmission was NACKED - * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS + * I2C_NACK, if transmission was NACKED + * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS */ static int WaitForXfer(struct s3c24x0_i2c *i2c) @@ -366,19 +366,19 @@ static int hsi2c_check_transfer(struct exynos5_hsi2c *i2c) { uint32_t status = read32(&i2c->usi_trans_status); if (status & (HSI2C_TRANS_ABORT | HSI2C_NO_DEV_ACK | - HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) { + HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) { if (status & HSI2C_TRANS_ABORT) printk(BIOS_ERR, - "%s: Transaction aborted.\n", __func__); + "%s: Transaction aborted.\n", __func__); if (status & HSI2C_NO_DEV_ACK) printk(BIOS_ERR, - "%s: No ack from device.\n", __func__); + "%s: No ack from device.\n", __func__); if (status & HSI2C_NO_DEV) printk(BIOS_ERR, - "%s: No response from device.\n", __func__); + "%s: No response from device.\n", __func__); if (status & HSI2C_TIMEOUT_AUTO) printk(BIOS_ERR, - "%s: Transaction time out.\n", __func__); + "%s: Transaction time out.\n", __func__); return -1; } return !(status & HSI2C_MASTER_BUSY); @@ -556,10 +556,10 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, write32(chip, &i2c->iicds); if ((cmd_type == I2C_WRITE) || (addr && addr_len)) write32(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat); else write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat); /* Wait for chip address to transmit. */ result = WaitForXfer(i2c); @@ -597,7 +597,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, /* Generate a re-START. */ write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat); ReadWriteByte(i2c); result = WaitForXfer(i2c); if (result != I2C_OK) @@ -608,8 +608,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, /* disable ACK for final READ */ if (i == data_len - 1) write32(readl(&i2c->iiccon) - & ~I2CCON_ACKGEN, - &i2c->iiccon); + & ~I2CCON_ACKGEN, + &i2c->iiccon); ReadWriteByte(i2c); result = WaitForXfer(i2c); data[i++] = read32(&i2c->iicds); diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h index 3c019d6..2a6e994 100644 --- a/src/cpu/samsung/exynos5420/power.h +++ b/src/cpu/samsung/exynos5420/power.h @@ -35,9 +35,9 @@ void power_enable_hw_thermal_trip(void); #define DPTX_PHY_ENABLE (1 << 0) /* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ -#define PMU_DEBUG_XXTI 0x1000 +#define PMU_DEBUG_XXTI 0x1000 /* Mask bit[12:8] for xxti clock selection */ -#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 /* Power Management Unit register map */ struct exynos5_power { @@ -55,7 +55,7 @@ struct exynos5_power { uint32_t inform1; /* 0x0804 */ uint8_t reserved6[0x1f8]; uint32_t pmu_debug; /* 0x0A00*/ - uint8_t reserved7[0x2908]; + uint8_t reserved7[0x2908]; uint32_t ps_hold_ctrl; /* 0x330c */ } __attribute__ ((__packed__)); diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index e89ed8e..12f5486 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -49,7 +49,7 @@ struct exynos5_phy_control; #define APLL_CON1_VAL (0x0020f300) /* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x0020f300) +#define MPLL_CON1_VAL (0x0020f300) /* CPLL_CON1 */ #define CPLL_CON1_VAL (0x0020f300) @@ -89,11 +89,11 @@ struct exynos5_phy_control; /* CLK_SRC_CPU */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 1 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 +#define MUX_HPM_SEL 1 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ | (MUX_CPU_SEL << 16) \ | (MUX_APLL_SEL)) @@ -104,47 +104,47 @@ struct exynos5_phy_control; #define DMC_MEMCONTROL_TP_DISABLE (0 << 4) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) -#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) +#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8) #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) -#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) -#define DMC_MEMCONTROL_BL_8 (3 << 20) -#define DMC_MEMCONTROL_BL_4 (2 << 20) +#define DMC_MEMCONTROL_BL_8 (3 << 20) +#define DMC_MEMCONTROL_BL_4 (2 << 20) -#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) +#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) -#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) /* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) - -#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) -#define DMC_MEMBASECONFIG_VAL(x) ( \ - DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ - DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ +#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) + +#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMBASECONFIG_VAL(x) ( \ + DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ + DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ ) #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) -#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF +#define DMC_PRECHCONFIG_VAL 0xFF000000 +#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 #define DFI_INIT_START (1 << 28) @@ -171,46 +171,46 @@ struct exynos5_phy_control; #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) /* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x33033300 -#define CLK_DIV_FSYS0_VAL 0x0 -#define CLK_DIV_FSYS1_VAL 0x04f13c4f -#define CLK_DIV_FSYS2_VAL 0x041d0000 +#define CLK_SRC_FSYS0_VAL 0x33033300 +#define CLK_DIV_FSYS0_VAL 0x0 +#define CLK_DIV_FSYS1_VAL 0x04f13c4f +#define CLK_DIV_FSYS2_VAL 0x041d0000 /* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x2 -#define COPY_RATIO 0x0 +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0 /* CLK_DIV_CPU1 = 0x00000003 */ -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ | (COPY_RATIO)) /* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00000000 +#define CLK_SRC_CORE0_VAL 0x00000000 /* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 +#define CLK_SRC_CORE1_VAL 0x100 /* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x00120000 +#define CLK_DIV_CORE0_VAL 0x00120000 /* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 +#define CLK_DIV_CORE1_VAL 0x07070700 /* CLK_DIV_SYSRGT */ -#define CLK_DIV_SYSRGT_VAL 0x00000111 +#define CLK_DIV_SYSRGT_VAL 0x00000111 /* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 +#define CLK_DIV_ACP_VAL 0x12 /* CLK_DIV_SYSLFT */ -#define CLK_DIV_SYSLFT_VAL 0x00000311 +#define CLK_DIV_SYSLFT_VAL 0x00000311 /* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x00000001 +#define CLK_SRC_CDREX_VAL 0x00000001 #define MUX_MCLK_CDR_MSPLL (1 << 4) -#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) -#define BPLL_SEL_MASK 0x7 -#define FOUTBPLL 2 +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define BPLL_SEL_MASK 0x7 +#define FOUTBPLL 2 /* CLK_DIV_CDREX */ #define CLK_DIV_CDREX0_VAL 0x30010100 @@ -282,19 +282,19 @@ struct exynos5_phy_control; #define TOP2_VAL 0x0110000 /* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0 /* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10 /* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10 /* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10 /* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_KFC */ #define SRC_KFC_HPM_SEL (1 << 15) @@ -421,19 +421,19 @@ struct exynos5_phy_control; #define MMC3_PRE_RATIO_OFFSET 24 /* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0 /* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10 /* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10 /* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10 /* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_DISP1_0 */ #define CLK_SRC_DISP1_0_VAL 0x10666600 diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 1c60378..8413b31 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -125,12 +125,12 @@ static inline void exynos_spi_flush_fifo(struct exynos_spi *regs) } static void exynos_spi_request_bytes(struct exynos_spi *regs, int count, - int width) + int width) { uint32_t mode_word = SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD, swap_word = (SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | - SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | - SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); + SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | + SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); /* For word address we need to swap bytes */ if (width == sizeof(uint32_t)) { @@ -170,7 +170,7 @@ static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, step = 1; } else if ((rx_bytes | tx_bytes | (uintptr_t)rxp |(uintptr_t)txp) & 3) { printk(BIOS_CRIT, "%s: WARNING: tranfer mode decreased to 1B\n", - __func__); + __func__); step = 1; } else { step = sizeof(uint32_t); @@ -190,7 +190,7 @@ static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, int rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK, tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; int min_tx = ((tx_bytes || !espi->half_duplex) ? - (espi->fifo_size / 2) : 1); + (espi->fifo_size / 2) : 1); // TODO(hungte) Abort if timeout happens in half-duplex mode. @@ -334,7 +334,7 @@ void spi_release_bus(struct spi_slave *slave) /* Reset swap mode to make sure no one relying on default values (Ex, * payload or kernel) will go wrong. */ clrbits_le32(&regs->mode_cfg, (SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD)); + SPI_MODE_BUS_WIDTH_WORD)); writel(0, &regs->swap_cfg); exynos_spi_flush_fifo(regs); } @@ -386,8 +386,8 @@ static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, } int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size) { + void *buffer_address, + size_t buffer_size) { // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; static struct exynos_spi_slave eslave = { diff --git a/src/cpu/samsung/exynos5420/spi.h b/src/cpu/samsung/exynos5420/spi.h index 94b4fda..445ebf0 100644 --- a/src/cpu/samsung/exynos5420/spi.h +++ b/src/cpu/samsung/exynos5420/spi.h @@ -88,6 +88,6 @@ struct exynos_spi { /* Serve as CBFS media source */ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); + void *buffer_address, + size_t buffer_size); #endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index de71b80..f9c227d 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -165,7 +165,7 @@ static void exynos5_uart_tx_byte(unsigned char data) #if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, + .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, // .tx_flush = exynos5_uart_tx_flush, .rx_byte = exynos5_uart_rx_byte, diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h index 1b7d635..87b785b 100644 --- a/src/cpu/samsung/exynos5420/usb.h +++ b/src/cpu/samsung/exynos5420/usb.h @@ -20,41 +20,41 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_USB_H #define CPU_SAMSUNG_EXYNOS5420_USB_H -#define CLK_24MHZ 5 +#define CLK_24MHZ 5 -#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) -#define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HOST_CTRL0_FSEL_MASK (7 << 16) -#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) /* Register map for PHY control */ struct usb_phy { - uint32_t usbphyctrl0; - uint32_t usbphytune0; - uint32_t reserved1[2]; - uint32_t hsicphyctrl1; - uint32_t hsicphytune1; - uint32_t reserved2[2]; - uint32_t hsicphyctrl2; - uint32_t hsicphytune2; - uint32_t reserved3[2]; - uint32_t ehcictrl; - uint32_t ohcictrl; - uint32_t usbotgsys; - uint32_t reserved4; - uint32_t usbotgtune; + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; }; void usb_init(device_t dev); diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..c036a4e 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -24,7 +24,7 @@ get_header_size= \ $(word 4,$(omap_header_info))))) $(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ $(call get_header_size,$(obj)/coreboot.rom, \ @@ -35,7 +35,7 @@ $(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom $(OBJCOPY) --only-section=".header" -O binary $@.tmp $@ $(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin - @printf " HEADER $(subst $(obj)/,,$(@))\n" + @printf " HEADER $(subst $(obj)/,,$(@))\n" $(Q)cat $(obj)/omap-header.bin $(obj)/coreboot.rom > $@ omap-header-y += header.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c index 553fe42..09fe077 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -55,7 +55,7 @@ int init_default_cbfs_media(struct cbfs_media *media) { struct cbfs_header *header = (struct cbfs_header *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + - CONFIG_CBFS_HEADER_ROM_OFFSET); + CONFIG_CBFS_HEADER_ROM_OFFSET); if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 5ed943e..7d40872 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -57,8 +57,8 @@ struct omap_image_headers headers __attribute__((section(".header"))) = { .size = 0xffffffff, .reserved = { 0xffffffff, 0xffffffff, 0xffffffff }, .filename = { 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff } + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff } }, .chsettings = { .key = 0xc0c0c0c1, diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c index ddab389..5203d09e 100644 --- a/src/cpu/ti/am335x/nand.c +++ b/src/cpu/ti/am335x/nand.c @@ -21,6 +21,6 @@ int init_default_cbfs_media(struct cbfs_media *media) { - /* FIXME: add support for reading coreboot from NAND */ + /* FIXME: add support for reading coreboot from NAND */ return 0; } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index bd2ff44..cfcf2db 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -180,7 +180,7 @@ uint32_t uartmem_getbaseaddr(void) #if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { - .init = am335x_uart_init_dev, + .init = am335x_uart_init_dev, .tx_byte = am335x_uart_tx_byte, .rx_byte = am335x_uart_rx_byte, }; diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..ad65165 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -37,7 +37,7 @@ static void c3_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = c3_init, + .init = c3_init, }; static struct cpu_device_id cpu_table[] = { @@ -48,6 +48,6 @@ static struct cpu_device_id cpu_table[] = { }; static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..2eecd73 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -34,28 +34,28 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0 static int c7a_speed_translation[] = { -// LFM HFM - 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M +// LFM HFM + 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV + 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV }; static int c7d_speed_translation[] = { -// LFM HFM - 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M +// LFM HFM + 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV + 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV @@ -107,7 +107,7 @@ static void set_c7_speed(int model) { for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { if ((c7a_speed_translation[i] == current) && ((c7a_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { + (msr.hi & 0xff00))) { new = c7a_speed_translation[i + 1]; } } @@ -116,7 +116,7 @@ static void set_c7_speed(int model) { for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { if ((c7d_speed_translation[i] == current) && ((c7d_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { + (msr.hi & 0xff00))) { new = c7d_speed_translation[i + 1]; } } diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..327a745 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -212,8 +212,8 @@ testok: /* * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we - * get STACK up, we restore that. It is only needed if we - * want to go back. + * get STACK up, we restore that. It is only needed if we + * want to go back. */ /* We don't need CAR from now on. */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..ec5602a 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -48,7 +48,7 @@ static void nano_finish_fid_vid_transition(void) cnt++; if (cnt > 128) { printk(BIOS_WARNING, - "Error while updating multiplier and voltage\n"); + "Error while updating multiplier and voltage\n"); break; } } while (msr.lo & ((1 << 16) | (1 << 17))); @@ -73,9 +73,9 @@ static void nano_set_max_fid_vid(void) u8 cur_fid = (msr.lo >> 8) & 0xff; printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", - cur_fid, min_fid, max_fid); - printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", - cur_vid, min_vid, max_vid); + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { /* Set highest frequency and VID */ diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7471928..5b9fd36 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -48,7 +48,7 @@ static void nano_print_ucode_info(const nano_ucode_header *ucode) printk(BIOS_SPEW, "Microcode update information:\n"); printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, - ucode->day, ucode->year ); + ucode->day, ucode->year ); } static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index ae58fb2..e4c25d7 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -22,21 +22,21 @@ #include <console/console.h> #include <cpu/cpu.h> -#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -#define MSR_IA32_BIOS_SIGN_ID 0x0000008b -#define MSR_UCODE_UPDATE_STATUS 0x00001205 +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 -#define NANO_UCODE_SIGNATURE 0x53415252 -#define NANO_UCODE_HEADER_SIZE 0x30 +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 /* These are values returned by the CPU after we attempt microcode updates. * We care what these values are exactly, so we define them to be sure */ typedef enum { - UCODE_UPDATE_NOT_ATTEMPTED = 0x0, - UCODE_UPDATE_SUCCESS = 0x1, - UCODE_UPDATE_FAIL = 0x2, - UCODE_UPDATE_WRONG_CPU = 0x3, - UCODE_INVALID_UPDATE_BLOCK = 0x4, + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, } ucode_update_status; @@ -48,19 +48,19 @@ typedef enum { } ucode_validity; typedef struct { - u32 signature; /* NANO_UCODE_SIGNATURE */ - u32 update_revision; /* Revision of the update header */ - u16 year; /* Year of patch release */ - u8 day; /* Day of patch release */ - u8 month; /* Month of patch release */ - u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ - u32 checksum; /* Two's complement checksum of ucode+header */ - u32 loader_revision; /* Revision of hardware ucode update loader*/ - u32 rfu_1; /* Reserved for future use */ - u32 payload_size; /* Size of the ucode payload only */ - u32 total_size; /* Size of the ucode, including header */ - char name[8]; /* ASCII string of ucode filename */ - u32 rfu_2; /* Reserved for future use */ + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reserved for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reserved for future use */ /* First double-word of the ucode payload * Its address represents the beginning of the ucode update we need to * send to the CPU */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e4613bf..7f609b1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -20,7 +20,7 @@ * it with the version available from LANL. * * Copyright (C) 2000, Ron Minnich rminnich(a)lanl.gov - * Advanced Computing Lab, LANL + * Advanced Computing Lab, LANL */ diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index 1be0e3a..62ca1e8 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -3,7 +3,7 @@ .globl reset_vector reset_vector: .byte 0xe9 - .int _start - ( . + 2 ) + .int _start - ( . + 2 ) /* Note: The above jump is hand coded to work around bugs in binutils. * 5 byte are used for a 3 byte instruction. This works because x86 * is little endian and allows us to use supported 32bit relocations diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds index a31a580..8f7388c 100644 --- a/src/cpu/x86/16bit/reset16.lds +++ b/src/cpu/x86/16bit/reset16.lds @@ -1,5 +1,5 @@ /* - * _ROMTOP : The top of the rom used where we + * _ROMTOP : The top of the rom used where we * need to put the reset vector. */ diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 481153d..7bd623e 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -36,7 +36,7 @@ extern char _car_data_end[]; * been migrated to real RAM. It does this by assuming the following things: * 1. cache-as-ram space is zero'd out once it is set up. * 2. Either the cache-as-ram space is memory-backed after getting torn down - * or the space returns 0xff's for each byte read. + * or the space returns 0xff's for each byte read. * Based on these 2 attributes there is the ability to tell when the * cache-as-ram region has been migrated. */ @@ -57,8 +57,8 @@ void *car_get_var_ptr(void *var) if (var < _car_start || var >= _car_end) { printk(BIOS_ERR, - "Requesting CAR variable outside of CAR region: %p\n", - var); + "Requesting CAR variable outside of CAR region: %p\n", + var); return var; } diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 868fb92..c6c70bc 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -133,8 +133,8 @@ void timer_monotonic_get(struct mono_time *mt) * around occurs. */ if (timer_fsb > 200) printk(BIOS_WARNING, - "apic timer freq (%d) may be too fast.\n", - timer_fsb); + "apic timer freq (%d) may be too fast.\n", + timer_fsb); mono_counter.last_value = lapic_read(LAPIC_TMCCT); mono_counter.initialized = 1; } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 555187f..40b3106 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -536,11 +536,11 @@ void initialize_cpus(struct bus *cpu_bus) enable_lapic(); /* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_APIC; + cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else /* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_CPU; + cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; #endif diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 6edcd0a..a9a2119 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -31,8 +31,8 @@ _secondary_start: /* This will get filled in by C code. */ _secondary_gdt_addr: gdtaddr: - .word 0 /* the table limit */ - .long 0 /* we know the offset */ + .word 0 /* the table limit */ + .long 0 /* we know the offset */ _secondary_start_end: diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index f16da27..2bad816 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -57,7 +57,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) * Determine address by calculating the XIP_ROM_SIZE sized area with * XIP_ROM_SIZE alignment that contains the global variable defined above; */ - unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); + unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d168978..3ae7fce 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -48,7 +48,7 @@ /* 2 MTRRS are reserved for the operating system */ #define BIOS_MTRRS 6 #define OS_MTRRS 2 -#define MTRRS (BIOS_MTRRS + OS_MTRRS) +#define MTRRS (BIOS_MTRRS + OS_MTRRS) static int total_mtrrs = MTRRS; static int bios_mtrrs = BIOS_MTRRS; @@ -88,9 +88,9 @@ static inline unsigned int fms(unsigned int x) int r; __asm__("bsrl %1,%0\n\t" - "jnz 1f\n\t" - "movl $0,%0\n" - "1:" : "=r" (r) : "g" (x)); + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); return r; } @@ -100,9 +100,9 @@ static inline unsigned int fls(unsigned int x) int r; __asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $32,%0\n" - "1:" : "=r" (r) : "g" (x)); + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); return r; } @@ -175,7 +175,7 @@ static struct memranges *get_physical_address_space(void) * regions. */ memranges_init(addr_space, mask, mask, MTRR_TYPE_WRBACK); memranges_add_resources(addr_space, mask, 0, - MTRR_TYPE_UNCACHEABLE); + MTRR_TYPE_UNCACHEABLE); /* Handle any write combining resources. Only prefetchable * resources with the IORESOURCE_WRCOMB flag are appropriate @@ -183,7 +183,7 @@ static struct memranges *get_physical_address_space(void) match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; mask |= match; memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + MTRR_TYPE_WRCOMB); #if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size @@ -192,7 +192,7 @@ static struct memranges *get_physical_address_space(void) resource_t rom_base = RANGE_TO_PHYS_ADDR( RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, - MTRR_TYPE_WRPROT); + MTRR_TYPE_WRPROT); #endif /* The address space below 4GiB is special. It needs to be @@ -201,15 +201,15 @@ static struct memranges *get_physical_address_space(void) * Therefore, ensure holes are filled up to 4GiB as * uncacheable */ memranges_fill_holes_up_to(addr_space, - RANGE_TO_PHYS_ADDR(RANGE_4GB), - MTRR_TYPE_UNCACHEABLE); + RANGE_TO_PHYS_ADDR(RANGE_4GB), + MTRR_TYPE_UNCACHEABLE); printk(BIOS_DEBUG, "MTRR: Physical address space:\n"); memranges_each_entry(r, addr_space) printk(BIOS_DEBUG, - "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", - range_entry_base(r), range_entry_end(r), - range_entry_size(r), range_entry_tag(r)); + "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", + range_entry_base(r), range_entry_end(r), + range_entry_size(r), range_entry_tag(r)); } return addr_space; @@ -284,8 +284,8 @@ static void calc_fixed_mtrrs(void) type = range_entry_tag(r); printk(MTRR_VERBOSE_LEVEL, - "MTRR addr 0x%x-0x%x set to %d type @ %d\n", - begin, begin + desc->step, type, type_index); + "MTRR addr 0x%x-0x%x set to %d type @ %d\n", + begin, begin + desc->step, type, type_index); if (type == MTRR_TYPE_WRBACK) type |= MTRR_FIXED_WRBACK_BITS; fixed_mtrr_types[type_index] = type; @@ -345,7 +345,7 @@ static void commit_fixed_mtrrs(void) for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) { printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", - msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); + msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); wrmsr(msr_index[i], fixed_msrs[i]); } @@ -415,9 +415,9 @@ static void disable_cache_rom(void *unused) BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), + disable_cache_rom, NULL), BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), + disable_cache_rom, NULL), }; #endif @@ -440,7 +440,7 @@ static void clear_var_mtrr(int index) } static void write_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint32_t base, uint32_t size, int mtrr_type) { msr_t msr_val; unsigned long msr_index; @@ -480,7 +480,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, #endif printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", - var_state->mtrr_index, rbase, rsize, mtrr_type); + var_state->mtrr_index, rbase, rsize, mtrr_type); msr_val.lo = rbase; msr_val.lo |= mtrr_type; @@ -497,7 +497,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, } static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint32_t base, uint32_t size, int mtrr_type) { while (size != 0) { uint32_t addr_lsb; @@ -525,7 +525,7 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, } static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, - struct range_entry *r) + struct range_entry *r) { uint32_t a1, a2, b1, b2; int mtrr_type; @@ -536,7 +536,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, * +------------------+ b2 = ALIGN_UP(end) * | 0 or more bytes | <-- hole is carved out between b1 and b2 * +------------------+ a2 = b1 = end - * | | + * | | * +------------------+ a1 = begin * * Thus, there are 3 sub-ranges to configure variable MTRRs for. @@ -603,7 +603,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, } static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, - struct range_entry *r) + struct range_entry *r) { uint32_t a1, a2, b1, b2, c1, c2; int mtrr_type; @@ -614,7 +614,7 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, * +------------------+ c2 = end * | 0 or more bytes | * +------------------+ b2 = c1 = ALIGN_DOWN(end) - * | | + * | | * +------------------+ b1 = a2 = ALIGN_UP(begin) * | 0 or more bytes | * +------------------+ a1 = begin @@ -662,7 +662,7 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, } static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) + int above4gb, int address_bits) { int wb_deftype_count; int uc_deftype_count; @@ -740,7 +740,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, } printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", - wb_deftype_count, uc_deftype_count); + wb_deftype_count, uc_deftype_count); if (wb_deftype_count < uc_deftype_count) { printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); @@ -751,7 +751,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, } static void commit_var_mtrrs(struct memranges *addr_space, int def_type, - int above4gb, int address_bits) + int above4gb, int address_bits) { struct range_entry *r; struct var_mtrr_state var_state; @@ -797,7 +797,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) disable_cache(); commit_var_mtrrs(addr_space, mtrr_default_type, !!above4gb, - address_bits); + address_bits); enable_var_mtrr(mtrr_default_type); enable_cache(); } diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index b595a36..14de34a 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,7 +42,7 @@ $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf $(OBJCOPY) -O binary $< $@ $(obj)/cpu/x86/smm/smmstub.ramstage.o: $(obj)/cpu/x86/smm/smmstub - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) # C-based SMM handler. @@ -57,7 +57,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf $(OBJCOPY) -O binary $< $@ $(obj)/cpu/x86/smm/smm.ramstage.o: $(obj)/cpu/x86/smm/smm - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) else # CONFIG_SMM_MODULES @@ -92,7 +92,7 @@ $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_L # change to the target path because objcopy will use the path name in its # ELF symbol names. $(obj)/cpu/x86/smm/smm_wrap.ramstage.o: $(obj)/cpu/x86/smm/smm_wrap - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(obj)/cpu/x86/smm; $(OBJCOPY) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o endif # CONFIG_SMM_MODULES diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index fc30909..6cf1450 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -69,7 +69,7 @@ void io_trap_handler(int smif) /* If a handler function handled a given IO trap, it * shall return a non-zero value */ - printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif); + printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif); if (southbridge_io_trap_handler(smif)) return; @@ -167,7 +167,7 @@ void smi_handler(u32 smm_revision) state_save.type = EM64T101; state_save.em64t101_state_save = smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); + SMM_EM64T101_ARCH_OFFSET, node); break; case 0x00030064: state_save.type = AMD64; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 444e335..f778dd4 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -123,7 +123,7 @@ void smm_handler_start(void *arg, int cpu, const struct smm_runtime *runtime) if (cpu >= CONFIG_MAX_CPUS) { console_init(); printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); + "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 478ae8c..6c24e99 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -72,7 +72,7 @@ struct smm_entry_ins { * other entry points are stride size below the previous. */ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, - void *jmp_target) + void *jmp_target) { int i; char *cur; @@ -91,8 +91,8 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, disp -= sizeof(entry) + (uint32_t)cur; printk(BIOS_DEBUG, - "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", - cur, disp); + "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", + cur, disp); entry.rel16 = disp; memcpy(cur, &entry, sizeof(entry)); cur -= stride; @@ -102,7 +102,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, /* Place stacks in base -> base + size region, but ensure the stacks don't * overlap the staggered entry points. */ static void *smm_stub_place_stacks(char *base, int size, - struct smm_loader_params *params) + struct smm_loader_params *params) { int total_stack_size; char *stacks_top; @@ -113,7 +113,7 @@ static void *smm_stub_place_stacks(char *base, int size, /* If stack space is requested assume the space lives in the lower * half of SMRAM. */ total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; + params->num_concurrent_stacks; /* There has to be at least one stack user. */ if (params->num_concurrent_stacks < 1) @@ -153,9 +153,9 @@ static void smm_stub_place_staggered_entry_points(char *base, num_entries--; } smm_place_jmp_instructions(base, - params->per_cpu_save_state_size, - num_entries, - rmodule_entry(smm_stub)); + params->per_cpu_save_state_size, + num_entries, + rmodule_entry(smm_stub)); } } @@ -197,7 +197,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) /* Adjust remaining size to account for save state. */ total_save_state_size = params->per_cpu_save_state_size * - params->num_concurrent_save_states; + params->num_concurrent_save_states; size -= total_save_state_size; /* The save state size encroached over the first SMM entry point. */ @@ -272,7 +272,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) params->runtime = &stub_params->runtime; printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", - smm_stub_loc, params->handler, params->handler_arg); + smm_stub_loc, params->handler, params->handler_arg); return 0; } @@ -307,13 +307,13 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | stacks | + * | stacks | * +-----------------+ <- smram + size - total_stack_size - * | ... | + * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE - * | handler | + * | handler | * +-----------------+ <- smram + SMM_DEFAULT_SIZE - * | stub code | + * | stub code | * +-----------------+ <- smram * * It should be noted that this algorithm will not work for @@ -338,7 +338,7 @@ int smm_load_module(void *smram, int size, struct smm_loader_params *params) return -1; total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; + params->num_concurrent_stacks; /* Stacks start at the top of the region. */ base = smram; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 07eb5dc..adc92ea 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -67,7 +67,7 @@ smm_handler_start: movl %cr0, %eax andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ + orl $0x1, %eax /* PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..f94cfd8 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -28,26 +28,26 @@ /* * +--------------------------------+ 0xaffff - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | * +--------------------------------+ 0xaf000 - * | | - * | | - * | | + * | | + * | | + * | | * +--------------------------------+ 0xa8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0xa8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | * +--------------------------------+ 0xa7400 - * | | - * | SMM Handler | - * | | + * | | + * | SMM Handler | + * | | * +--------------------------------+ 0xa0000 * */ @@ -76,16 +76,16 @@ * All the bad magic is not all that bad after all. */ smm_handler_start: - movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx + movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 /* Enable protected mode */ - data32 ljmp $0x08, $1f + data32 ljmp $0x08, $1f .code32 1: @@ -93,12 +93,12 @@ smm_handler_start: wbinvd /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs /* Get this CPU's LAPIC ID */ movl $LAPIC_ID, %esi diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index fdc5053..6b52ba3 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -21,30 +21,30 @@ /* * +--------------------------------+ - * | SMM Handler C Code | + * | SMM Handler C Code | * +--------------------------------+ 0x14000 - * | SMM Handler Heap | + * | SMM Handler Heap | * +--------------------------------+ 0x10000 - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | * +--------------------------------+ 0xf000 - * | | - * | | - * | EARLY DATA (lock, vectors) | + * | | + * | | + * | EARLY DATA (lock, vectors) | * +--------------------------------+ 0x8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0x8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | * +--------------------------------+ 0x7400 - * | | - * | SMM Handler Assembly Stub | - * | | + * | | + * | SMM Handler Assembly Stub | + * | | * +--------------------------------+ TSEG * */ @@ -132,14 +132,14 @@ smm_check_gdt_vector: addr32 movl %ebx, (%eax) smm_load_gdt: - movl $(smm_gdt_vector), %ebx - addl %edx, %ebx /* TSEG base in %edx */ + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ data32 lgdt (%ebx) - movl %cr0, %eax - andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ - movl %eax, %cr0 + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0 /* Enable protected mode */ movl $(smm_prot_vector), %eax @@ -149,12 +149,12 @@ smm_load_gdt: .code32 smm_prot_start: /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs /* Get this CPU's LAPIC ID */ movl $LAPIC_ID, %esi diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index a0a5d18..93c0b30 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -100,9 +100,9 @@ * 13 0x9cc00 0xa4c00 0xac900 * 14 0x9c800 0xa4800 0xac500 * 15 0x9c400 0xa4400 0xac100 - * . . . . - * . . . . - * . . . . + * . . . . + * . . . . + * . . . . * 31 0x98400 0xa0400 0xa8100 * * With 32 cores, the SMM handler would need to fit between @@ -123,7 +123,7 @@ smm_relocation_start: * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 * Intel SandyBridge: 0x30101 - * AMD64: 0x3XX64 + * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. */ diff --git a/src/device/agp_device.c b/src/device/agp_device.c index 550297a..6465c3a 100644 --- a/src/device/agp_device.c +++ b/src/device/agp_device.c @@ -65,11 +65,11 @@ static struct pci_operations agp_bus_ops_pci = { struct device_operations default_agp_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = agp_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &agp_bus_ops_pci, + .init = 0, + .scan_bus = agp_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &agp_bus_ops_pci, }; diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index cbc878d..95d86d6 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -257,7 +257,7 @@ void azalia_audio_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", - codec_mask); + codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index f25f96c..0613b69 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -106,7 +106,7 @@ void cardbus_read_resources(device_t dev) /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_0, IORESOURCE_IO); + PCI_CB_IO_BASE_0, IORESOURCE_IO); cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); /* See which bridge I/O resources are implemented. */ @@ -116,7 +116,7 @@ void cardbus_read_resources(device_t dev) /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_1, IORESOURCE_IO); + PCI_CB_IO_BASE_1, IORESOURCE_IO); /* If I can, enable prefetch for mem0. */ ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); @@ -136,7 +136,7 @@ void cardbus_read_resources(device_t dev) if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) type |= IORESOURCE_PREFETCH; cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_0, type); + PCI_CB_MEMORY_BASE_0, type); if (type & IORESOURCE_PREFETCH) cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); @@ -147,7 +147,7 @@ void cardbus_read_resources(device_t dev) /* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); + PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); compact_resources(dev); @@ -175,10 +175,10 @@ void cardbus_enable_resources(device_t dev) struct device_operations default_cardbus_ops_bus = { .read_resources = cardbus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, }; diff --git a/src/device/device.c b/src/device/device.c index 8bde663..d5142e8 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -16,7 +16,7 @@ */ /* - * (c) 1999--2000 Martin Mares <mj(a)suse.cz> + * (c) 1999--2000 Martin Mares <mj(a)suse.cz> */ /* @@ -201,7 +201,7 @@ static void read_resources(struct bus *bus) struct device *curdev; printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), - __func__, bus->secondary, bus->link_num); + __func__, bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -212,7 +212,7 @@ static void read_resources(struct bus *bus) if (!curdev->ops || !curdev->ops->read_resources) { printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } curdev->ops->read_resources(curdev); @@ -222,7 +222,7 @@ static void read_resources(struct bus *bus) read_resources(link); } printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num); } struct pick_largest_state { @@ -249,9 +249,9 @@ static void pick_largest_resource(void *gp, struct device *dev, return; /* Skip it. */ if (last && ((last->align < resource->align) || ((last->align == resource->align) && - (last->size < resource->size)) || + (last->size < resource->size)) || ((last->align == resource->align) && - (last->size == resource->size) && (!state->seen_last)))) { + (last->size == resource->size) && (!state->seen_last)))) { return; } if (!state->result || @@ -264,9 +264,9 @@ static void pick_largest_resource(void *gp, struct device *dev, } static struct device *largest_resource(struct bus *bus, - struct resource **result_res, - unsigned long type_mask, - unsigned long type) + struct resource **result_res, + unsigned long type_mask, + unsigned long type) { struct pick_largest_state state; @@ -276,7 +276,7 @@ static struct device *largest_resource(struct bus *bus, state.seen_last = 0; search_bus_resources(bus, type_mask, type, pick_largest_resource, - &state); + &state); *result_res = state.result; return state.result_dev; @@ -316,7 +316,7 @@ static struct device *largest_resource(struct bus *bus, * @return TODO */ static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) + unsigned long type_mask, unsigned long type) { struct device *dev; struct resource *resource; @@ -324,10 +324,10 @@ static void compute_resources(struct bus *bus, struct resource *bridge, base = round(bridge->base, bridge->align); printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, - bridge->gran, bridge->limit); + " limit: %llx\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", base, bridge->size, bridge->align, + bridge->gran, bridge->limit); /* For each child which is a bridge, compute the resource needs. */ for (dev = bus->children; dev; dev = dev->sibling) { @@ -359,8 +359,8 @@ static void compute_resources(struct bus *bus, struct resource *bridge, if (link == NULL) { printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); } compute_resources(link, child_bridge, @@ -396,9 +396,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, if ((resource->limit == 0xffffffff) && (resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); + "Resource limit looks wrong! (no APIC?)\n"); printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); + dev_path(dev), resource->index, resource->limit); } if (resource->flags & IORESOURCE_IO) { @@ -426,11 +426,11 @@ static void compute_resources(struct bus *bus, struct resource *bridge, base += resource->size; printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_PREFETCH) ? - "prefmem" : "mem"); + dev_path(dev), resource->index, resource->base, + resource->base + resource->size - 1, + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_PREFETCH) ? + "prefmem" : "mem"); } /* @@ -440,13 +440,13 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * address positively decoded by the bridge. */ bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); + round(bridge->base, bridge->align); printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), __func__, - (bridge->flags & IORESOURCE_IO) ? "io" : - (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran, bridge->limit); + " limit: %llx done\n", dev_path(bus->dev), __func__, + (bridge->flags & IORESOURCE_IO) ? "io" : + (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); } /** @@ -464,7 +464,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * @see compute_resources */ static void allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) + unsigned long type_mask, unsigned long type) { struct device *dev; struct resource *resource; @@ -472,10 +472,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, base = bridge->base; printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran, bridge->limit); + "limit:%llx\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); /* Remember we haven't found anything yet. */ resource = NULL; @@ -528,29 +528,29 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, base += resource->size; } else { printk(BIOS_ERR, "!! Resource didn't fit !!\n"); - printk(BIOS_ERR, " aligned base %llx size %llx " - "limit %llx\n", round(base, resource->align), - resource->size, resource->limit); - printk(BIOS_ERR, " %llx needs to be <= %llx " - "(limit)\n", (round(base, resource->align) + + printk(BIOS_ERR, " aligned base %llx size %llx " + "limit %llx\n", round(base, resource->align), + resource->size, resource->limit); + printk(BIOS_ERR, " %llx needs to be <= %llx " + "(limit)\n", (round(base, resource->align) + resource->size) - 1, resource->limit); - printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" - " %s\n", (resource->flags & IORESOURCE_ASSIGNED) - ? "Assigned: " : "", dev_path(dev), - resource->index, resource->base, - resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" - : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" + " %s\n", (resource->flags & IORESOURCE_ASSIGNED) + ? "Assigned: " : "", dev_path(dev), + resource->index, resource->base, + resource->base + resource->size - 1, + (resource->flags & IORESOURCE_IO) ? "io" + : (resource->flags & IORESOURCE_PREFETCH) + ? "prefmem" : "mem"); } printk(BIOS_SPEW, "%s%s %02lx * [0x%llx - 0x%llx] %s\n", - (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " - : "", dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, (resource->flags & IORESOURCE_IO) - ? "io" : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " + : "", dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, (resource->flags & IORESOURCE_IO) + ? "io" : (resource->flags & IORESOURCE_PREFETCH) + ? "prefmem" : "mem"); } /* @@ -563,10 +563,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, bridge->flags |= IORESOURCE_ASSIGNED; printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, - bridge->gran); + "gran: %d done\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", base, bridge->size, bridge->align, + bridge->gran); /* For each child which is a bridge, allocate_resources. */ for (dev = bus->children; dev; dev = dev->sibling) { @@ -593,17 +593,17 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, */ link = dev->link_list; while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) + IOINDEX_LINK(child_bridge->index)) link = link->next; if (link == NULL) printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); } } } @@ -614,10 +614,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, #define MEM_MASK (IORESOURCE_MEM) #endif -#define IO_MASK (IORESOURCE_IO) +#define IO_MASK (IORESOURCE_IO) #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) #define MEM_TYPE (IORESOURCE_MEM) -#define IO_TYPE (IORESOURCE_IO) +#define IO_TYPE (IORESOURCE_IO) struct constraints { struct resource pref, io, mem; @@ -639,7 +639,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) if (!res->size) { /* It makes no sense to have 0-sized, fixed resources.*/ printk(BIOS_ERR, "skipping %s@%lx fixed resource, " - "size=0!\n", dev_path(dev), res->index); + "size=0!\n", dev_path(dev), res->index); continue; } @@ -703,7 +703,7 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & IORESOURCE_FIXED)) continue; printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); + dev_path(dev), res->index, res->limit); if ((res->flags & MEM_MASK) == PREF_TYPE && (res->limit < limits.pref.limit)) limits.pref.limit = res->limit; @@ -736,9 +736,9 @@ static void avoid_fixed_resources(struct device *dev) continue; printk(BIOS_SPEW, "%s2: %s@%02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); + dev_path(dev), res->index, res->limit); printk(BIOS_SPEW, "\tlim->base %08llx lim->limit %08llx\n", - lim->base, lim->limit); + lim->base, lim->limit); /* Is the resource outside the limits? */ if (lim->base > res->base) @@ -808,7 +808,7 @@ static void set_vga_bridge_bits(void) /* Now walk up the bridges setting the VGA enable. */ while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", - dev_path(bus->dev)); + dev_path(bus->dev)); bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } @@ -832,7 +832,7 @@ void assign_resources(struct bus *bus) struct device *curdev; printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -840,7 +840,7 @@ void assign_resources(struct bus *bus) if (!curdev->ops || !curdev->ops->set_resources) { printk(BIOS_ERR, "%s missing set_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } post_log_path(curdev); @@ -848,7 +848,7 @@ void assign_resources(struct bus *bus) } post_log_clear(); printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num); } /** @@ -1078,17 +1078,17 @@ void dev_configure(void) continue; if (res->flags & IORESOURCE_PREFETCH) { allocate_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); + res, MEM_MASK, PREF_TYPE); continue; } if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, - res, MEM_MASK, MEM_TYPE); + res, MEM_MASK, MEM_TYPE); continue; } if (res->flags & IORESOURCE_IO) { allocate_resources(child->link_list, - res, IO_MASK, IO_TYPE); + res, IO_MASK, IO_TYPE); continue; } } @@ -1142,7 +1142,7 @@ static void init_dev(struct device *dev) #endif if (dev->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(dev->bus->dev), dev->bus->link_num); + dev_path(dev->bus->dev), dev->bus->link_num); } printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); @@ -1151,7 +1151,7 @@ static void init_dev(struct device *dev) #if CONFIG_HAVE_MONOTONIC_TIMER dev_init_time = current_time_from(&start_time); printk(BIOS_DEBUG, "%s init %ld usecs\n", dev_path(dev), - rela_time_in_microseconds(&dev_init_time)); + rela_time_in_microseconds(&dev_init_time)); #endif } } diff --git a/src/device/device_util.c b/src/device/device_util.c index cad2a06..74a5f82 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -35,7 +35,7 @@ * @param parent The bus to find the device on. * @param path The relative path from the bus to the appropriate device. * @return Pointer to a device structure for the device on bus at path - * or 0/NULL if no device is found. + * or 0/NULL if no device is found. */ device_t find_dev_path(struct bus *parent, struct device_path *path) { @@ -119,8 +119,8 @@ device_t dev_find_lapic(unsigned apic_id) * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). * @param device A PCI device ID. * @param from Pointer to the device structure, used as a starting point in - * the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices). + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). * @return Pointer to the device struct. */ struct device *dev_find_device(u16 vendor, u16 device, struct device *from) @@ -141,8 +141,8 @@ struct device *dev_find_device(u16 vendor, u16 device, struct device *from) * * @param class Class of the device. * @param from Pointer to the device structure, used as a starting point in - * the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices). + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). * @return Pointer to the device struct. */ struct device *dev_find_class(unsigned int class, struct device *from) @@ -276,7 +276,7 @@ const char *dev_path(device_t dev) break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", - dev->path.type); + dev->path.type); break; } } @@ -497,7 +497,7 @@ struct resource *find_resource(device_t dev, unsigned index) resource = probe_resource(dev, index); if (!resource) { printk(BIOS_EMERG, "%s missing resource: %02x\n", - dev_path(dev), index); + dev_path(dev), index); die(""); } return resource; @@ -625,7 +625,7 @@ void report_resource_stored(device_t dev, struct resource *resource, #endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " - "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, + "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, resource->size, resource->gran, buf, resource_type(resource), comment); } @@ -652,14 +652,14 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, if (res->flags & IORESOURCE_SUBTRACTIVE) { struct bus * subbus; for (subbus = curdev->link_list; subbus; - subbus = subbus->next) + subbus = subbus->next) if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) break; if (!subbus) /* Why can subbus be NULL? */ break; search_bus_resources(subbus, type_mask, type, - search, gp); + search, gp); continue; } search(gp, curdev, res); @@ -668,7 +668,7 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, } void search_global_resources(unsigned long type_mask, unsigned long type, - resource_search_t search, void *gp) + resource_search_t search, void *gp) { struct device *curdev; @@ -760,7 +760,7 @@ void print_resource_tree(struct device *root, int debug_level, const char *msg) /* Bail if not printing to screen. */ if (!do_printk(debug_level, "Show resources in subtree (%s)...%s\n", - dev_path(root), msg)) + dev_path(root), msg)) return; resource_tree(root, debug_level, 0); @@ -799,7 +799,7 @@ void show_devs_subtree(struct device *root, int debug_level, const char *msg) { /* Bail if not printing to screen. */ if (!do_printk(debug_level, "Show all devs in subtree %s...%s\n", - dev_path(root), msg)) + dev_path(root), msg)) return; do_printk(debug_level, "%s\n", msg); show_devs_tree(root, debug_level, 0, -1); @@ -819,7 +819,7 @@ void show_all_devs(int debug_level, const char *msg) } void show_one_resource(int debug_level, struct device *dev, - struct resource *resource, const char *comment) + struct resource *resource, const char *comment) { char buf[10]; unsigned long long base, end; @@ -896,7 +896,7 @@ u32 find_pci_tolm(struct bus *bus) u32 tolm; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); + tolm_test, &min); tolm = 0xffffffffUL; diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index d98de91..404eba8 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -56,7 +56,7 @@ int dimm_is_registered(enum spd_dimm_type type) * array, and passed to this function. * * @param dimm pointer to @ref dimm_attr structure where the decoded data is to - * be stored + * be stored * @param spd array of raw data previously read from the SPD. * * @return @ref spd_status enumerator @@ -207,7 +207,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } bus_width = 8 << val; - printram(" Bus width : %u\n", bus_width); + printram(" Bus width : %u\n", bus_width); /* We have all the info we need to compute the dimm size */ /* Capacity is 256Mbit multiplied by the power of 2 specified in @@ -345,12 +345,12 @@ void dram_print_spd_ddr3(const dimm_attr * dimm) printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); - printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); - printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); /* CAS Latencies Supported */ val16 = dimm->cas_supported; - printk(BIOS_INFO, " CAS latencies :"); + printk(BIOS_INFO, " CAS latencies :"); i = 0; do { if (val16 & 1) @@ -360,18 +360,18 @@ void dram_print_spd_ddr3(const dimm_attr * dimm) } while (val16); printk(BIOS_INFO, "\n"); - print_ns(" tCKmin : ", dimm->tCK); - print_ns(" tAAmin : ", dimm->tAA); - print_ns(" tWRmin : ", dimm->tWR); - print_ns(" tRCDmin : ", dimm->tRCD); - print_ns(" tRRDmin : ", dimm->tRRD); - print_ns(" tRPmin : ", dimm->tRP); - print_ns(" tRASmin : ", dimm->tRAS); - print_ns(" tRCmin : ", dimm->tRC); - print_ns(" tRFCmin : ", dimm->tRFC); - print_ns(" tWTRmin : ", dimm->tWTR); - print_ns(" tRTPmin : ", dimm->tRTP); - print_ns(" tFAWmin : ", dimm->tFAW); + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tAAmin : ", dimm->tAA); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tFAWmin : ", dimm->tFAW); } /*============================================================================== @@ -430,12 +430,12 @@ static u16 ddr3_cas_to_mr0_map(u8 cas) * @param cas CAS latency in clock cycles. */ mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type burst_type, - enum ddr3_mr0_burst_length burst_length) + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type burst_type, + enum ddr3_mr0_burst_length burst_length) { mrs_cmd_t cmd = 0 << 16; @@ -493,12 +493,12 @@ static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) * \brief Get command address for a DDR3 MR1 command */ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods ods, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable) + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods ods, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable) { mrs_cmd_t cmd = 1 << 16; @@ -532,8 +532,8 @@ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, * @param cas_cwl CAS write latency in clock cycles. */ mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl) + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, u8 cas_cwl) { mrs_cmd_t cmd = 2 << 16; @@ -554,7 +554,7 @@ mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, * \brief Get command address for a DDR3 MR3 command * * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read - * leveling mode. Zero for normal operation. + * leveling mode. Zero for normal operation. */ mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) { @@ -578,8 +578,8 @@ mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) { u32 downshift, upshift; - /* High bits= A4 | A6 | A8 | BA1 */ - /* Low bits = A3 | A5 | A7 | BA0 */ + /* High bits= A4 | A6 | A8 | BA1 */ + /* Low bits = A3 | A5 | A7 | BA0 */ u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); downshift = (cmd & (lowbits << 1)); upshift = (cmd & lowbits); diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index d9ab486..cb96dd4 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -53,8 +53,8 @@ static device_t ht_scan_get_devs(device_t *old_devices) * hypertransport device. */ while (last && last->sibling && - (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) + (last->sibling->path.type == DEVICE_PATH_PCI) && + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } @@ -154,14 +154,14 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1; if (!linkb_to_host) { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; + cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; + cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; } else { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; + cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; + cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; } @@ -207,8 +207,8 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) new_freq &= 0x0f; if (new_freq != freq) { printk(BIOS_ERR, "%s Hypertransport frequency would " - "not set. Wanted: %x, got: %x\n", - dev_path(dev), freq, new_freq); + "not set. Wanted: %x, got: %x\n", + dev_path(dev), freq, new_freq); } } old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1); @@ -218,13 +218,13 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) present_width); reset_needed = 1; printk(BIOS_SPEW, "HyperT widthP old %x new %x\n", - old_width, present_width); + old_width, present_width); new_width = pci_read_config8(cur->dev, - cur->pos + cur->config_off + 1); + cur->pos + cur->config_off + 1); if (new_width != present_width) { printk(BIOS_ERR, "%s Hypertransport width would not " - "set. Wanted: %x, got: %x\n", - dev_path(dev), present_width, new_width); + "set. Wanted: %x, got: %x\n", + dev_path(dev), present_width, new_width); } } @@ -236,14 +236,14 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq); reset_needed = 1; printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", - old_freq, freq); + old_freq, freq); new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off); new_freq &= 0x0f; if (new_freq != freq) { printk(BIOS_ERR, "%s Hypertransport frequency would " - "not set. Wanted: %x, got: %x\n", - dev_path(prev->dev), freq, new_freq); + "not set. Wanted: %x, got: %x\n", + dev_path(prev->dev), freq, new_freq); } } old_width = @@ -254,13 +254,13 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_width); reset_needed = 1; printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, - upstream_width); + upstream_width); new_width = pci_read_config8(prev->dev, - prev->pos + prev->config_off + 1); + prev->pos + prev->config_off + 1); if (new_width != upstream_width) { printk(BIOS_ERR, "%s Hypertransport width would not " - "set. Wanted: %x, got: %x\n", - dev_path(prev->dev), upstream_width, new_width); + "set. Wanted: %x, got: %x\n", + dev_path(prev->dev), upstream_width, new_width); } } #endif @@ -317,9 +317,9 @@ static void ht_collapse_early_enumeration(struct bus *bus, /* Initialize the hypertransport enumeration state. */ prev.dev = bus->dev; prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; + prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; + prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; /* Wait until the link initialization is complete. */ @@ -339,12 +339,12 @@ static void ht_collapse_early_enumeration(struct bus *bus, */ ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */ pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, - ctrl); + ctrl); ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { printk(BIOS_ALERT, "Detected error on " - "Hypertransport link\n"); + "Hypertransport link\n"); return; } } @@ -405,14 +405,14 @@ static void ht_collapse_early_enumeration(struct bus *bus, flags &= ~0x1f; pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); + dev_path(&dummy), dummy.vendor, dummy.device); } } unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max, - unsigned *ht_unitid_base, - unsigned offset_unitid) + unsigned max_devfn, unsigned int max, + unsigned *ht_unitid_base, + unsigned offset_unitid) { /* * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this @@ -427,7 +427,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - /* + /* * Let's record the device of last HT device, so we can set the unitid * to CONFIG_HT_CHAIN_END_UNITID_BASE. */ @@ -447,9 +447,9 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, prev.dev = bus->dev; prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; + prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; + prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; /* If present, assign unitid to a hypertransport chain. */ @@ -485,7 +485,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, prev.pos + prev.ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { printk(BIOS_ALERT, "Detected error on " - "hypertransport link\n"); + "hypertransport link\n"); goto end_of_chain; } } @@ -504,7 +504,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, pos = ht_lookup_slave_capability(dev); if (pos == 0) { printk(BIOS_ERR, "%s Hypertransport link capability " - "not found", dev_path(dev)); + "not found", dev_path(dev)); break; } @@ -528,7 +528,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */ if (next_unitid > (max_devfn >> 3)) { if (!end_used) { - next_unitid = + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { @@ -546,13 +546,13 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, for (func = dev; func; func = func->sibling) { func->path.pci.devfn += (next_unitid << 3); static_count = (func->path.pci.devfn >> 3) - - (dev->path.pci.devfn >> 3) + 1; + - (dev->path.pci.devfn >> 3) + 1; last_func = func; } /* Compute the number of unitids consumed. */ printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", - dev_path(dev), count, static_count); + dev_path(dev), count, static_count); if (count < static_count) count = static_count; @@ -575,8 +575,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, bus->reset_needed |= ht_setup_link(&prev, dev, pos); printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", - dev_path(dev), dev->vendor, dev->device, - (dev->enabled? "enabled" : "disabled"), next_unitid); + dev_path(dev), dev->vendor, dev->device, + (dev->enabled? "enabled" : "disabled"), next_unitid); } while (last_unitid != next_unitid); @@ -611,7 +611,7 @@ end_of_chain: ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", - real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); + real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); } #endif next_unitid = max_unitid; @@ -632,7 +632,7 @@ end_of_chain: printk(BIOS_DEBUG, "%s\n", dev_path(left)); printk(BIOS_ERR, "HT: Leftover static devices. " - "Check your devicetree.cb\n"); + "Check your devicetree.cb\n"); /* * Put back the leftover static device, and let pci_scan_bus() @@ -682,11 +682,11 @@ static struct pci_operations ht_bus_ops_pci = { struct device_operations default_ht_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = ht_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &ht_bus_ops_pci, + .init = 0, + .scan_bus = ht_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &ht_bus_ops_pci, }; diff --git a/src/device/oprom/include/x86emu/fpu_regs.h b/src/device/oprom/include/x86emu/fpu_regs.h index 7c7df85..4085e61 100644 --- a/src/device/oprom/include/x86emu/fpu_regs.h +++ b/src/device/oprom/include/x86emu/fpu_regs.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for FPU register definitions. * @@ -46,16 +46,16 @@ /* Basic 8087 register can hold any of the following values: */ union x86_fpu_reg_u { - s8 tenbytes[10]; - double dval; - float fval; - s16 sval; - s32 lval; + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; }; struct x86_fpu_reg { union x86_fpu_reg_u reg; - char tag; + char tag; }; /* @@ -67,24 +67,24 @@ struct x86_fpu_reg { * attempt the conversion. */ -#define X86_FPU_VALID 0x80 -#define X86_FPU_REGTYP(r) ((r) & 0x7F) +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) -#define X86_FPU_WORD 0x0 -#define X86_FPU_SHORT 0x1 -#define X86_FPU_LONG 0x2 -#define X86_FPU_FLOAT 0x3 -#define X86_FPU_DOUBLE 0x4 -#define X86_FPU_LDBL 0x5 -#define X86_FPU_BSD 0x6 +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 #define X86_FPU_STKTOP 0 struct x86_fpu_registers { struct x86_fpu_reg x86_fpu_stack[8]; - int x86_fpu_flags; - int x86_fpu_config; /* rounding modes, etc. */ - short x86_fpu_tos, x86_fpu_bos; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; }; #pragma pack() diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 4bf1294..eb2b75e 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for x86 register definitions. * @@ -170,18 +170,18 @@ struct i386_segment_regs { #define R_GS seg.GS /* flag conditions */ -#define FB_CF 0x0001 /* CARRY flag */ -#define FB_PF 0x0004 /* PARITY flag */ -#define FB_AF 0x0010 /* AUX flag */ -#define FB_ZF 0x0040 /* ZERO flag */ -#define FB_SF 0x0080 /* SIGN flag */ -#define FB_TF 0x0100 /* TRAP flag */ -#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define FB_DF 0x0400 /* DIR flag */ -#define FB_OF 0x0800 /* OVERFLOW flag */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ /* 80286 and above always have bit#1 set */ -#define F_ALWAYS_ON (0x0002) /* flag bits always on */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* * Define a mask for only those flag bits we will ever pass back @@ -191,18 +191,18 @@ struct i386_segment_regs { /* following bits masked in to a 16bit quantity */ -#define F_CF 0x0001 /* CARRY flag */ -#define F_PF 0x0004 /* PARITY flag */ -#define F_AF 0x0010 /* AUX flag */ -#define F_ZF 0x0040 /* ZERO flag */ -#define F_SF 0x0080 /* SIGN flag */ -#define F_TF 0x0100 /* TRAP flag */ -#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define F_DF 0x0400 /* DIR flag */ -#define F_OF 0x0800 /* OVERFLOW flag */ +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ #define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) -#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) @@ -210,42 +210,42 @@ struct i386_segment_regs { #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) -#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ -#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ -#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ -#define F_ALL_CALC 0xff0000 /* All have been calced */ +#define F_ALL_CALC 0xff0000 /* All have been calced */ /* * Emulator machine state. * Segment usage control. */ -#define SYSMODE_SEG_DS_SS 0x00000001 -#define SYSMODE_SEGOVR_CS 0x00000002 -#define SYSMODE_SEGOVR_DS 0x00000004 -#define SYSMODE_SEGOVR_ES 0x00000008 -#define SYSMODE_SEGOVR_FS 0x00000010 -#define SYSMODE_SEGOVR_GS 0x00000020 -#define SYSMODE_SEGOVR_SS 0x00000040 -#define SYSMODE_PREFIX_REPE 0x00000080 -#define SYSMODE_PREFIX_REPNE 0x00000100 -#define SYSMODE_PREFIX_DATA 0x00000200 -#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 //phueper: for REP(E|NE) Instructions, we need to decide whether it should be //using the 32bit ECX register as or the 16bit CX register as count register -#define SYSMODE_32BIT_REP 0x00000800 -#define SYSMODE_INTR_PENDING 0x10000000 -#define SYSMODE_EXTRN_INTR 0x20000000 -#define SYSMODE_HALTED 0x40000000 +#define SYSMODE_32BIT_REP 0x00000800 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 -#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS) -#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ @@ -256,40 +256,40 @@ struct i386_segment_regs { SYSMODE_PREFIX_ADDR | \ SYSMODE_32BIT_REP) -#define INTR_SYNCH 0x1 -#define INTR_ASYNCH 0x2 -#define INTR_HALTED 0x4 +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 typedef struct { - struct i386_general_regs gen; - struct i386_special_regs spc; - struct i386_segment_regs seg; + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; /* * MODE contains information on: - * REPE prefix 2 bits repe,repne - * SEGMENT overrides 5 bits normal,DS,SS,CS,ES - * Delayed flag set 3 bits (zero, signed, parity) - * reserved 6 bits - * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits - * Extern interrupt 1 bits - * Halted 1 bits + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits */ - u32 mode; - volatile int intr; /* mask of pending interrupts */ - volatile int debug; + u32 mode; + volatile int intr; /* mask of pending interrupts */ + volatile int debug; #if CONFIG_X86EMU_DEBUG - int check; - u16 saved_ip; - u16 saved_cs; - int enc_pos; - int enc_str_pos; - char decode_buf[32]; /* encoded byte stream */ - char decoded_buf[256]; /* disassembled strings */ + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ #endif - u8 intno; - u8 __pad[3]; + u8 intno; + u8 __pad[3]; } X86EMU_regs; /**************************************************************************** @@ -307,7 +307,7 @@ typedef struct { unsigned long mem_base; unsigned long mem_size; unsigned long abseg; - void* private; + void* private; X86EMU_regs x86; } X86EMU_sysEnv; @@ -316,7 +316,7 @@ typedef struct { /*----------------------------- Global Variables --------------------------*/ #ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif /* Global emulator machine state. @@ -324,8 +324,8 @@ extern "C" { /* Use "C" linkage when in C++ mode */ * We keep it global to avoid pointer dereferences in the code for speed. */ -extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env #define X86_EAX M.x86.R_EAX #define X86_EBX M.x86.R_EBX @@ -366,7 +366,7 @@ extern X86EMU_sysEnv _X86EMU_env; #define X86_DH M.x86.R_DH #ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_REGS_H */ diff --git a/src/device/oprom/include/x86emu/types.h b/src/device/oprom/include/x86emu/types.h index bb6dab44..61de104 100644 --- a/src/device/oprom/include/x86emu/types.h +++ b/src/device/oprom/include/x86emu/types.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for x86 emulator type definitions. * diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index b912bd2..7ee1483 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,11 +30,11 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for public specific functions. -* Any application linking against us should only -* include this header +* Any application linking against us should only +* include this header * ****************************************************************************/ /* $XFree86: xc/extras/x86emu/include/x86emu.h,v 1.2 2000/11/21 23:10:25 tsi Exp $ */ @@ -73,10 +73,10 @@ x86emu.h MEMBERS: inb - Function to read a byte from an I/O port inw - Function to read a word from an I/O port -inl - Function to read a dword from an I/O port +inl - Function to read a dword from an I/O port outb - Function to write a byte to an I/O port -outw - Function to write a word to an I/O port -outl - Function to write a dword to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port ****************************************************************************/ typedef struct { u8 (X86APIP inb)(X86EMU_pioAddr addr); @@ -104,7 +104,7 @@ x86emu.h MEMBERS: rdb - Function to read a byte from an address rdw - Function to read a word from an address -rdl - Function to read a dword from an address +rdl - Function to read a dword from an address wrb - Function to write a byte to an address wrw - Function to write a word to an address wrl - Function to write a dword to an address @@ -139,7 +139,7 @@ extern X86EMU_intrFuncs _X86EMU_intrTab[256]; /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); @@ -164,25 +164,25 @@ void X86EMU_halt_sys(void); /* Debug options */ -#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ -#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ -#define DEBUG_STEP_F 0x000004 -#define DEBUG_DISASSEMBLE_F 0x000008 -#define DEBUG_BREAK_F 0x000010 -#define DEBUG_SVC_F 0x000020 -#define DEBUG_FS_F 0x000080 -#define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ -#define DEBUG_TRACECALL_F 0x000400 -#define DEBUG_INSTRUMENT_F 0x000800 -#define DEBUG_MEM_TRACE_F 0x001000 -#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 #define DEBUG_DECODE_NOPRINT_F 0x008000 -#define DEBUG_SAVE_IP_CS_F 0x010000 -#define DEBUG_TRACEJMP_F 0x020000 -#define DEBUG_TRACEJMP_REGS_F 0x040000 -#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) +#define DEBUG_SAVE_IP_CS_F 0x010000 +#define DEBUG_TRACEJMP_F 0x020000 +#define DEBUG_TRACEJMP_REGS_F 0x040000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) void X86EMU_trace_regs(void); void X86EMU_trace_xregs(void); @@ -191,7 +191,7 @@ int X86EMU_trace_on(void); int X86EMU_trace_off(void); #ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_X86EMU_H */ diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 4385c03..b23f97b 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -272,8 +272,8 @@ void vbe_set_graphics(void) struct jpeg_decdata *decdata; decdata = malloc(sizeof(*decdata)); unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + "bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; @@ -458,10 +458,10 @@ int asmlinkage interrupt_handler(u32 intnumber, #if CONFIG_REALMODE_DEBUG printk(BIOS_DEBUG, "oprom: INT# 0x%x\n", intnumber); printk(BIOS_DEBUG, "oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", - eax, ebx, ecx, edx); + eax, ebx, ecx, edx); printk(BIOS_DEBUG, "oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", ebp, esp, edi, esi); - printk(BIOS_DEBUG, "oprom: ip: %04x cs: %04x flags: %08x\n", + printk(BIOS_DEBUG, "oprom: ip: %04x cs: %04x flags: %08x\n", ip, cs, flags); #endif diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index 54cf374..aee895b 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -343,12 +343,12 @@ __interrupt_handler_16bit = RELOCATED(.) pushl %eax /* ... and make it the first parameter */ /* Switch to protected mode */ - movl %cr0, %eax + movl %cr0, %eax orl $PE, %eax movl %eax, %cr0 /* ... and jump to a 32 bit code segment. */ - data32 ljmp $0x10, $RELOCATED(1f) + data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 mov $0x18, %ax diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 383c736..32a5e9e 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -81,7 +81,7 @@ int int10_handler(void) X86_EBX &= 0x00ff; res = 1; break; - default: + default: printk(BIOS_WARNING, "Unknown INT10 function %04x!\n", X86_EAX & 0xffff); break; @@ -107,7 +107,7 @@ int int16_handler(void) X86_EFLAGS |= 1<<6; // Zero Flag set (no key available) res = 1; break; - default: + default: printk(BIOS_WARNING, "Unknown INT16 function %04x!\n", X86_EAX & 0xffff); break; @@ -216,7 +216,7 @@ int int1a_handler(void) #if CONFIG_REALMODE_DEBUG printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", - func, bus, devfn, reg, X86_ECX); + func, bus, devfn, reg, X86_ECX); #endif X86_EAX &= 0xffff00ff; /* Clear AH */ X86_EAX |= PCIBIOS_SUCCESSFUL; diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index a3ede4a..39e5842 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -1,5 +1,5 @@ - License information - ------------------- + License information + ------------------- The x86emu library is under a BSD style license, comaptible with the XFree86 and X licenses used by XFree86. The diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index b3f4b6e..c80b3d0 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file contains the code to handle debugging of the -* emulator. +* emulator. * ****************************************************************************/ @@ -43,31 +43,31 @@ #ifdef DEBUG -static void print_encoded_bytes (u16 s, u16 o); -static void print_decoded_instruction (void); -int parse_line (char *s, int *ps, int *n); +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +int parse_line (char *s, int *ps, int *n); /* should look something like debug's output. */ void X86EMU_trace_regs (void) { if (DEBUG_TRACE()) { if (M.x86.mode & (SYSMODE_PREFIX_DATA | SYSMODE_PREFIX_ADDR)) { - x86emu_dump_xregs(); + x86emu_dump_xregs(); } else { - x86emu_dump_regs(); + x86emu_dump_regs(); } } if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { - printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); - print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); - print_decoded_instruction(); + printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); } } void X86EMU_trace_xregs (void) { if (DEBUG_TRACE()) { - x86emu_dump_xregs(); + x86emu_dump_xregs(); } } @@ -97,8 +97,8 @@ void disassemble_forward (u16 seg, u16 off, int n) * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) - * {just_disassemble(); goto EndOfInstruction;} - * if (debug&DEBUG_TRACE) trace_regs(r,m); + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); * * ...... and at the last line of the routine. * @@ -131,8 +131,8 @@ void disassemble_forward (u16 seg, u16 off, int n) * Note the use of a copy of the register structure... */ for (i=0; i<n; i++) { - op1 = (*sys_rdb)(((u32)M.x86.R_CS<<4) + (M.x86.R_IP++)); - (x86emu_optab[op1])(op1); + op1 = (*sys_rdb)(((u32)M.x86.R_CS<<4) + (M.x86.R_IP++)); + (x86emu_optab[op1])(op1); } /* end major hack mode. */ } @@ -186,7 +186,7 @@ static void print_encoded_bytes (u16 s, u16 o) int i; char buf1[64]; for (i=0; i< M.x86.enc_pos; i++) { - sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); + sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); } printf("%-20s ",buf1); } @@ -201,8 +201,8 @@ void x86emu_print_int_vect (u16 iv) u16 seg,off; if (iv > 256) return; - seg = fetch_data_word_abs(0,iv*4); - off = fetch_data_word_abs(0,iv*4+2); + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); printf("%04x:%04x ", seg, off); } @@ -215,14 +215,14 @@ void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) current = start; while (end <= off + amt) { - printf("%04x:%04x ", seg, start); - for (i=start; i< off; i++) - printf(" "); - for ( ; i< end; i++) - printf("%02x ", fetch_data_byte_abs(seg,i)); - printf("\n"); - start = end; - end = start + 16; + printf("%04x:%04x ", seg, start); + for (i=start; i< off; i++) + printf(" "); + for ( ; i< end; i++) + printf("%02x ", fetch_data_byte_abs(seg,i)); + printf("\n"); + start = end; + end = start + 16; } } @@ -234,88 +234,88 @@ void x86emu_single_step (void) int ntok; int cmd; int done; - int segment; + int segment; int offset; static int breakpoint; static int noDecode = 1; char *p; - if (DEBUG_BREAK()) { - if (M.x86.saved_ip != breakpoint) { - return; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - M.x86.debug |= DEBUG_TRACE_F; - M.x86.debug &= ~DEBUG_BREAK_F; - print_decoded_instruction (); - X86EMU_trace_regs(); - } - } + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } done=0; offset = M.x86.saved_ip; while (!done) { - printf("-"); - p = fgets(s, 1023, stdin); - cmd = parse_line(s, ps, &ntok); - switch(cmd) { - case 'u': - disassemble_forward(M.x86.saved_cs,(u16)offset,10); - break; - case 'd': - if (ntok == 2) { - segment = M.x86.saved_cs; - offset = ps[1]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else if (ntok == 3) { - segment = ps[1]; - offset = ps[2]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else { - segment = M.x86.saved_cs; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } - break; - case 'c': - M.x86.debug ^= DEBUG_TRACECALL_F; - break; - case 's': - M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; - break; - case 'r': - X86EMU_trace_regs(); - break; - case 'x': - X86EMU_trace_xregs(); - break; - case 'g': - if (ntok == 2) { - breakpoint = ps[1]; - if (noDecode) { - M.x86.debug |= DEBUG_DECODE_NOPRINT_F; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - } - M.x86.debug &= ~DEBUG_TRACE_F; - M.x86.debug |= DEBUG_BREAK_F; - done = 1; - } - break; - case 'q': - M.x86.debug |= DEBUG_EXIT; - return; + printf("-"); + p = fgets(s, 1023, stdin); + cmd = parse_line(s, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; case 'P': - noDecode = (noDecode)?0:1; - printf("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); - break; - case 't': + noDecode = (noDecode)?0:1; + printf("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); + break; + case 't': case 0: - done = 1; - break; - } + done = 1; + break; + } } #endif } @@ -340,23 +340,23 @@ int parse_line (char *s, int *ps, int *n) ps[*n] = *s; switch (*s) { case '\n': - *n += 1; - return 0; + *n += 1; + return 0; default: - cmd = *s; - *n += 1; + cmd = *s; + *n += 1; } while (1) { - while (*s != ' ' && *s != '\t' && *s != '\n') s++; + while (*s != ' ' && *s != '\t' && *s != '\n') s++; - if (*s == '\n') - return cmd; + if (*s == '\n') + return cmd; - while(*s == ' ' || *s == '\t') s++; + while(*s == ' ' || *s == '\t') s++; - sscanf(s,"%x",&ps[*n]); - *n += 1; + sscanf(s,"%x",&ps[*n]); + *n += 1; } #else return 0; @@ -380,22 +380,22 @@ void x86emu_dump_regs (void) printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("IP=%04x ", M.x86.R_IP ); - if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ - else printf("NV "); + if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ + else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); - else printf("UP "); + else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); - else printf("DI "); + else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); - else printf("PL "); + else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); - else printf("NZ "); + else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); - else printf("NA "); + else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); - else printf("PO "); + else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); - else printf("NC "); + else printf("NC "); printf("\n"); } @@ -414,21 +414,21 @@ void x86emu_dump_xregs (void) printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("EIP=%08x\n\t", M.x86.R_EIP ); - if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ - else printf("NV "); + if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ + else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); - else printf("UP "); + else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); - else printf("DI "); + else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); - else printf("PL "); + else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); - else printf("NZ "); + else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); - else printf("NA "); + else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); - else printf("PO "); + else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); - else printf("NC "); + else printf("NC "); printf("\n"); } diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 6858f15..3d497d4 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for debug definitions. * @@ -49,16 +49,16 @@ /* checks to be enabled for "runtime" */ -#define CHECK_IP_FETCH_F 0x1 -#define CHECK_SP_ACCESS_F 0x2 -#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ -#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ #ifdef DEBUG -# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) -# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) -# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) -# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) #else # define CHECK_IP_FETCH() # define CHECK_SP_ACCESS() @@ -68,42 +68,42 @@ #ifdef DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) -# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) -# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) -# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) # define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) -# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) -# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) -# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) -# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) -# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) -# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) # define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) # define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) -# define DEBUG_TRACEJMP() (M.x86.debug & DEBUG_TRACEJMP_F) -# define DEBUG_TRACEJMPREGS() (M.x86.debug & DEBUG_TRACEJMP_REGS_F) -# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_TRACEJMP() (M.x86.debug & DEBUG_TRACEJMP_F) +# define DEBUG_TRACEJMPREGS() (M.x86.debug & DEBUG_TRACEJMP_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) # define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) # define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) #else # define DEBUG_INSTRUMENT() 0 -# define DEBUG_DECODE() 0 -# define DEBUG_TRACE() 0 -# define DEBUG_STEP() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 # define DEBUG_DISASSEMBLE() 0 -# define DEBUG_BREAK() 0 -# define DEBUG_SVC() 0 -# define DEBUG_SAVE_IP_CS() 0 -# define DEBUG_FS() 0 -# define DEBUG_PROC() 0 -# define DEBUG_SYSINT() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 # define DEBUG_TRACECALL() 0 # define DEBUG_TRACECALLREGS() 0 -# define DEBUG_TRACEJMP() 0 -# define DEBUG_TRACEJMPREGS() 0 -# define DEBUG_SYS() 0 +# define DEBUG_TRACEJMP() 0 +# define DEBUG_TRACEJMPREGS() 0 +# define DEBUG_SYS() 0 # define DEBUG_MEM_TRACE() 0 # define DEBUG_IO_TRACE() 0 # define DEBUG_DECODE_NOPRINT() 0 @@ -122,15 +122,15 @@ * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ -#define INC_DECODED_INST_LEN(x) \ - if (DEBUG_DECODE()) \ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ x86emu_inc_decoded_inst_len(x) -#define SAVE_IP_CS(x,y) \ +#define SAVE_IP_CS(x,y) \ if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ - | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ - M.x86.saved_cs = x; \ - M.x86.saved_ip = y; \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ } #else # define INC_DECODED_INST_LEN(x) @@ -140,11 +140,11 @@ #endif #ifdef DEBUG -#define TRACE_REGS() \ - if (DEBUG_DISASSEMBLE()) { \ - x86emu_just_disassemble(); \ - goto EndOfTheInstructionProcedure; \ - } \ +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() #else # define TRACE_REGS() @@ -171,17 +171,17 @@ #endif #ifdef DEBUG -# define CALL_TRACE(u,v,w,x,s) \ +# define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ printf("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); -# define RETURN_TRACE(u,v,w,x,s) \ +# define RETURN_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ printf("%04x:%04x: RET %s %04x:%04x\n",u,v,s,w,x); -# define JMP_TRACE(u,v,w,x,s) \ +# define JMP_TRACE(u,v,w,x,s) \ if (DEBUG_TRACEJMPREGS()) \ x86emu_dump_regs(); \ if (DEBUG_TRACEJMP()) \ @@ -207,7 +207,7 @@ /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif void x86emu_inc_decoded_inst_len (int x); @@ -228,7 +228,7 @@ void x86emu_check_data_access (uint s, uint o); void disassemble_forward (u16 seg, u16 off, int n); #ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DEBUG_H */ diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index 3d3f77d..cc5e22c 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines which are related to -* instruction decoding and accesses of immediate data via IP. etc. +* instruction decoding and accesses of immediate data via IP. etc. * ****************************************************************************/ @@ -50,19 +50,19 @@ static void x86emu_intr_handle(void) u8 intno; if (M.x86.intr & INTR_SYNCH) { - intno = M.x86.intno; - if (_X86EMU_intrTab[intno]) { - (*_X86EMU_intrTab[intno])(intno); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intno * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intno * 4); - M.x86.intr = 0; - } + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } } } @@ -97,34 +97,34 @@ void X86EMU_exec(void) DB(x86emu_end_instr();) for (;;) { -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - /* If debugging, save the IP and CS values. */ - SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); - INC_DECODED_INST_LEN(1); - if (M.x86.intr) { - if (M.x86.intr & INTR_HALTED) { -DB( if (M.x86.R_SP != 0) { - printf("halted\n"); - X86EMU_trace_regs(); - } - else { - if (M.x86.debug) - printf("Service completed successfully\n"); - }) - return; - } - if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || - !ACCESS_FLAG(F_IF)) { - x86emu_intr_handle(); - } - } - op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - (*x86emu_optab[op1])(op1); - //if (M.x86.debug & DEBUG_EXIT) { - // M.x86.debug &= ~DEBUG_EXIT; - // return; - //} +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + printf("halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + printf("Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + //if (M.x86.debug & DEBUG_EXIT) { + // M.x86.debug &= ~DEBUG_EXIT; + // return; + //} } } @@ -139,9 +139,9 @@ void X86EMU_halt_sys(void) /**************************************************************************** PARAMETERS: -mod - Mod value from decoded byte -regh - Reg h value from decoded byte -regl - Reg l value from decoded byte +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte REMARKS: Raise the specified interrupt to be handled before the execution of the @@ -157,7 +157,7 @@ void fetch_decode_modrm( int fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); *mod = (fetched >> 6) & 0x03; @@ -180,7 +180,7 @@ u8 fetch_byte_imm(void) u8 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); return fetched; @@ -201,7 +201,7 @@ u16 fetch_word_imm(void) u16 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 2; INC_DECODED_INST_LEN(2); @@ -223,7 +223,7 @@ u32 fetch_long_imm(void) u32 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 4; INC_DECODED_INST_LEN(4); @@ -263,33 +263,33 @@ _INLINE u32 get_data_segment(void) { #define GET_SEGMENT(segment) switch (M.x86.mode & SYSMODE_SEGMASK) { - case 0: /* default case: use ds register */ + case 0: /* default case: use ds register */ case SYSMODE_SEGOVR_DS: case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: - return M.x86.R_DS; - case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ - return M.x86.R_SS; + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; case SYSMODE_SEGOVR_CS: case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: - return M.x86.R_CS; + return M.x86.R_CS; case SYSMODE_SEGOVR_ES: case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: - return M.x86.R_ES; + return M.x86.R_ES; case SYSMODE_SEGOVR_FS: case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: - return M.x86.R_FS; + return M.x86.R_FS; case SYSMODE_SEGOVR_GS: case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: - return M.x86.R_GS; + return M.x86.R_GS; case SYSMODE_SEGOVR_SS: case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: - return M.x86.R_SS; + return M.x86.R_SS; default: #ifdef DEBUG - printf("error: should not happen: multiple overrides.\n"); + printf("error: should not happen: multiple overrides.\n"); #endif - HALT_SYS(); - return 0; + HALT_SYS(); + return 0; } } @@ -307,7 +307,7 @@ u8 fetch_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdb)((get_data_segment() << 4) + offset); } @@ -326,7 +326,7 @@ u16 fetch_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdw)((get_data_segment() << 4) + offset); } @@ -345,7 +345,7 @@ u32 fetch_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdl)((get_data_segment() << 4) + offset); } @@ -366,7 +366,7 @@ u8 fetch_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdb)(((u32)segment << 4) + offset); } @@ -387,7 +387,7 @@ u16 fetch_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdw)(((u32)segment << 4) + offset); } @@ -408,7 +408,7 @@ u32 fetch_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdl)(((u32)segment << 4) + offset); } @@ -416,7 +416,7 @@ u32 fetch_data_long_abs( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -430,7 +430,7 @@ void store_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrb)((get_data_segment() << 4) + offset, val); } @@ -438,7 +438,7 @@ void store_data_byte( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -452,7 +452,7 @@ void store_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrw)((get_data_segment() << 4) + offset, val); } @@ -460,7 +460,7 @@ void store_data_word( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a long value to an segmented memory location. The segment used is @@ -474,7 +474,7 @@ void store_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrl)((get_data_segment() << 4) + offset, val); } @@ -483,7 +483,7 @@ void store_data_long( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a byte value to an absolute memory location. @@ -497,7 +497,7 @@ void store_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrb)(((u32)segment << 4) + offset, val); } @@ -506,7 +506,7 @@ void store_data_byte_abs( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a word value to an absolute memory location. @@ -520,7 +520,7 @@ void store_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrw)(((u32)segment << 4) + offset, val); } @@ -529,7 +529,7 @@ void store_data_word_abs( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store REMARKS: Writes a long value to an absolute memory location. @@ -543,7 +543,7 @@ void store_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrl)(((u32)segment << 4) + offset, val); } @@ -564,32 +564,32 @@ u8* decode_rm_byte_register( { switch (reg) { case 0: - DECODE_PRINTF("AL"); - return &M.x86.R_AL; + DECODE_PRINTF("AL"); + return &M.x86.R_AL; case 1: - DECODE_PRINTF("CL"); - return &M.x86.R_CL; + DECODE_PRINTF("CL"); + return &M.x86.R_CL; case 2: - DECODE_PRINTF("DL"); - return &M.x86.R_DL; + DECODE_PRINTF("DL"); + return &M.x86.R_DL; case 3: - DECODE_PRINTF("BL"); - return &M.x86.R_BL; + DECODE_PRINTF("BL"); + return &M.x86.R_BL; case 4: - DECODE_PRINTF("AH"); - return &M.x86.R_AH; + DECODE_PRINTF("AH"); + return &M.x86.R_AH; case 5: - DECODE_PRINTF("CH"); - return &M.x86.R_CH; + DECODE_PRINTF("CH"); + return &M.x86.R_CH; case 6: - DECODE_PRINTF("DH"); - return &M.x86.R_DH; + DECODE_PRINTF("DH"); + return &M.x86.R_DH; case 7: - DECODE_PRINTF("BH"); - return &M.x86.R_BH; + DECODE_PRINTF("BH"); + return &M.x86.R_BH; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -608,32 +608,32 @@ u16* decode_rm_word_register( { switch (reg) { case 0: - DECODE_PRINTF("AX"); - return &M.x86.R_AX; + DECODE_PRINTF("AX"); + return &M.x86.R_AX; case 1: - DECODE_PRINTF("CX"); - return &M.x86.R_CX; + DECODE_PRINTF("CX"); + return &M.x86.R_CX; case 2: - DECODE_PRINTF("DX"); - return &M.x86.R_DX; + DECODE_PRINTF("DX"); + return &M.x86.R_DX; case 3: - DECODE_PRINTF("BX"); - return &M.x86.R_BX; + DECODE_PRINTF("BX"); + return &M.x86.R_BX; case 4: - DECODE_PRINTF("SP"); - return &M.x86.R_SP; + DECODE_PRINTF("SP"); + return &M.x86.R_SP; case 5: - DECODE_PRINTF("BP"); - return &M.x86.R_BP; + DECODE_PRINTF("BP"); + return &M.x86.R_BP; case 6: - DECODE_PRINTF("SI"); - return &M.x86.R_SI; + DECODE_PRINTF("SI"); + return &M.x86.R_SI; case 7: - DECODE_PRINTF("DI"); - return &M.x86.R_DI; + DECODE_PRINTF("DI"); + return &M.x86.R_DI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -652,32 +652,32 @@ u32* decode_rm_long_register( { switch (reg) { case 0: - DECODE_PRINTF("EAX"); - return &M.x86.R_EAX; + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; case 1: - DECODE_PRINTF("ECX"); - return &M.x86.R_ECX; + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; case 2: - DECODE_PRINTF("EDX"); - return &M.x86.R_EDX; + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; case 3: - DECODE_PRINTF("EBX"); - return &M.x86.R_EBX; + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; case 4: - DECODE_PRINTF("ESP"); - return &M.x86.R_ESP; + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; case 5: - DECODE_PRINTF("EBP"); - return &M.x86.R_EBP; + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; case 6: - DECODE_PRINTF("ESI"); - return &M.x86.R_ESI; + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; case 7: - DECODE_PRINTF("EDI"); - return &M.x86.R_EDI; + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -697,30 +697,30 @@ u16* decode_rm_seg_register( { switch (reg) { case 0: - DECODE_PRINTF("ES"); - return &M.x86.R_ES; + DECODE_PRINTF("ES"); + return &M.x86.R_ES; case 1: - DECODE_PRINTF("CS"); - return &M.x86.R_CS; + DECODE_PRINTF("CS"); + return &M.x86.R_CS; case 2: - DECODE_PRINTF("SS"); - return &M.x86.R_SS; + DECODE_PRINTF("SS"); + return &M.x86.R_SS; case 3: - DECODE_PRINTF("DS"); - return &M.x86.R_DS; + DECODE_PRINTF("DS"); + return &M.x86.R_DS; case 4: - DECODE_PRINTF("FS"); - return &M.x86.R_FS; + DECODE_PRINTF("FS"); + return &M.x86.R_FS; case 5: - DECODE_PRINTF("GS"); - return &M.x86.R_GS; + DECODE_PRINTF("GS"); + return &M.x86.R_GS; case 6: case 7: - DECODE_PRINTF("ILLEGAL SEGREG"); - break; + DECODE_PRINTF("ILLEGAL SEGREG"); + break; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -741,38 +741,38 @@ static unsigned decode_sib_si( { scale = 1 << scale; if (scale > 1) { - DECODE_PRINTF2("[%d*", scale); + DECODE_PRINTF2("[%d*", scale); } else { - DECODE_PRINTF("["); + DECODE_PRINTF("["); } switch (index) { case 0: - DECODE_PRINTF("EAX]"); - return M.x86.R_EAX * index; + DECODE_PRINTF("EAX]"); + return M.x86.R_EAX * index; case 1: - DECODE_PRINTF("ECX]"); - return M.x86.R_ECX * index; + DECODE_PRINTF("ECX]"); + return M.x86.R_ECX * index; case 2: - DECODE_PRINTF("EDX]"); - return M.x86.R_EDX * index; + DECODE_PRINTF("EDX]"); + return M.x86.R_EDX * index; case 3: - DECODE_PRINTF("EBX]"); - return M.x86.R_EBX * index; + DECODE_PRINTF("EBX]"); + return M.x86.R_EBX * index; case 4: - DECODE_PRINTF("0]"); - return 0; + DECODE_PRINTF("0]"); + return 0; case 5: - DECODE_PRINTF("EBP]"); - return M.x86.R_EBP * index; + DECODE_PRINTF("EBP]"); + return M.x86.R_EBP * index; case 6: - DECODE_PRINTF("ESI]"); - return M.x86.R_ESI * index; + DECODE_PRINTF("ESI]"); + return M.x86.R_ESI * index; case 7: - DECODE_PRINTF("EDI]"); - return M.x86.R_EDI * index; + DECODE_PRINTF("EDI]"); + return M.x86.R_EDI * index; } HALT_SYS(); - return 0; /* NOT REACHED OR REACHED ON ERROR */ + return 0; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -797,58 +797,58 @@ static unsigned decode_sib_address( switch (base) { case 0: - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 1: - DECODE_PRINTF("[ECX]"); - offset = M.x86.R_ECX; - break; + DECODE_PRINTF("[ECX]"); + offset = M.x86.R_ECX; + break; case 2: - DECODE_PRINTF("[EDX]"); - offset = M.x86.R_EDX; - break; + DECODE_PRINTF("[EDX]"); + offset = M.x86.R_EDX; + break; case 3: - DECODE_PRINTF("[EBX]"); - offset = M.x86.R_EBX; - break; + DECODE_PRINTF("[EBX]"); + offset = M.x86.R_EBX; + break; case 4: - DECODE_PRINTF("[ESP]"); - offset = M.x86.R_ESP; - break; + DECODE_PRINTF("[ESP]"); + offset = M.x86.R_ESP; + break; case 5: - switch (mod) { - case 0: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - offset = displacement; - break; - case 1: - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - case 2: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - default: - HALT_SYS(); - } - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + switch (mod) { + case 0: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + offset = displacement; + break; + case 1: + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + case 2: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + default: + HALT_SYS(); + } + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 6: - DECODE_PRINTF("[ESI]"); - offset = M.x86.R_ESI; - break; + DECODE_PRINTF("[ESI]"); + offset = M.x86.R_ESI; + break; case 7: - DECODE_PRINTF("[EDI]"); - offset = M.x86.R_EDI; - break; + DECODE_PRINTF("[EDI]"); + offset = M.x86.R_EDI; + break; default: - HALT_SYS(); + HALT_SYS(); } offset += decode_sib_si(ss, index); return offset; @@ -865,14 +865,14 @@ REMARKS: Return the offset given by mod=00 addressing. Also enables the decoding of instructions. -NOTE: The code which specifies the corresponding segment (ds vs ss) - below in the case of [BP+..]. The assumption here is that at the - point that this subroutine is called, the bit corresponding to - SYSMODE_SEG_DS_SS will be zero. After every instruction - except the segment override instructions, this bit (as well - as any bits indicating segment overrides) will be clear. So - if a SS access is needed, set this bit. Otherwise, DS access - occurs (unless any of the segment override bits are set). +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). ****************************************************************************/ unsigned decode_rm00_address( int rm) @@ -880,64 +880,64 @@ unsigned decode_rm00_address( unsigned offset; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[EAX]"); - return M.x86.R_EAX; - case 1: - DECODE_PRINTF("[ECX]"); - return M.x86.R_ECX; - case 2: - DECODE_PRINTF("[EDX]"); - return M.x86.R_EDX; - case 3: - DECODE_PRINTF("[EBX]"); - return M.x86.R_EBX; - case 4: - return decode_sib_address(0); - case 5: - offset = fetch_long_imm(); - DECODE_PRINTF2("[%08x]", offset); - return offset; - case 6: - DECODE_PRINTF("[ESI]"); - return M.x86.R_ESI; - case 7: - DECODE_PRINTF("[EDI]"); - return M.x86.R_EDI; - } + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + return decode_sib_address(0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } } else { - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[BX+SI]"); - return (M.x86.R_BX + M.x86.R_SI) & 0xffff; - case 1: - DECODE_PRINTF("[BX+DI]"); - return (M.x86.R_BX + M.x86.R_DI) & 0xffff; - case 2: - DECODE_PRINTF("[BP+SI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI) & 0xffff; - case 3: - DECODE_PRINTF("[BP+DI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI) & 0xffff; - case 4: - DECODE_PRINTF("[SI]"); - return M.x86.R_SI; - case 5: - DECODE_PRINTF("[DI]"); - return M.x86.R_DI; - case 6: - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]", offset); - return offset; - case 7: - DECODE_PRINTF("[BX]"); - return M.x86.R_BX; - } + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } } HALT_SYS(); return 0; @@ -960,76 +960,76 @@ unsigned decode_rm01_address( int displacement; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - if (rm != 4) - displacement = (s8)fetch_byte_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(1); - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + /* 32-bit addressing */ + if (rm != 4) + displacement = (s8)fetch_byte_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(1); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - /* 16-bit addressing */ - displacement = (s8)fetch_byte_imm(); - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + /* 16-bit addressing */ + displacement = (s8)fetch_byte_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } /**************************************************************************** @@ -1047,79 +1047,79 @@ unsigned decode_rm10_address( int rm) { if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - int displacement; - - /* 32-bit addressing */ - if (rm != 4) - displacement = (s32)fetch_long_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(2); - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + int displacement; + + /* 32-bit addressing */ + if (rm != 4) + displacement = (s32)fetch_long_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(2); + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - int displacement = (s16)fetch_word_imm(); - - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + int displacement = (s16)fetch_word_imm(); + + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } diff --git a/src/device/oprom/x86emu/decode.h b/src/device/oprom/x86emu/decode.h index 99ed7f6..80ed1a4 100644 --- a/src/device/oprom/x86emu/decode.h +++ b/src/device/oprom/x86emu/decode.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for instruction decoding logic. * @@ -47,31 +47,31 @@ #define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) #define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) #define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) -#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif void x86emu_intr_raise (u8 type); -void fetch_decode_modrm (int *mod,int *regh,int *regl); -u8 fetch_byte_imm (void); -u16 fetch_word_imm (void); -u32 fetch_long_imm (void); -u8 fetch_data_byte (uint offset); -u8 fetch_data_byte_abs (uint segment, uint offset); -u16 fetch_data_word (uint offset); -u16 fetch_data_word_abs (uint segment, uint offset); -u32 fetch_data_long (uint offset); -u32 fetch_data_long_abs (uint segment, uint offset); -void store_data_byte (uint offset, u8 val); -void store_data_byte_abs (uint segment, uint offset, u8 val); -void store_data_word (uint offset, u16 val); -void store_data_word_abs (uint segment, uint offset, u16 val); -void store_data_long (uint offset, u32 val); -void store_data_long_abs (uint segment, uint offset, u32 val); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); u8* decode_rm_byte_register(int reg); u16* decode_rm_word_register(int reg); u32* decode_rm_long_register(int reg); @@ -82,7 +82,7 @@ unsigned decode_rm10_address(int rm); unsigned decode_rmXX_address(int mod, int rm); #ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DECODE_H */ diff --git a/src/device/oprom/x86emu/fpu.c b/src/device/oprom/x86emu/fpu.c index 7edebd4..2896023 100644 --- a/src/device/oprom/x86emu/fpu.c +++ b/src/device/oprom/x86emu/fpu.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file contains the code to implement the decoding and -* emulation of the FPU instructions. +* emulation of the FPU instructions. * ****************************************************************************/ @@ -108,192 +108,192 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { - DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); } #endif switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - if (rh < 4) { - DECODE_PRINTF2("ST(%d)\n", stkelem); - } else { - DECODE_PRINTF("\n"); - } - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); - break; - case 1: - x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); - break; - case 2: - switch (rl) { - case 0: - x86emu_fpu_R_nop(); - break; - default: - x86emu_fpu_illegal(); - break; - } - case 3: - x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); - break; - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); - break; - default: - /* 2,3,6,7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 5: - switch (rl) { - case 0: - x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); - break; - default: - /* 7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 6: - switch (rl) { - case 0: - x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_R_decstp(); - break; - case 7: - x86emu_fpu_R_incstp(); - break; - } - break; - - case 7: - switch (rl) { - case 0: - x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); - break; - case 6: - case 7: - default: - x86emu_fpu_illegal(); - break; - } - break; - - default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); - break; - case 4: - x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); - break; - } - } + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } } #endif /* X86EMU_FPU_PRESENT */ DECODE_CLEAR_SEGOVR(); @@ -319,7 +319,7 @@ static const char *x86emu_fpu_op_da_tab[] = { "FIDIVR\tDWORD PTR ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", - "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", }; #endif /* DEBUG */ @@ -336,54 +336,54 @@ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - x86emu_fpu_illegal(); - break; + x86emu_fpu_illegal(); + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); - break; - case 2: - x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); - break; - case 5: - x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); - break; - case 6: - x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); - break; - case 7: - x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -415,95 +415,95 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); - } else if (rh == 4) { /* === 11 10 0 nnn */ - switch (rl) { - case 0: - DECODE_PRINTF("FENI\n"); - break; - case 1: - DECODE_PRINTF("FDISI\n"); - break; - case 2: - DECODE_PRINTF("FCLEX\n"); - break; - case 3: - DECODE_PRINTF("FINIT\n"); - break; - } + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } } else { - DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } #endif /* DEBUG */ switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - break; + destoffset = decode_rm00_address(rl); + break; case 1: - destoffset = decode_rm01_address(rl); - break; + destoffset = decode_rm01_address(rl); + break; case 2: - destoffset = decode_rm10_address(rl); - break; - case 3: /* register to register */ - break; + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_feni(); - break; - case 1: - x86emu_fpu_R_fdisi(); - break; - case 2: - x86emu_fpu_R_fclex(); - break; - case 3: - x86emu_fpu_R_finit(); - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_illegal(); - break; - case 5: - x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); - break; - case 6: - x86emu_fpu_illegal(); - break; - case 7: - x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -544,80 +544,80 @@ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); - break; - case 2: - x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); - break; - case 5: - x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); - break; - case 6: - x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); - break; - case 7: - x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -654,70 +654,70 @@ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -761,82 +761,82 @@ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - if (stkelem == 1) - x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); - else - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); - break; - case 2: - x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -880,70 +880,70 @@ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d)\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); - break; - case 5: - x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); - break; - case 6: - x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); - break; - case 7: - x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); diff --git a/src/device/oprom/x86emu/fpu.h b/src/device/oprom/x86emu/fpu.h index 5fb2714..1a866c7 100644 --- a/src/device/oprom/x86emu/fpu.h +++ b/src/device/oprom/x86emu/fpu.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for FPU instruction decoding. * @@ -40,7 +40,7 @@ #define __X86EMU_FPU_H #ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif /* these have to be defined, whether 8087 support compiled in or not. */ @@ -55,7 +55,7 @@ extern void x86emuOp_esc_coprocess_de (u8 op1); extern void x86emuOp_esc_coprocess_df (u8 op1); #ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_FPU_H */ diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index c805b58..e334672 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,10 +30,10 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 processor instructions. +* and emulation of all the x86 processor instructions. * * There are approximately 250 subroutines in here, which correspond * to the 256 byte-"opcodes" found on the 8086. The table which @@ -84,38 +84,38 @@ static const char *x86emu_GenOpName[8] = { /* used by several opcodes */ static u8 (*genop_byte_operation[])(u8 d, u8 s) = { - add_byte, /* 00 */ - or_byte, /* 01 */ - adc_byte, /* 02 */ - sbb_byte, /* 03 */ - and_byte, /* 04 */ - sub_byte, /* 05 */ - xor_byte, /* 06 */ - cmp_byte, /* 07 */ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ }; static u16 (*genop_word_operation[])(u16 d, u16 s) = { - add_word, /*00 */ - or_word, /*01 */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ - sub_word, /*05 */ - xor_word, /*06 */ - cmp_word, /*07 */ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ }; static u32 (*genop_long_operation[])(u32 d, u32 s) = { - add_long, /*00 */ - or_long, /*01 */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ - sub_long, /*05 */ - xor_long, /*06 */ - cmp_long, /*07 */ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ }; /* used by opcodes 80, c0, d0, and d2. */ @@ -127,7 +127,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) = rcr_byte, shl_byte, shr_byte, - shl_byte, /* sal_byte === shl_byte by definition */ + shl_byte, /* sal_byte === shl_byte by definition */ sar_byte, }; @@ -140,7 +140,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) = rcr_word, shl_word, shr_word, - shl_word, /* sal_byte === shl_byte by definition */ + shl_word, /* sal_byte === shl_byte by definition */ sar_word, }; @@ -153,7 +153,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = rcr_long, shl_long, shr_long, - shl_long, /* sal_byte === shl_byte by definition */ + shl_long, /* sal_byte === shl_byte by definition */ sar_long, }; @@ -176,21 +176,21 @@ static void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); - TRACE_REGS(); - DB( printf("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-1,op1)); - HALT_SYS(); - } + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( printf("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1)); + HALT_SYS(); + } else { - /* If we get here, it means the stack pointer is back to zero - * so we are just returning from an emulator service call - * so therte is no need to display an error message. We trap - * the emulator with an 0xF1 opcode to finish the service - * call. - */ - X86EMU_halt_sys(); - } + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } END_OF_INSTR(); } @@ -212,25 +212,25 @@ static void x86emuOp_genop_byte_RM_R(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) - { destoffset = decode_rmXX_address(mod,rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_byte_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_byte(destoffset, destval); - } + { destoffset = decode_rmXX_address(mod,rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_byte_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_byte(destoffset, destval); + } else - { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_byte_operation[op1](*destreg, *srcreg); - } + { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, *srcreg); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -252,52 +252,52 @@ static void x86emuOp_genop_word_RM_R(u8 op1) FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) { - destoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_long_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_word_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_long_operation[op1](*destreg, *srcreg); - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_long_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_word_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_long_operation[op1](*destreg, *srcreg); + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -321,15 +321,15 @@ static void x86emuOp_genop_byte_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod,rl); - srcval = fetch_data_byte(srcoffset); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - srcval = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod,rl); + srcval = fetch_data_byte(srcoffset); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + srcval = *srcreg; } DECODE_PRINTF("\n"); TRACE_AND_STEP(); @@ -357,40 +357,40 @@ static void x86emuOp_genop_word_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, srcval); - } else { - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, srcval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); - } else { - u16 *srcreg; - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + srcoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, srcval); + } else { + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, srcval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); + } else { + u16 *srcreg; + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -429,20 +429,20 @@ static void x86emuOp_genop_word_AX_IMM(u8 op1) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); + M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); } else { - M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); + M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -682,17 +682,17 @@ static void x86emuOp_inc_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("INC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -708,17 +708,17 @@ static void x86emuOp_dec_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("DEC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -734,17 +734,17 @@ static void x86emuOp_push_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("PUSH\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -760,17 +760,17 @@ static void x86emuOp_pop_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("POP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_long(); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_long(); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_word(); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -784,33 +784,33 @@ static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHAD\n"); + DECODE_PRINTF("PUSHAD\n"); } else { - DECODE_PRINTF("PUSHA\n"); + DECODE_PRINTF("PUSHA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 old_sp = M.x86.R_ESP; - - push_long(M.x86.R_EAX); - push_long(M.x86.R_ECX); - push_long(M.x86.R_EDX); - push_long(M.x86.R_EBX); - push_long(old_sp); - push_long(M.x86.R_EBP); - push_long(M.x86.R_ESI); - push_long(M.x86.R_EDI); + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); } else { - u16 old_sp = M.x86.R_SP; - - push_word(M.x86.R_AX); - push_word(M.x86.R_CX); - push_word(M.x86.R_DX); - push_word(M.x86.R_BX); - push_word(old_sp); - push_word(M.x86.R_BP); - push_word(M.x86.R_SI); - push_word(M.x86.R_DI); + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -824,36 +824,36 @@ static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPAD\n"); + DECODE_PRINTF("POPAD\n"); } else { - DECODE_PRINTF("POPA\n"); + DECODE_PRINTF("POPA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - M.x86.R_ESI = pop_long(); - M.x86.R_EBP = pop_long(); - M.x86.R_ESP += 4; /* skip ESP */ - M.x86.R_EBX = pop_long(); - M.x86.R_EDX = pop_long(); - M.x86.R_ECX = pop_long(); - M.x86.R_EAX = pop_long(); + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); } else { - M.x86.R_DI = pop_word(); - M.x86.R_SI = pop_word(); - M.x86.R_BP = pop_word(); - M.x86.R_SP += 2; /* skip SP */ - M.x86.R_BX = pop_word(); - M.x86.R_DX = pop_word(); - M.x86.R_CX = pop_word(); - M.x86.R_AX = pop_word(); + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } -/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ -/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ /**************************************************************************** REMARKS: @@ -927,16 +927,16 @@ static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - imm = fetch_long_imm(); + imm = fetch_long_imm(); } else { - imm = fetch_word_imm(); + imm = fetch_word_imm(); } DECODE_PRINTF2("PUSH\t%x\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word((u16)imm); + push_word((u16)imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -955,95 +955,95 @@ static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1062,9 +1062,9 @@ static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("PUSH\t%d\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word(imm); + push_word(imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1084,92 +1084,92 @@ static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1197,11 +1197,11 @@ static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INSD\n"); - ins(4); + DECODE_PRINTF("INSD\n"); + ins(4); } else { - DECODE_PRINTF("INSW\n"); - ins(2); + DECODE_PRINTF("INSW\n"); + ins(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1230,11 +1230,11 @@ static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUTSD\n"); - outs(4); + DECODE_PRINTF("OUTSD\n"); + outs(4); } else { - DECODE_PRINTF("OUTSW\n"); - outs(2); + DECODE_PRINTF("OUTSW\n"); + outs(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1259,7 +1259,7 @@ static void x86emuOp_jump_near_cond(u8 op1) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (cond) { - M.x86.R_IP = target; + M.x86.R_IP = target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R_IP, " NEAR COND "); } DECODE_CLEAR_SEGOVR(); @@ -1287,59 +1287,59 @@ static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_byte_operation[rh]) (*destreg, imm); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_byte_operation[rh]) (*destreg, imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1363,37 +1363,37 @@ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* @@ -1401,51 +1401,51 @@ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) * mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_long_operation[rh]) (*destreg, imm); - } else { - u16 *destreg, imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_word_operation[rh]) (*destreg, imm); - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_long_operation[rh]) (*destreg, imm); + } else { + u16 *destreg, imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_word_operation[rh]) (*destreg, imm); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1473,56 +1473,56 @@ static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_byte_operation[rh]) (*destreg, imm); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_byte_operation[rh]) (*destreg, imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1547,83 +1547,83 @@ static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod,rl); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_long_operation[rh]) (*destreg, imm); - } else { - u16 *destreg, imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_word_operation[rh]) (*destreg, imm); - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod,rl); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_long_operation[rh]) (*destreg, imm); + } else { + u16 *destreg, imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_word_operation[rh]) (*destreg, imm); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1644,20 +1644,20 @@ static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(*destreg, *srcreg); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1676,48 +1676,48 @@ static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1739,25 +1739,25 @@ static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1776,59 +1776,59 @@ static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 tmp; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } else { - u16 *destreg,*srcreg; - u16 tmp; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1848,19 +1848,19 @@ static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1879,44 +1879,44 @@ static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1937,20 +1937,20 @@ static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1969,49 +1969,49 @@ static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2032,20 +2032,20 @@ static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2064,21 +2064,21 @@ static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u32)destoffset; + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; } else { - u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - } + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } } /* else { undefined. Do nothing. } */ DECODE_CLEAR_SEGOVR(); @@ -2100,20 +2100,20 @@ static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } /* * Clean up, and reset all the R_xSP pointers to the correct @@ -2138,42 +2138,42 @@ static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_long(); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_word(); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2205,23 +2205,23 @@ static void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - DECODE_PRINTF("XCHG\tEAX,"); - reg32 = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_EAX; - M.x86.R_EAX = *reg32; - *reg32 = tmp; + u32 *reg32; + DECODE_PRINTF("XCHG\tEAX,"); + reg32 = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_EAX; + M.x86.R_EAX = *reg32; + *reg32 = tmp; } else { - u16 *reg16; - DECODE_PRINTF("XCHG\tAX,"); - reg16 = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_AX; - M.x86.R_AX = *reg16; - *reg16 = (u16)tmp; + u16 *reg16; + DECODE_PRINTF("XCHG\tAX,"); + reg16 = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_AX; + M.x86.R_AX = *reg16; + *reg16 = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2235,23 +2235,23 @@ static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CWDE\n"); + DECODE_PRINTF("CWDE\n"); } else { - DECODE_PRINTF("CBW\n"); + DECODE_PRINTF("CBW\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_AX & 0x8000) { - M.x86.R_EAX |= 0xffff0000; - } else { - M.x86.R_EAX &= 0x0000ffff; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } } else { - if (M.x86.R_AL & 0x80) { - M.x86.R_AH = 0xff; - } else { - M.x86.R_AH = 0x0; - } + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2265,24 +2265,24 @@ static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CDQ\n"); + DECODE_PRINTF("CDQ\n"); } else { - DECODE_PRINTF("CWD\n"); + DECODE_PRINTF("CWD\n"); } DECODE_PRINTF("CWD\n"); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_EAX & 0x80000000) { - M.x86.R_EDX = 0xffffffff; - } else { - M.x86.R_EDX = 0x0; - } + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } } else { - if (M.x86.R_AX & 0x8000) { - M.x86.R_DX = 0xffff; - } else { - M.x86.R_DX = 0x0; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2299,11 +2299,11 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - faroff = fetch_long_imm(); - farseg = fetch_word_imm(); + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); } else { - faroff = fetch_word_imm(); - farseg = fetch_word_imm(); + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); } DECODE_PRINTF2("%04x:", farseg); DECODE_PRINTF2("%04x\n", faroff); @@ -2319,9 +2319,9 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_CS); M.x86.R_CS = farseg; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EIP); + push_long(M.x86.R_EIP); } else { - push_word(M.x86.R_IP); + push_word(M.x86.R_IP); } M.x86.R_EIP = faroff & 0xffff; DECODE_CLEAR_SEGOVR(); @@ -2352,18 +2352,18 @@ static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHFD\n"); + DECODE_PRINTF("PUSHFD\n"); } else { - DECODE_PRINTF("PUSHF\n"); + DECODE_PRINTF("PUSHF\n"); } TRACE_AND_STEP(); /* clear out *all* bits not representing flags, and turn on real bits */ flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(flags); + push_long(flags); } else { - push_word((u16)flags); + push_word((u16)flags); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2377,15 +2377,15 @@ static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPFD\n"); + DECODE_PRINTF("POPFD\n"); } else { - DECODE_PRINTF("POPF\n"); + DECODE_PRINTF("POPF\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EFLG = pop_long(); + M.x86.R_EFLG = pop_long(); } else { - M.x86.R_FLG = pop_word(); + M.x86.R_FLG = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2454,15 +2454,15 @@ static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); } else { - DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(offset); + M.x86.R_EAX = fetch_data_long(offset); } else { - M.x86.R_AX = fetch_data_word(offset); + M.x86.R_AX = fetch_data_word(offset); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2497,15 +2497,15 @@ static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); } else { - DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long(offset, M.x86.R_EAX); + store_data_long(offset, M.x86.R_EAX); } else { - store_data_word(offset, M.x86.R_AX); + store_data_word(offset, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2524,27 +2524,27 @@ static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOVS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - val = fetch_data_byte(M.x86.R_SI); - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2562,41 +2562,41 @@ static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOVS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("MOVS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long(M.x86.R_SI); - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); - } else { - val = fetch_data_word(M.x86.R_SI); - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2615,35 +2615,35 @@ static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("CMPS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2660,53 +2660,53 @@ static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMPS\tDWORD\n"); - inc = 4; + DECODE_PRINTF("CMPS\tDWORD\n"); + inc = 4; } else { - DECODE_PRINTF("CMPS\tWORD\n"); - inc = 2; + DECODE_PRINTF("CMPS\tWORD\n"); + inc = 2; } if (ACCESS_FLAG(F_DF)) /* down */ - inc = -inc; + inc = -inc; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2740,18 +2740,18 @@ static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("TEST\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF("TEST\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - test_long(M.x86.R_EAX, srcval); + test_long(M.x86.R_EAX, srcval); } else { - test_word(M.x86.R_AX, (u16)srcval); + test_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2768,27 +2768,27 @@ static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("STOS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_DI += inc; + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2805,38 +2805,38 @@ static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("STOS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("STOS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); - } else { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); - } - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2854,26 +2854,26 @@ static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LODS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_SI += inc; + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2890,38 +2890,38 @@ static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("LODS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("LODS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(M.x86.R_SI); - } else { - M.x86.R_AX = fetch_data_word(M.x86.R_SI); - } - M.x86.R_SI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2940,47 +2940,47 @@ static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("SCAS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_DI += inc; + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2997,72 +2997,72 @@ static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SCAS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("SCAS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3101,19 +3101,19 @@ static void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOV\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - reg32 = DECODE_RM_LONG_REGISTER(op1); - srcval = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg32 = srcval; + u32 *reg32; + reg32 = DECODE_RM_LONG_REGISTER(op1); + srcval = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg32 = srcval; } else { - u16 *reg16; - reg16 = DECODE_RM_WORD_REGISTER(op1); - srcval = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg16 = (u16)srcval; + u16 *reg16; + reg16 = DECODE_RM_WORD_REGISTER(op1); + srcval = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg16 = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3140,57 +3140,57 @@ static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3215,83 +3215,83 @@ static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3346,15 +3346,15 @@ static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LES\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); } - /* else UNDEFINED! register to register */ + /* else UNDEFINED! register to register */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3374,13 +3374,13 @@ static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LDS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); } /* else UNDEFINED! */ DECODE_CLEAR_SEGOVR(); @@ -3402,22 +3402,22 @@ static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); } if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3436,49 +3436,49 @@ static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 imm; - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { u16 *destreg; u16 imm; - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3503,12 +3503,12 @@ static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_BP); frame_pointer = M.x86.R_SP; if (nesting > 0) { - for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); - } - push_word(frame_pointer); - } + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); @@ -3583,13 +3583,13 @@ static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[3]) { (*_X86EMU_intrTab[3])(3); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(3 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(3 * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3613,13 +3613,13 @@ static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[intnum]) { (*_X86EMU_intrTab[intnum])(intnum); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intnum * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intnum * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3637,18 +3637,18 @@ static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("INTO\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) { - tmp = mem_access_word(4 * 4 + 2); + tmp = mem_access_word(4 * 4 + 2); if (_X86EMU_intrTab[4]) { (*_X86EMU_intrTab[4])(4); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(4 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(4 * 4); - } + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3692,54 +3692,54 @@ static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, 1); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3763,82 +3763,82 @@ static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *destreg; - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (*destreg, 1); - *destreg = destval; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { u16 destval; u16 *destreg; - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (*destreg, 1); - *destreg = destval; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3865,55 +3865,55 @@ static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3938,79 +3938,79 @@ static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4028,9 +4028,9 @@ static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); - TRACE_REGS(); - HALT_SYS(); + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); } TRACE_AND_STEP(); /* note the type change here --- returning AL and AH in AX. */ @@ -4092,11 +4092,11 @@ static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && !ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and !ZF */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && !ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and !ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4116,11 +4116,11 @@ static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and ZF */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4140,11 +4140,11 @@ static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0) /* (E)CX != 0 */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0) /* (E)CX != 0 */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4166,7 +4166,7 @@ static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (M.x86.R_CX == 0) { - M.x86.R_IP = target; + M.x86.R_IP = target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R_IP, " CXZ "); } DECODE_CLEAR_SEGOVR(); @@ -4203,15 +4203,15 @@ static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("EAX,%x\n", port); + DECODE_PRINTF2("EAX,%x\n", port); } else { - DECODE_PRINTF2("AX,%x\n", port); + DECODE_PRINTF2("AX,%x\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(port); + M.x86.R_EAX = (*sys_inl)(port); } else { - M.x86.R_AX = (*sys_inw)(port); + M.x86.R_AX = (*sys_inw)(port); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4247,15 +4247,15 @@ static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("%x,EAX\n", port); + DECODE_PRINTF2("%x,EAX\n", port); } else { - DECODE_PRINTF2("%x,AX\n", port); + DECODE_PRINTF2("%x,AX\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(port, M.x86.R_EAX); + (*sys_outl)(port, M.x86.R_EAX); } else { - (*sys_outw)(port, M.x86.R_AX); + (*sys_outw)(port, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4273,23 +4273,23 @@ static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip32 = (s32) fetch_long_imm(); - ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", (u16)ip32); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); } else { - ip16 = (s16) fetch_word_imm(); - ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip16); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EIP); - M.x86.R_EIP = ip32 & 0xffff; + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; } else { - push_word(M.x86.R_IP); - M.x86.R_EIP = ip16; + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4306,19 +4306,19 @@ static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("JMP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip = (u32)fetch_long_imm(); + ip = (u32)fetch_long_imm(); ip += (u32)M.x86.R_EIP; DECODE_PRINTF2("%08x\n", (u32)ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); TRACE_AND_STEP(); M.x86.R_EIP = (u32)ip; } else { - ip = (s16)fetch_word_imm(); - ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", (u16)ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); - TRACE_AND_STEP(); - M.x86.R_IP = (u16)ip; + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4336,9 +4336,9 @@ static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("JMP\tFAR "); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip = fetch_long_imm(); + ip = fetch_long_imm(); } else { - ip = fetch_word_imm(); + ip = fetch_word_imm(); } cs = fetch_word_imm(); DECODE_PRINTF2("%04x:", cs); @@ -4394,15 +4394,15 @@ static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("IN\tEAX,DX\n"); + DECODE_PRINTF("IN\tEAX,DX\n"); } else { - DECODE_PRINTF("IN\tAX,DX\n"); + DECODE_PRINTF("IN\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); } else { - M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4430,15 +4430,15 @@ static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUT\tDX,EAX\n"); + DECODE_PRINTF("OUT\tDX,EAX\n"); } else { - DECODE_PRINTF("OUT\tDX,AX\n"); + DECODE_PRINTF("OUT\tDX,AX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); } else { - (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4470,7 +4470,7 @@ static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPNE; if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.mode |= SYSMODE_32BIT_REP; + M.x86.mode |= SYSMODE_32BIT_REP; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4486,7 +4486,7 @@ static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPE; if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.mode |= SYSMODE_32BIT_REP; + M.x86.mode |= SYSMODE_32BIT_REP; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4537,100 +4537,100 @@ static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(destval); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - } else { /* mod=11 */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_byte(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_byte(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(*destreg); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(*destreg); - break; - } + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(destval); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + } else { /* mod=11 */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4650,213 +4650,213 @@ static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval, srcval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_long(destoffset); - - switch (rh) { - case 0: - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(destval); - break; - } - } else { - u16 destval, srcval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_word(destoffset); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(destval); - break; - } - } - - } else { /* mod=11 */ - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_long(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_long(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(*destreg); - break; - } - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_word(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_word(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(*destreg); - break; - } - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval, srcval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_long(destoffset); + + switch (rh) { + case 0: + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(destval); + break; + } + } else { + u16 destval, srcval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_word(destoffset); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(destval); + break; + } + } + + } else { /* mod=11 */ + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + break; + } + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4968,49 +4968,49 @@ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("INC\t"); - break; - case 1: - DECODE_PRINTF("DEC\t"); - break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - if (rh == 0) - destval = inc_byte(destval); - else - destval = dec_byte(destval); - store_data_byte(destoffset, destval); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + if (rh == 0) + destval = inc_byte(destval); + else + destval = dec_byte(destval); + store_data_byte(destoffset, destval); } else { - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - if (rh == 0) - *destreg = inc_byte(*destreg); - else - *destreg = dec_byte(*destreg); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + if (rh == 0) + *destreg = inc_byte(*destreg); + else + *destreg = dec_byte(*destreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -5034,185 +5034,185 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tDWORD PTR "); - } else { - DECODE_PRINTF("INC\tWORD PTR "); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tDWORD PTR "); - } else { - DECODE_PRINTF("DEC\tWORD PTR "); - } - break; - case 2: - DECODE_PRINTF("CALL\t "); - break; - case 3: - DECODE_PRINTF("CALL\tFAR "); - break; - case 4: - DECODE_PRINTF("JMP\t"); - break; - case 5: - DECODE_PRINTF("JMP\tFAR "); - break; - case 6: - DECODE_PRINTF("PUSH\t"); - break; - case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval32 = inc_long(destval32); - store_data_long(destoffset, destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: /* dec word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval32 = dec_long(destval32); - store_data_long(destoffset, destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, destval, " WORD "); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, destval2, destval, " FAR "); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval32 = inc_long(destval32); + store_data_long(destoffset, destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval32 = dec_long(destval32); + store_data_long(destoffset, destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, destval, " WORD "); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, destval2, destval, " FAR "); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } } else { - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = inc_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_word(*destreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = dec_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_word(*destreg); - } - break; - case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; - break; - case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - - case 4: /* jmp ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); - break; - case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*destreg); - } - break; - } + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = inc_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = dec_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); diff --git a/src/device/oprom/x86emu/ops.h b/src/device/oprom/x86emu/ops.h index 825b9ea..a5129fe 100644 --- a/src/device/oprom/x86emu/ops.h +++ b/src/device/oprom/x86emu/ops.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for operand decoding functions. * diff --git a/src/device/oprom/x86emu/ops2.c b/src/device/oprom/x86emu/ops2.c index 95ec09a..efb7e90 100644 --- a/src/device/oprom/x86emu/ops2.c +++ b/src/device/oprom/x86emu/ops2.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,13 +28,13 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 extended two-byte processor -* instructions. +* and emulation of all the x86 extended two-byte processor +* instructions. * ****************************************************************************/ @@ -55,7 +55,7 @@ static void x86emuOp2_illegal_op(u8 op2) DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printf("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2, op2); + M.x86.R_CS, M.x86.R_IP-2, op2); HALT_SYS(); END_OF_INSTR(); } @@ -76,8 +76,8 @@ static void x86emuOp2_opc_01(u8 op2) switch(rh) { case 4: // SMSW (Store Machine Status Word) - // Decode the mod byte to find the addressing - // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1) + // Decode the mod byte to find the addressing + // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1) #define SMSW_INITIAL_VALUE 0x10 DECODE_PRINTF("SMSW\t"); switch (mod) { @@ -106,7 +106,7 @@ static void x86emuOp2_opc_01(u8 op2) DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE IN 0F 01\n"); TRACE_REGS(); printf("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2, op2); + M.x86.R_CS, M.x86.R_IP-2, op2); HALT_SYS(); break; } @@ -216,69 +216,69 @@ int x86emu_check_jump_condition(u8 op) { switch (op) { case 0x0: - DECODE_PRINTF("JO\t"); - return ACCESS_FLAG(F_OF); + DECODE_PRINTF("JO\t"); + return ACCESS_FLAG(F_OF); case 0x1: - DECODE_PRINTF("JNO\t"); - return !ACCESS_FLAG(F_OF); - break; + DECODE_PRINTF("JNO\t"); + return !ACCESS_FLAG(F_OF); + break; case 0x2: - DECODE_PRINTF("JB\t"); - return ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JB\t"); + return ACCESS_FLAG(F_CF); + break; case 0x3: - DECODE_PRINTF("JNB\t"); - return !ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JNB\t"); + return !ACCESS_FLAG(F_CF); + break; case 0x4: - DECODE_PRINTF("JZ\t"); - return ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JZ\t"); + return ACCESS_FLAG(F_ZF); + break; case 0x5: - DECODE_PRINTF("JNZ\t"); - return !ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JNZ\t"); + return !ACCESS_FLAG(F_ZF); + break; case 0x6: - DECODE_PRINTF("JBE\t"); - return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JBE\t"); + return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x7: - DECODE_PRINTF("JNBE\t"); - return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JNBE\t"); + return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x8: - DECODE_PRINTF("JS\t"); - return ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JS\t"); + return ACCESS_FLAG(F_SF); + break; case 0x9: - DECODE_PRINTF("JNS\t"); - return !ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JNS\t"); + return !ACCESS_FLAG(F_SF); + break; case 0xa: - DECODE_PRINTF("JP\t"); - return ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JP\t"); + return ACCESS_FLAG(F_PF); + break; case 0xb: - DECODE_PRINTF("JNP\t"); - return !ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JNP\t"); + return !ACCESS_FLAG(F_PF); + break; case 0xc: - DECODE_PRINTF("JL\t"); - return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JL\t"); + return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xd: - DECODE_PRINTF("JNL\t"); - return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JNL\t"); + return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xe: - DECODE_PRINTF("JLE\t"); - return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JLE\t"); + return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; default: - DECODE_PRINTF("JNLE\t"); - return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); + DECODE_PRINTF("JNLE\t"); + return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); } } @@ -295,7 +295,7 @@ static void x86emuOp2_long_jump(u8 op2) DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) { - M.x86.R_IP = (u16)target; + M.x86.R_IP = (u16)target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R

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coreboot-gerrit November 2013