coreboot-gerrit November 2013

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New patch to review for coreboot: c0751f7 Fix VGA option rom INT15 handler
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4135 -gerrit commit c0751f73dd1d2e8953e386086cfb595df2dec41c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 23 15:00:02 2013 -0700 Fix VGA option rom INT15 handler The format of this function changed but was not updated in all mainboards. This fixes all Sandybridge/Ivybridge boards. The int15 handler no longer takes a regs structure as an argument and instead uses global variables. The yabel interface is now similar enough that we can drop the duplicate handler. Change-Id: Icdaae4d6d50884f6d7bce7a167d48cb1d4807010 Reviewed-on: https://gerrit.chromium.org/gerrit/48969 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/butterfly/mainboard.c | 152 +++++------------------------ src/mainboard/google/link/mainboard.c | 152 +++++------------------------ src/mainboard/google/parrot/mainboard.c | 152 +++++------------------------ src/mainboard/google/stout/mainboard.c | 152 +++++------------------------ 4 files changed, 91 insertions(+), 517 deletions(-) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index a1d9126..c33b9cf 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2011-2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,7 +24,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -191,15 +191,15 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res = -1; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + __func__, X86_AX); - switch (regs->eax & 0xffff) { + switch (X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -208,10 +208,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x00; /* Use video bios default */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ res = 0; break; case 0x5f35: @@ -226,10 +224,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; /* Use video bios default */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ res = 0; break; case 0x5f51: @@ -240,148 +236,46 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0001; /* Int-LVDS */ + X86_AX = 0x005f; + X86_CX = 0x0001; /* Int-LVDS */ res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + X86_CH); return 0; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x00; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) - * bit 2 = EFP - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; /* Use video bios default */ - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 1; /* Int-LVDS */ - break; - case 0x5f70: - switch (M.x86.R_CH) { - case 0: - /* Get Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CL = 0; - break; - case 1: - /* Set Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - case 2: - /* Get SG/Non-SG mode */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - M.x86.R_CH); - return 0; - } - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (*yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 *cim_verb_data; @@ -494,9 +388,9 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index f0afd81..01d4484 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -61,15 +61,15 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res=-1; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + __func__, X86_AX); - switch(regs->eax & 0xffff) { + switch(X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -78,10 +78,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x00; /* Use video bios default */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ res = 0; break; case 0x5f35: @@ -96,10 +94,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; /* Use video bios default */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ res = 0; break; case 0x5f51: @@ -110,42 +106,34 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0003; /* eDP */ + X86_AX = 0x005f; + X86_CX = 0x0003; /* eDP */ res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + X86_CH); return 0; } break; @@ -153,109 +141,13 @@ static int int15_handler(struct eregs *regs) res = 0; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x00; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) - * bit 2 = EFP - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; /* Use video bios default */ - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 3; /* eDP */ - break; - case 0x5f70: - switch (M.x86.R_CH) { - case 0: - /* Get Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CL = 0; - break; - case 1: - /* Set Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - case 2: - /* Get SG/Non-SG mode */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - M.x86.R_CH); - return 0; - } - break; - case 0x5fac: - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -343,9 +235,9 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 3822723..c07d9e2 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,7 +24,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -49,15 +49,15 @@ void mainboard_suspend_resume(void) outb(0xe1, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res=-1; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + __func__, X86_AX); - switch(regs->eax & 0xffff) { + switch(X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -66,10 +66,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x00; /* Use video bios default */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ res = 0; break; case 0x5f35: @@ -84,10 +82,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; /* Use video bios default */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ res = 0; break; case 0x5f51: @@ -98,148 +94,46 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0003; /* eDP */ + X86_AX = 0x005f; + X86_CX = 0x0003; /* eDP */ res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + X86_CH); return 0; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x00; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) - * bit 2 = EFP - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; /* Use video bios default */ - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 3; /* eDP */ - break; - case 0x5f70: - switch (M.x86.R_CH) { - case 0: - /* Get Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CL = 0; - break; - case 1: - /* Set Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - case 2: - /* Get SG/Non-SG mode */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - M.x86.R_CH); - return 0; - } - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -315,9 +209,9 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 4af0ff5..62ac7ea 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,7 +24,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -49,15 +49,15 @@ void mainboard_suspend_resume(void) ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static int int15_handler(struct eregs *regs) +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) { int res=-1; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, regs->eax & 0xffff); + __func__, X86_AX); - switch(regs->eax & 0xffff) { + switch(X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -66,10 +66,8 @@ static int int15_handler(struct eregs *regs) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffffff00; - regs->ecx |= 0x00; /* Use video bios default */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ res = 0; break; case 0x5f35: @@ -84,10 +82,8 @@ static int int15_handler(struct eregs *regs) * bit 6 = EFP2 * bit 7 = LFP2 */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; /* Use video bios default */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ res = 0; break; case 0x5f51: @@ -98,148 +94,46 @@ static int int15_handler(struct eregs *regs) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0001; + X86_AX = 0x005f; + X86_CX = 0x0001; res = 0; break; case 0x5f70: - switch ((regs->ecx >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 1: /* Set Mux */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; case 2: /* Get SG/Non-SG mode */ - regs->eax &= 0xffff0000; - regs->eax |= 0x005f; - regs->ecx &= 0xffff0000; - regs->ecx |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 0; break; default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((regs->ecx >> 8) & 0xff)); + X86_CH); return 0; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - - switch (M.x86.R_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - M.x86.R_AX = 0x005f; - M.x86.R_CL = 0x00; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) - * bit 2 = EFP - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0x0000; /* Use video bios default */ - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 1; - break; - case 0x5f70: - switch (M.x86.R_CH) { - case 0: - /* Get Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CL = 0; - break; - case 1: - /* Set Mux */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - case 2: - /* Get SG/Non-SG mode */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - M.x86.R_CH); - return 0; - } - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - M.x86.R_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE -static void int15_install(void) -{ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -#endif -#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -280,9 +174,9 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); }

1 0

New patch to review for coreboot: 349a2e2 armv7: import updated cache/MMU stuff from coreboot
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4134 -gerrit commit 349a2e20bbf67b0424804bf21dfda5632edc9b2c Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 29 13:24:29 2013 -0700 armv7: import updated cache/MMU stuff from coreboot This imports the cache/MMU code from coreboot as of 1877cee. Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48288 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/arch/armv7/cache.c | 43 +++++++++++++++++++------- payloads/libpayload/include/armv7/arch/cache.h | 23 ++++++++++++-- 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c index 9fac442..04eaa88 100644 --- a/payloads/libpayload/arch/armv7/cache.c +++ b/payloads/libpayload/arch/armv7/cache.c @@ -31,7 +31,7 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ -#include <inttypes.h> +#include <stdint.h> #include <arch/cache.h> @@ -149,14 +149,39 @@ static void dcache_op_set_way(enum dcache_op op) isb(); } +static void dcache_foreach(enum dcache_op op) +{ + uint32_t clidr; + int level; + + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x2: + case 0x3: + case 0x4: + csselr = level << 1; + write_csselr(csselr); + dcache_op_set_way(op); + break; + default: + /* no cache, icache only, or reserved */ + break; + } + } +} + void dcache_clean_invalidate_all(void) { - dcache_op_set_way(OP_DCCISW); + dcache_foreach(OP_DCCISW); } void dcache_invalidate_all(void) { - dcache_op_set_way(OP_DCISW); + dcache_foreach(OP_DCISW); } static unsigned int line_bytes(void) @@ -212,15 +237,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) void dcache_mmu_disable(void) { - uint32_t sctlr, csselr; - - /* ensure L1 data/unified cache is selected */ - csselr = read_csselr(); - csselr &= ~0xf; - write_csselr(csselr); + uint32_t sctlr; dcache_clean_invalidate_all(); - sctlr = read_sctlr(); sctlr &= ~(SCTLR_C | SCTLR_M); write_sctlr(sctlr); @@ -264,6 +283,8 @@ void armv7_invalidate_caches(void) case 0x2: case 0x4: /* dcache only or unified cache */ + csselr = level << 1; + write_csselr(csselr); dcache_invalidate_all(); break; case 0x3: @@ -272,7 +293,7 @@ void armv7_invalidate_caches(void) write_csselr(csselr); icache_invalidate_all(); - csselr = level < 1; + csselr = level << 1; write_csselr(csselr); dcache_invalidate_all(); break; diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index f074a3b..1db86dc 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -219,10 +219,29 @@ static inline void write_csselr(uint32_t val) isb(); /* ISB to sync the change to CCSIDR */ } +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ -static inline unsigned int read_sctlr(void) +static inline uint32_t read_sctlr(void) { - unsigned int val; + uint32_t val; asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); return val; }

1 0

New patch to review for coreboot: 82d6326 haswell: configure c-states
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4133 -gerrit commit 82d63269d3aa315251bc4ead223c06333ec279b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 10 14:46:25 2013 -0500 haswell: configure c-states The c-states are configured according to the BWG, however the package c-states are disabled as they currently cause platform instability. The exposed ACPI c-state to processor c-state mapping are as follows for ULT boards: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C7S long latency) ACPI(C3) = MWAIT(C10) The non-ULT boards have an expoed c-state mapping: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Included in this patch is removing the updating of current limit registers as some of the MSRs are different and the proper values are currently unknown. Lastly, some of the MSRs were renamed to match the BWG. Booted 3.8 kernel and used powertop to note package, core, and acpi c-state residency. Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48291 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/haswell/haswell.h | 14 +- src/cpu/intel/haswell/haswell_init.c | 249 +++++++++++++++---------- src/mainboard/intel/baskingridge/devicetree.cb | 12 +- src/mainboard/intel/wtm2/devicetree.cb | 12 +- 4 files changed, 168 insertions(+), 119 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index ac082b8..ab1cef4 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -59,9 +59,12 @@ #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc -#define MSR_PKGC3_IRTL 0x60a -#define MSR_PKGC6_IRTL 0x60b -#define MSR_PKGC7_IRTL 0x60c +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 #define IRTL_VALID (1 << 15) #define IRTL_1_NS (0 << 10) #define IRTL_32_NS (1 << 10) @@ -79,12 +82,7 @@ #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f -#define MSR_PP0_CURRENT_CONFIG 0x601 #define MSR_VR_CURRENT_CONFIG 0x601 -#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ -#define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ -#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU 0x614 #define MSR_PP0_POWER_LIMIT 0x638 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 85f6afd..5b53afe 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -35,87 +35,118 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> #include "haswell.h" #include "chip.h" +/* Intel suggested latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + /* - * List of supported C-states in this processor - * - * Latencies are typical worst-case package exit time in uS - * taken from the SandyBridge BIOS specification. + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. */ -#if 0 -static acpi_cstate_t cstate_map[] = { - { /* 0: C0 */ - },{ /* 1: C1 */ - .latency = 1, +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, .power = 1000, - .resource = { - .addrl = 0x00, /* MWAIT State 0 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0,0), }, - { /* 2: C1E */ - .latency = 1, + [C_STATE_C1E] = { + .latency = 0, .power = 1000, - .resource = { - .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0,1), }, - { /* 3: C3 */ - .latency = 63, - .power = 500, - .resource = { - .addrl = 0x10, /* MWAIT State 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), }, - { /* 4: C6 */ - .latency = 87, - .power = 350, - .resource = { - .addrl = 0x20, /* MWAIT State 2 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), }, - { /* 5: C7 */ - .latency = 90, - .power = 200, - .resource = { - .addrl = 0x30, /* MWAIT State 3 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), }, - { /* 6: C7S */ - .latency = 90, - .power = 200, - .resource = { - .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), }, - { 0 } }; -#endif /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -175,6 +206,17 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; +/* Dynamically determine if the part is ULT. */ +static int is_ult(void) +{ + static int ult = -1; + + if (ult < 0) + ult = (cpuid_eax(1) > 0x40650); + + return ult; +} + int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -250,24 +292,28 @@ void set_power_limits(u8 power_limit_1_time) } } -#if 0 static void configure_c_states(void) { msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 30); // Package c-state Undemotion Enable + msr.lo |= (1 << 29); // Package c-state Demotion Enable msr.lo |= (1 << 28); // C1 Auto Undemotion Enable msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - msr.lo |= 7; // No package C-state limit + msr.lo &= ~(0xf); // Clear deepest package c-state + /* FIXME: The deepest package c-state is set to C0/C1 to work around + * platform instability when package C3 or deeper c-states are used. */ + msr.lo |= 0; // Deepeset package c-state is C0/C1. wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0x7ffff; - msr.lo |= (get_pmbase() + 4); // LVL_2 base address - msr.lo |= (2 << 16); // CST Range: C7 is max C-state + msr.lo &= ~0xffff; + msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address + /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); @@ -280,37 +326,42 @@ static void configure_c_states(void) msr.lo |= (1 << 0); // Bi-directional PROCHOT# wrmsr(MSR_POWER_CTL, msr); - /* C3 Interrupt Response Time Limit */ + /* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; - wrmsr(MSR_PKGC3_IRTL, msr); + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); - /* C6 Interrupt Response Time Limit */ + /* C-state Interrupt Response Latency Control 1 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; - wrmsr(MSR_PKGC6_IRTL, msr); + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - /* C7 Interrupt Response Time Limit */ + /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; - wrmsr(MSR_PKGC7_IRTL, msr); - - /* Primary Plane Current Limit */ - msr = rdmsr(MSR_PP0_CURRENT_CONFIG); - msr.lo &= ~0x1fff; - msr.lo |= PP0_CURRENT_LIMIT; - wrmsr(MSR_PP0_CURRENT_CONFIG, msr); - - /* Secondary Plane Current Limit */ - msr = rdmsr(MSR_PP1_CURRENT_CONFIG); - msr.lo &= ~0x1fff; - if (cpuid_eax(1) >= 0x30600) - msr.lo |= PP1_CURRENT_LIMIT_IVB; - else - msr.lo |= PP1_CURRENT_LIMIT_SNB; - wrmsr(MSR_PP1_CURRENT_CONFIG, msr); + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); + + /* Haswell ULT only supoprts the 3-5 latency response registers.*/ + if (is_ult()) { + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); + } } -#endif static void configure_thermal_target(void) { @@ -481,7 +532,7 @@ static void haswell_init(device_t cpu) setup_lapic(); /* Configure C States */ - //configure_c_states(); + configure_c_states(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); @@ -555,6 +606,6 @@ static struct cpu_device_id cpu_table[] = { static const struct cpu_driver driver __cpu_driver = { .ops = &cpu_dev_ops, .id_table = cpu_table, - /* .cstates = cstate_map, */ + .cstates = cstate_map, }; diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index fa3f3e7..a173aaa 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -17,13 +17,13 @@ chip northbridge/intel/haswell # Magic APIC ID to locate this chip device lapic 0xACAC off end - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 5e1ca3a..3193369 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -17,13 +17,13 @@ chip northbridge/intel/haswell # Magic APIC ID to locate this chip device lapic 0xACAC off end - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10) - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10) end end

1 0

New patch to review for coreboot: 79355c6 lynxpoint: Build intermediate step to add LynxPoint ME image
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4132 -gerrit commit 79355c6110ca0a825aea7deebdea31153c3e8a34 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 19 11:03:40 2013 -0700 lynxpoint: Build intermediate step to add LynxPoint ME image This is needed to successfully build fox_wtm2 from external repo. Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48676 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f1a82fb..1cc995e 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -20,8 +20,7 @@ # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -# FIXME, uncomment as soon as we have ME firmware in the blobs repo -# INTERMEDIATE:=lynxpoint_add_me +INTERMEDIATE:=lynxpoint_add_me ramstage-y += pch.c ramstage-y += azalia.c

1 0

New patch to review for coreboot: 29b74c5 Fix compile error in chromeos by adding stddef.h
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4131 -gerrit commit 29b74c5ccf3f1cba52cfa98e0bb33ec7c29aedc0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 8 09:32:12 2013 -0700 Fix compile error in chromeos by adding stddef.h Compile was failing with the following error: In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0, from src/vendorcode/google/chromeos/chromeos.c:22: vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t' src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload': src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function) Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48289 --- src/vendorcode/google/chromeos/chromeos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 658694d..6f1fe72 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stddef.h> #include "chromeos.h" #if CONFIG_VBOOT_VERIFY_FIRMWARE #include "vboot_handoff.h"

1 0

New patch to review for coreboot: f60d3f6 haswell: Put each logical processor in its own P-state domain
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4130 -gerrit commit f60d3f60309ad6e4e4990c6e86a4b4dba9f96e41 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 19 10:02:23 2013 -0700 haswell: Put each logical processor in its own P-state domain The recommendation from Intel is to report each core as a separate logical domain in the _PSD table. This goes against the recommendation in the ACPI specification because all of these cores are on the same package and share a VR so they will do voltage transitions together. The reasoning is that with a larger number of logical processors the P-state often ramps too quickly resulting in higher power consumption. By exposing each core as a separate domain the OS can manage them individually allowing the socket to select the optimum frequency. $ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT $ iasl -d /tmp/SSDT Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000001, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000002, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000003, 0x000000FE, 0x00000001 } }) } Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48662 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index a4d9cd9..9e10c75 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -254,7 +254,7 @@ static int generate_P_state_entries(int core, int cores_per_package) len += acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + len += acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ len += acpigen_write_name("_PSS"); @@ -346,7 +346,7 @@ void generate_cpu_entries(void) /* Generate P-state tables */ len_pr += generate_P_state_entries( - cpuID-1, cores_per_package); + coreID-1, cores_per_package); /* Generate C-state tables */ len_pr += generate_C_state_entries();

1 0

New patch to review for coreboot: f9fce4a haswell: Update microcode for ULT/40651 to rev 8
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4129 -gerrit commit f9fce4a4b6c8d761836f7ad71f54ba752f6a4cfe Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 19 09:47:58 2013 -0700 haswell: Update microcode for ULT/40651 to rev 8 $ cat /sys/devices/system/cpu/cpu*/microcode/version 0x8 0x8 0x8 0x8 Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48661 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- .../intel/haswell/microcode-M7240651_00000006.h | 960 --------------------- .../intel/haswell/microcode-M7240651_00000008.h | 960 +++++++++++++++++++++ src/cpu/intel/haswell/microcode_blob.h | 2 +- 3 files changed, 961 insertions(+), 961 deletions(-) diff --git a/src/cpu/intel/haswell/microcode-M7240651_00000006.h b/src/cpu/intel/haswell/microcode-M7240651_00000006.h deleted file mode 100644 index 7df48a9..0000000 --- a/src/cpu/intel/haswell/microcode-M7240651_00000006.h +++ /dev/null @@ -1,960 +0,0 @@ -0x00000001, 0x00000006, 0x02222013, 0x00040651, -0xc9c88122, 0x00000001, 0x00000072, 0x00003bd0, -0x00003c00, 0x00000000, 0x00000000, 0x00000000, -0x00000000, 0x000000a1, 0x00020001, 0x00000006, -0x00000000, 0x00000e41, 0x20130221, 0x00000e41, -0x00000001, 0x00040651, 0x00000000, 0x00000000, -0x00000000, 0x00000000, 0x00000000, 0x00000000, -0x00000000, 0x00000000, 0x00000000, 0x00000000, -0x00000000, 0x00000000, 0x00000000, 0x00000000, -0x28f5c8c7, 0x9e112164, 0xf02f86e8, 0xf6b6111d, -0x3c4e5d43, 0xd650ad15, 0x38aa12f0, 0xa22e6707, -0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6, -0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58, -0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068, -0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142, -0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1, -0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f, -0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c, -0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606, -0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531, -0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786, -0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01, -0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4, -0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66, -0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184, -0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84, -0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c, -0x00000011, 0xb446b9bb, 0x11a39f7e, 0x83a4e800, -0xf403aa18, 0x12d1dc1e, 0x438bea79, 0xd7808b62, -0x51b1b426, 0x7b7d0b59, 0x7ca0d77c, 0x5104e85b, -0xcf72fbb2, 0xde64ad8b, 0x18555138, 0xd1b30f33, -0x51f7abc6, 0xb9f5f98a, 0x63433b31, 0x020fb6ec, -0xc83d63c4, 0x5235d1c1, 0x75f744ca, 0x1a2a203a, -0xd2acee38, 0x0257ee06, 0x743dc8fd, 0x7092432f, -0xd669ef00, 0x406bd83f, 0xbf41491b, 0x97f73536, -0xfd3d1815, 0x197dedcd, 0x619286eb, 0xf463e603, -0xc4a6391f, 0x70b5c1aa, 0xe97b562f, 0xbee42bdc, -0xc5f9161b, 0x19c16776, 0x54677a02, 0x577e4564, -0x3f7f0a9e, 0xf2b94d7d, 0x8a2bee71, 0xe5523125, -0xc48ffd22, 0x7ade387b, 0x5b59c395, 0x3195e214, -0x987839ae, 0xef23b028, 0xe9574b34, 0x084f9aed, -0xb8d14461, 0x92ee473a, 0x5b5fc73d, 0x00460894, -0x0b5967ed, 0x987685ef, 0x50a2550b, 0xd87522c8, -0xbe2ff4a9, 0xe299bc1b, 0x452096bd, 0x5baaecf9, -0xf8f1956e, 0x2d02606f, 0x87fd45e8, 0x5bf097b3, -0x07236f9d, 0xcd6a058d, 0xbf9fa005, 0x8c7cc99a, -0xb89e30ef, 0xad128bcb, 0x4a7e1219, 0xc2481852, -0x19129474, 0x227d9802, 0xdb6047f0, 0x44fb7f7e, -0xa553b7de, 0xd36cf600, 0x50b29f3b, 0xba3798d0, -0xde788331, 0x344dac23, 0x63716887, 0x835d6c94, -0xc1c178e4, 0x68fae96d, 0x5a50782e, 0xb6054e32, -0x3a501249, 0xe2fe62da, 0x778a6b05, 0x7de9f5fa, -0xc0a1a476, 0xf765e134, 0xf9906b29, 0x4c847ede, -0xd721564e, 0x37c16584, 0xfcfa7c80, 0x8b7c405d, -0xe0929d68, 0xc21e8810, 0x96e75c1a, 0xd07a402f, -0x1c42a7c1, 0x97f0146b, 0x8fc5d3f3, 0x3dace643, -0xeba6869d, 0xf67391bd, 0x5f5cb5b5, 0x74fb3b28, -0x7a9e587b, 0x33ca7543, 0x2e0775aa, 0x9e1097be, -0xb019ad1c, 0x79642e86, 0x6ab5e4ba, 0x470d2670, -0x6fd90246, 0x65c3c566, 0x39a298f5, 0x7b779f08, -0x1f4a965f, 0xead217d9, 0x7e538c63, 0xdf71122c, -0x2d8e5893, 0x650a8b5b, 0x07848c67, 0x5a5a9714, -0x8d4884c2, 0xae30cbeb, 0x2a75f5b2, 0x5ad9ef89, -0xe6f968d6, 0x4976db33, 0x2aae8868, 0x54a0f425, -0x938be96c, 0xe4779ace, 0x15f6d58d, 0xd9773d3a, -0x7986c83d, 0x58a8f3b2, 0x3d927e9c, 0xb981d8d6, -0xfc5b69b4, 0x816c556d, 0xb79d4dac, 0x56c72592, -0x30793478, 0x52792616, 0xdd3368bf, 0x8615f67c, -0x9e9ad64e, 0x21986208, 0x52cbf75b, 0x99158bf6, -0x90a4bb94, 0xd101ccdd, 0x7f9893bf, 0x95d654ad, -0x75747d0c, 0x2a0aed08, 0xd51abee7, 0x0b1a1664, -0x44dba341, 0x76435331, 0x1ed332d7, 0x86af2c20, -0x5a14dcf0, 0x720af164, 0xdb03b43d, 0xf0434592, -0xcd374221, 0xbe6cb668, 0xc7fe200d, 0x9024aa11, -0x98973a68, 0x45854fe5, 0x42fbfba1, 0x7ecda23c, -0xd3810753, 0x94a2dfd9, 0xa6d9c615, 0xb01f739c, -0x072672eb, 0x5f71c0d3, 0xbcb5e5b5, 0x4bd6829f, -0x9357c942, 0x7d2dc61c, 0xdc737d79, 0x0e8069b9, -0xa6a8948b, 0x824cb986, 0x8712ca46, 0x88a6e076, -0xf6e4bdd4, 0x125194ba, 0xa6c566b0, 0x21b6ae11, -0xb0e55a44, 0x1c71d4d9, 0xdcb7b53f, 0x8d9aa903, -0x3b2f3e5e, 0xba0a80d2, 0xd81b15c3, 0xf8b69b19, -0xfc4f4ee6, 0x371aff7c, 0xf977d01d, 0x6753eb49, -0xf8c6aba3, 0x52a32da8, 0xf8bc09a9, 0xafaae176, -0xbd1a2509, 0x9c4ba2f7, 0xf2c5117b, 0x408fd867, -0xb417fd42, 0xf7c63c92, 0xd7817632, 0x45820959, -0xe3180104, 0x95f3cf3e, 0xa758b59c, 0x887a8fe2, -0x3dd7a338, 0x5a73b3ca, 0xad7db285, 0x1ccbb377, -0xf7dec7f9, 0x9bbf2b6b, 0xe05ab128, 0x3d92924b, -0x61c63664, 0xd544d18f, 0xba6ddcb4, 0xec691bc4, -0xd5ffea1d, 0x4a06c0a8, 0x6fbc8ca8, 0x75676b0d, -0x0f557867, 0x9fa53efd, 0xc7e736fe, 0x0580f0c1, -0xbceac219, 0x8f8e0bbf, 0x0cc23b6f, 0xb81dc329, -0x7e0b8083, 0x3a80b402, 0x4dd57a81, 0x1026ba1b, -0x63f8d61a, 0x33aa33a8, 0xfbb2388a, 0x2db9444f, -0x1b2337bf, 0x68a9e70b, 0xb0278540, 0x04ca1d3f, -0xdda4cbba, 0x07285957, 0x2bb2ad49, 0xbc3c632e, -0xdb30073a, 0x3485ea61, 0x728c610a, 0x26d911fc, -0xd9079ed1, 0xdb5ed68e, 0xe8015226, 0xc674c819, -0x8245885c, 0x1e78f037, 0xec3f2319, 0x2218c785, -0x5233ddb2, 0x22ad3fe8, 0x627f3680, 0x34be829c, -0x68db8e7e, 0x648fa39b, 0x50be8c93, 0x76e8032a, -0x9d6bc072, 0xe4cb2873, 0xdd4659e3, 0x4ca89b06, -0x68cee095, 0x331b6344, 0x8b42e6bd, 0x189f545f, -0x810656bb, 0xdef5199b, 0xe95eb90a, 0xaa8fa334, -0x9f74279b, 0x7a0cfa6f, 0xaebc1cb6, 0x453573ed, -0x39873714, 0x84ea8dd6, 0xeaa7d8ac, 0x753f045e, -0xed5a38fc, 0xd15b3135, 0x9bcb2a47, 0x3bec4c99, -0xffdce6e3, 0xc172bfc1, 0x5086aee0, 0xf3df0a2e, -0x90efa3b3, 0x29d3bcfd, 0x2feea67c, 0xad1ad1fb, -0xb8a68400, 0xbd7e92e6, 0x0181a4ed, 0x72a0d21c, -0x6ec9cd1e, 0x4470dbcc, 0xcb62bb94, 0x2e9f2616, -0x71f85a2c, 0x4e645795, 0x4c0b3aaa, 0xefc2fd2e, -0x12126c51, 0x5fe0b2bd, 0xa2ea0296, 0x241aab09, -0x3ff9e277, 0xfec1e535, 0xa1862c20, 0x1d388628, -0x15bac0e6, 0x5107fc7f, 0x017c73c4, 0xb45e3354, -0x1e20663b, 0xc155ab92, 0x702600e0, 0xd42bc23e, -0x235caab1, 0xca8e02b0, 0xdfc5efba, 0xb99d7766, -0x709eee81, 0xc0f9742d, 0x3cfbf530, 0xafc0cb77, -0xa1d97cce, 0x1c7e8e9f, 0x99405b33, 0xe17f2274, -0x3270f9b9, 0x2f702761, 0x50c87113, 0xe9fbc2c5, -0x598d7a49, 0x1ebf50e8, 0x69e46dba, 0x45a0e13a, -0x531dea3a, 0x4f167a0f, 0x50301d05, 0x011ec979, -0x046416ac, 0xf8f24e19, 0x52abb228, 0x586163f8, -0x83a4f211, 0xdf42625b, 0x59549ea4, 0x2f1e65e6, -0x9fe42b62, 0xc0d869d1, 0x6615ef68, 0xa2687bce, -0x49a46a7c, 0xe9dd362b, 0x0bb5d2e4, 0x0b19630e, -0xe121854d, 0x0aa9ab28, 0x715231f7, 0xda126b34, -0x4935896d, 0x92d0d59b, 0x2865b221, 0x2d7659a5, -0xcfdaaa5f, 0x4b3df303, 0xdb6ee69a, 0xfd8acc6d, -0xe9f0f278, 0xbe73c6ea, 0x79a6cc3a, 0xd0ec7aa4, -0x6f4f3211, 0xe5ceb325, 0xedcb8bec, 0x3c06567b, -0xfc4020db, 0xe4514d36, 0xa6efdf9a, 0xd1027491, -0x22ac2657, 0x9573ce20, 0xb975b125, 0xc2a43590, -0xf2bd1d69, 0xa65d09fb, 0x791ad65c, 0xb22629c4, -0x00d8f643, 0x10c31e80, 0x59366171, 0x1c5eae00, -0x66fc579e, 0xa9cd3b65, 0x52b251a6, 0x80601bcf, -0x96310f9a, 0x9750dd48, 0x8b893602, 0x38a25b68, -0xdc6a3b4d, 0x627b969c, 0x31a0702b, 0x73c624ca, -0x7fc4eef2, 0x80c81884, 0x117f023f, 0x3e981c1e, -0x873d99ca, 0x9bfc9459, 0x0be5af0b, 0x3c257880, -0xb8cf77b8, 0x11949c50, 0x47114468, 0x80f91bbe, -0x442cd2ab, 0xee976c2e, 0xcefe1a32, 0xef5ebaeb, -0xd573c27e, 0x2978d764, 0x653eddfc, 0x85a6910a, -0x644a1dce, 0xd194a1eb, 0x3103ca3a, 0xddf7c31e, -0x502d1c7b, 0x9ea11aca, 0x8415e1be, 0xc8b5e6b7, -0x737ec3d1, 0x0025a1e8, 0x2d10e23e, 0xe1cf25c9, -0xd93f9834, 0x5f176c76, 0xed90f0eb, 0x5bfd86a7, -0x0572ccd4, 0xd70c8a08, 0x850da421, 0x0daab877, -0x619e62e6, 0x18c6cda2, 0xc6893dfd, 0xa89177db, -0x7f1797fa, 0x949da24a, 0x3243a802, 0xc98709ed, -0x99134653, 0x671a8b96, 0x5fed050f, 0x78425038, -0xf4d43815, 0x114618a8, 0x75a50583, 0xb8ef5853, -0xbcdff144, 0x10b07fca, 0x99ed97bd, 0xe815d87b, -0x948c0a51, 0x8573a114, 0xf28e0f59, 0xc12cb20e, -0x8aa754d1, 0x199dc118, 0x5fdf32ba, 0x57146859, -0xa4941b44, 0xdcc65dad, 0x6bec0038, 0xeadee691, -0x635fc01b, 0x70e7ea43, 0x6f3e679d, 0xb04deb01, -0x96aba9ef, 0x0409473f, 0x6c69818a, 0xd41e74bf, -0x822f563b, 0x6b224567, 0xc9583923, 0x64460243, -0x6fab20e5, 0x20b85a7d, 0x7ff6c610, 0x84ce4172, -0xc2242380, 0xd512c67d, 0x2f1c7df7, 0x55289339, -0x8cfe618e, 0x14ebf8cb, 0x7b562bbc, 0x37b512cd, -0x5c07cce5, 0xb8020aee, 0x9a91c3a0, 0x3be3adf3, -0x50ffc652, 0x76d2ae8c, 0xafc3153d, 0x6ec9e9ca, -0xfc7908f7, 0xdb95584b, 0xe9195fa7, 0xa68ccbfa, -0xfb5c972f, 0x9f8c7d1c, 0x0bf06c92, 0xe1581091, -0x1fe6f263, 0xff2ef660, 0xd3207637, 0x63c75e6c, -0x6e058902, 0xd2b7fc96, 0xe624c80f, 0xd9567175, -0x07a2f14d, 0xea931882, 0xd82b83e6, 0xef0333d2, -0xc9aefaa5, 0x9cc369a9, 0x2f8d3dde, 0xd357d196, -0xbf34448b, 0x568a4927, 0xa011c011, 0x842b8e78, -0x5f713235, 0xfc9635da, 0xe32b8035, 0x993efdc7, -0x662b2e4c, 0x203c2fda, 0x1a637a9d, 0x4ffb9037, -0x8750b84a, 0xc0678521, 0xa409c34e, 0x87beeb49, -0x2b9c74ed, 0xaaaab901, 0xfc00020d, 0x31450438, -0x0115b209, 0x9c6000e3, 0x34fbc4e7, 0xe4904905, -0xb18ba3fd, 0xf59461e7, 0x0cfe1630, 0xc9fdf2a3, -0xe778d88d, 0xac018200, 0xb71fea46, 0xe303e55f, -0xce7e8ed7, 0xb84a943e, 0x6e2cdd1d, 0x6cdba37d, -0x488d4d64, 0xc7956242, 0x1a8056a8, 0xef28092f, -0x205bcdd9, 0xdb000225, 0x60592274, 0xe2b5e6a3, -0x61f0299e, 0x826c08b4, 0x5840da4b, 0x7b38f75a, -0x02435a81, 0x0411fc4e, 0x27d53980, 0xb68be32f, -0x66c7132b, 0xe5095758, 0xb5369c1d, 0xcd36f9e0, -0x4b3cd470, 0x815c94b9, 0x188df989, 0x2ce8d855, -0xaa643e10, 0x79800fbc, 0x3e5b5471, 0x0d894001, -0xbdbb3801, 0x9ff9f719, 0x1cd71921, 0x17ef534b, -0x0c779b3d, 0xcfe872ac, 0x4f810fdd, 0x83017c60, -0xbfec9761, 0xebace400, 0xe2dfb6ee, 0x18d62ca4, -0xae3b101d, 0xacd56190, 0x6fb19c2f, 0xc01a2110, -0x677fefcb, 0x792a248a, 0x83c8d7ff, 0xfd1365ef, -0x64e955b3, 0x61a37834, 0xc4141d09, 0xd85ace5d, -0x67b146dd, 0xdfcb7a9b, 0xcd76894a, 0x0465e1a0, -0x2abd5dd7, 0x832d6077, 0xcff6633e, 0xcf03bd51, -0x524b04d8, 0x98bf7f34, 0xcf495873, 0xeaa6d8b8, -0xaa928eda, 0xd1d364c7, 0x3c93d762, 0x7a64ffc6, -0x0a8037f6, 0x92000ece, 0xf4e3195d, 0x01c4ee4b, -0x9612d484, 0x941bc1eb, 0xac0a1f83, 0x4c8be21d, -0x7800d3b8, 0x61c76ba7, 0x1c2145e0, 0x91a403b5, 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-0x3c2f4b20, 0x92e67606, 0xe1bac93a, 0xa805c705, -0x4aed9ea0, 0xd1f0c546, 0x807248fd, 0x43b26233, -0x3486434b, 0x4e2d025a, 0x755f498f, 0xb58c5be4, -0xebb5fcfe, 0xb6bc61f2, 0xa7693118, 0xd9df5f82, -0x23c0c360, 0x436d2b4e, 0x717ca75e, 0x6f0fea5e, -0xfe11bed5, 0x1031f3bb, 0x3a8c3570, 0x3c784752, -0x90a3f899, 0x38929e1c, 0x00c554a7, 0xfe083bb7, -0x489b1d2b, 0x81b619ed, 0xe8a7207a, 0xebfcc03f, -0x58265a1c, 0xdb698877, 0xc8da280f, 0xdb60cfd3, -0x0f8ac573, 0x41935f4a, 0x03f574c1, 0xe7084e1a, -0x4f481b4f, 0xccecdfe4, 0x17974d9a, 0x50ef62bc, -0xb28317d6, 0x1118de1e, 0x9f95e190, 0x116d18f5, -0x4d83f4f2, 0xfd2069d3, 0xff4df0c6, 0x1fb97350, -0x738c1695, 0x81218575, 0x049869e2, 0xafd6d853, -0x2eef0331, 0xabe2333d, 0x5f5da74e, 0x2aad7e80, -0x30ef17d8, 0xda18d115, 0x14cf5948, 0x83a8fd0f, -0xe0418383, 0x1051450a, 0xeda7fd61, 0xc1e5636f, -0xba6853ca, 0xd442829f, 0xba5046b0, 0x49ed0cdc, -0x47b45c36, 0x947b6622, 0xb937b3ab, 0xcc56bf60, -0x114b3314, 0x689ee17b, 0xd06cf12e, 0x27d6ede6, -0x6f558857, 0xe04c4418, 0x7b8d2ee6, 0xac511481, -0xa7ffeb98, 0xfcdc240b, 0x2df5364c, 0x76c0a100, -0xadb9fe5d, 0x1c947fba, 0xde6aa412, 0x4a27d690, -0x1b0b912f, 0xfb9e0ef1, 0xccb65c2b, 0xfc951766, -0x6e2517a2, 0x6915a740, 0x5d25a614, 0x6cd7b974, -0xa7ce4d32, 0x3224f657, 0x4282b7a1, 0xec366255, -0x0e47b33e, 0xdcfcc85d, 0xa1664173, 0xf59ba283, -0xee9e56ff, 0x19394206, 0x10c79974, 0xae5dc824, -0x6c0ee811, 0x71e73438, 0x3dbd7096, 0x3067b002, -0xd4dbf4a1, 0xeeadf929, 0xf9fbf969, 0x313828ac, -0xf3098c09, 0x9f4471b4, 0x603db9bc, 0x183e48cb, -0x4fde31ea, 0x1d742894, 0x15925c74, 0x05c76d00, -0x0c4014bc, 0x8740492f, 0x55d13385, 0x26da473b, -0x46073574, 0xe838bddf, 0x05eebc9f, 0x102db9d7, -0x29e40133, 0x25358cec, 0xfc5a1101, 0x3d47e19e, -0xd5d41f36, 0xf0ed93fb, 0xfed93b52, 0xa8eb8c88, -0x8c46e49a, 0x53e1c785, 0x6b16ceb0, 0x7b371456, -0xa002bb76, 0x124fb3fa, 0xcce07630, 0xf7a2b85b, -0xbfc9d8f6, 0xcabd8927, 0xa17a6f95, 0x376f6b76, -0x736e63e6, 0x1817b743, 0xb1065d6a, 0x465c9f0b, -0xa0f2834b, 0xf2a4e312, 0x440c9337, 0xf90a881c, -0x5394b548, 0x39d7270b, 0x34df5a19, 0xef293328, -0x9208a78d, 0xb10047a0, 0x4cdb36e0, 0x956341d2, -0x1172f6a7, 0x0d4dbcd9, 0x150257e5, 0x6fcd2819, -0x58d0fbb0, 0xd0c02e0a, 0xdaa14a11, 0x9916a9cb, -0x1b57cc6a, 0xfcb7d15f, 0x1f53a411, 0x5879f5b8, -0x16b0a08b, 0x682bc794, 0xc7a3b009, 0xe03786c4, -0x0b5a7c63, 0xc8dc0446, 0x193e9316, 0x47d5c30d, -0xa60a3c80, 0xf4a12762, 0xf8793c61, 0x2409a00b, -0x6c6d50f1, 0x7ea3a994, 0x30451730, 0x826e1d45, -0x3976f84e, 0xd23342a7, 0xd4f833df, 0x15fb07a5, -0x44a51f2f, 0xa791f9c7, 0x2ab655ac, 0x330f04ed, -0x7993420d, 0x6c30b008, 0x5605f4a6, 0x0b8f8ab9, -0x6cf1deee, 0x6b60da51, 0xbc1422b1, 0x74e8f1f0, -0x0c2c01f4, 0x88eee820, 0x9f6f60ca, 0xbd4e5376, -0xa2e01d54, 0xbbac9a7e, 0x95ffc15c, 0xf17cbfe7, -0x2f7be37e, 0x65db6739, 0xe75ad573, 0xa9b14b3a, -0x3999e77d, 0x402c7ee2, 0xef122e31, 0x2b82eacc, -0x29085b92, 0xe4ffbf36, 0xf8ed47db, 0xead6e5cf, -0x5de54805, 0x7a1d9515, 0xcb865781, 0x4e60f4ed, -0x98d61f94, 0x3cef4824, 0x6ce64200, 0x7a8e1493, -0xefab6481, 0xf9e0de21, 0x00d68953, 0x8328e844, -0xc5ffa497, 0xcdd2f8e5, 0xe70ed12d, 0x8c8d24f0, -0x95abdfaf, 0xed54a7a8, 0x443150f3, 0xbfd46120, -0xbf5a7bf6, 0x99a5b47f, 0x0c9d7760, 0xd70a3ea5, -0xe4183d93, 0x5af80980, 0xba263b1d, 0xeedf5a94, -0x8f935597, 0x7e84bb8d, 0x24a54001, 0x230a3c64, -0x5ee409a0, 0xbc4a02e8, 0x73487e4b, 0xb8a14b12, -0x4d2c9105, 0x1fdcdc1c, 0x10eb2962, 0xb0217fba, -0xbe8793f2, 0x3c44cfcf, 0x67a95305, 0xdef9c77f, -0xd60b9d0d, 0xa8a1fbc7, 0xc3b7fef7, 0x1a76c5ac, -0xf55092a9, 0xe3a3752a, 0x08a88130, 0x9909eb5a, -0x0e4c37c4, 0x13b66089, 0x7a49ac95, 0xe60b4832, -0xc300cf0c, 0xe1582543, 0x3b3d2c8a, 0xfe882522, -0xa24b794c, 0x81a3b399, 0x48f3fb1e, 0xd2b325a8, -0xf8015b2c, 0x0c35913d, 0x639e9bbf, 0x80c8ec76, -0x81c0705b, 0xa4fe643b, 0xa06100d6, 0x9f8d4894, -0x5d17d490, 0xd7a9007c, 0x5adcc8b3, 0xd7c1c03e, -0xaefa34f6, 0xbf959047, 0xdaafcc99, 0xdd14e71c, -0xd7ac0efc, 0x3c9c4c89, 0x48bbd2ed, 0x907b4da3, -0x817d5b8b, 0x822c5db5, 0x7f3293bc, 0xb712ffb3, -0x7c154824, 0xc354ea89, 0xd6b1252b, 0x39bf78c0, -0x2127a973, 0x9bd70e29, 0x51fd538a, 0x535fac18, -0xf2c5e53f, 0x1b736b26, 0x71255f0f, 0x6c254021, -0x3eb72bda, 0x05da558d, 0x84131772, 0xa276638f, -0xd577fb79, 0xef0d1a08, 0x8bdc53fd, 0x2a71b3fd, -0x4ed41204, 0x592abca3, 0x995154c7, 0xbede8562, -0xe9492455, 0xddc9a5ce, 0x1e9db016, 0x57477a40, -0xcc86ebfa, 0xba7c18a3, 0xd9060d3a, 0x3866c4a7, -0x5ad05ee6, 0xcd1df98e, 0xcf031455, 0x3d31984a, -0x481e2ea1, 0x29e760dc, 0x5e49a8e0, 0xe8354e48, -0x611ffef7, 0xfa9bb0d3, 0x7c8bbad7, 0x65fb7b7b, -0x47971e27, 0x431f6b52, 0x1cf9b8f0, 0x2ab3c24e, -0xecbaeb0e, 0x7d57cf23, 0x23d1f43f, 0x3e607986, -0x3d697fe1, 0xbb3c596e, 0x707a141c, 0x9c3c5974, -0x4789aa5c, 0x2354a40b, 0x4e050f47, 0x430f417f, -0x1ad0b489, 0x291fbd9f, 0x0919fd8c, 0xb5b1cffa, -0xcab90385, 0xd81804ac, 0x818b7b6b, 0xb3fff6b4, -0x42881bda, 0xe562c316, 0x4d374783, 0xe5d9eebd, -0x0f8d2d59, 0x014043c9, 0x68dd37c2, 0x0b1cee46, -0xe0fde299, 0x0ee2e06d, 0x8314a2a2, 0x0492cb97, -0x402bd26a, 0x7e3b9161, 0xa492def0, 0xb3474888, -0xeeeb9bfe, 0x00dbde69, 0x585d8ad8, 0x3cdc19f9, -0x6d5b6885, 0x3809aac8, 0x7da7e149, 0xbca5df24, -0x6379477f, 0xc7953baf, 0x9c6782e7, 0xcab924d8, -0x0e319d11, 0x6e190440, 0xecf1be0c, 0x8b4940fc, -0x5ac3a404, 0x60aa3685, 0x421d8f9f, 0x29d74acf, -0x0ebbd757, 0x2d32d521, 0xacc74cc8, 0xbd2cb4db, -0x35d8f179, 0xd3e00599, 0xfea923b0, 0x921c158e, -0x129411a1, 0x9d7caf7b, 0x49e567e6, 0xc4807bdf, -0xf93181c9, 0x718e08c3, 0x19c6ed21, 0xdef94589, -0xd0768a4c, 0x148e8c3e, 0x68788954, 0xf34fccad, diff --git a/src/cpu/intel/haswell/microcode-M7240651_00000008.h b/src/cpu/intel/haswell/microcode-M7240651_00000008.h new file mode 100644 index 0000000..c0f9f9a --- /dev/null +++ b/src/cpu/intel/haswell/microcode-M7240651_00000008.h @@ -0,0 +1,960 @@ + 0x00000001, 0x00000008, 0x03122013, 0x00040651, + 0xc409cf52, 0x00000001, 0x00000072, 0x00003bd0, + 0x00003c00, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000000a1, 0x00020001, 0x00000008, + 0x00000001, 0x00000e51, 0x20130312, 0x00000e51, + 0x00000001, 0x00040651, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0bd8beab, 0x3f030ef5, 0xb4ff0dd1, 0x6182d4bc, + 0x2b5062c2, 0xc096a703, 0xdddca87d, 0x3c268f5f, + 0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6, + 0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58, + 0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068, + 0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142, + 0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1, + 0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f, + 0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c, + 0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606, + 0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531, + 0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786, + 0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01, + 0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4, + 0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66, + 0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184, + 0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84, + 0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c, + 0x00000011, 0xfc67ee70, 0x9aaccac1, 0xe0f5734a, + 0x5e558594, 0xa1f9d3e1, 0x6d0d9896, 0x2ff6d82a, + 0x8b22b734, 0xe20988ac, 0x7c0dd541, 0x9fc09b9c, + 0xd1c062c8, 0x36ed7d24, 0x4fd76aff, 0x40990d7b, + 0x550ab834, 0x58d8ffd6, 0x43eccc92, 0xb93166cf, + 0x056a0bd1, 0xe0f41c64, 0x5b9306c7, 0x07cabbee, + 0xde9fd60c, 0xad44b0e6, 0xffbe8052, 0x79195750, + 0x8b50e2b8, 0x5143823b, 0x33815ed7, 0xcde461bd, + 0x4d6bf517, 0xe88e3968, 0x27c45907, 0x6bd090a7, + 0x964dee08, 0xf20c34bc, 0xf3d2a3f5, 0xacc4700a, + 0x4618df29, 0xbc6e231d, 0x3e327e64, 0xf00ffce9, + 0x9de935b8, 0x50ae404b, 0x36a5da25, 0xff41f9cd, + 0xe2f19869, 0x98266f8a, 0xccc7b9d9, 0x0d99c041, + 0x6e16c353, 0x9e978059, 0x5410d919, 0x53e9275a, + 0x56c2412f, 0x6619570c, 0x4cd96519, 0x873d2b6e, + 0xc7c9fe21, 0x8bcf375b, 0x8888ebce, 0x57cd8707, + 0xcd7f60b2, 0xad7585ce, 0x732bb99e, 0x1b80aaad, + 0xd90a5ef4, 0x6b680807, 0x7db4f941, 0x3f743d53, + 0x45f39845, 0xefab0dd5, 0xc8a185d8, 0x55d73f1c, + 0x7a1d9e6f, 0x9fcc99bb, 0xf5e9e062, 0xdad7bd70, + 0x6948012a, 0x8f431b52, 0x4e08ea54, 0x37b761d0, + 0x8bb2d6e8, 0x8f50c098, 0x6a2589ba, 0xbe59d5ce, + 0x1962ffcd, 0x5e0afc4d, 0x24bb6d1b, 0xe273614f, + 0x466268e9, 0xa7772a0a, 0x80cd4b8d, 0x865c2672, + 0xcf542840, 0x2a668728, 0x47a4f1f8, 0xe8139fbd, + 0x853223ab, 0xd3af9f27, 0x6958f017, 0x74f6dee6, + 0x61dfa37e, 0x5da7d740, 0xf0d5742c, 0xe04b7884, + 0x8a7732a1, 0x2f02d5f7, 0x0d6e42b3, 0xb5f40e73, + 0xba2fc9af, 0x8abba8d1, 0x08e76173, 0xcaa85fc1, + 0x491b2f62, 0x2b3cd789, 0xff78fdf4, 0x814d87b9, + 0x95ce85b5, 0xb6392eed, 0x5ca167ad, 0xbbfe8d40, + 0xebbb609f, 0x07aac95a, 0xb7d2fbe0, 0x2614a3aa, + 0x6e22cb84, 0x2da8c951, 0x2467e3cb, 0x518ff989, + 0x56b550f8, 0x54387bee, 0x96e6af22, 0x617631ee, + 0x236b69ad, 0xd0f3eeb2, 0x936b6bb9, 0x477842d5, + 0x68412d3a, 0x96b147ad, 0x64b1bb76, 0xc321f1fd, + 0xeb6399c5, 0xc5e4ed53, 0xac36bfb4, 0xbd1eb18a, + 0x47ecd205, 0xd967b736, 0x522d00c5, 0x82fc8d01, + 0xacfd7978, 0xee0c0687, 0xdd9a6316, 0x561a59cf, + 0x0555d295, 0x7d08fefd, 0xff14c77f, 0xd8ed9d12, + 0xce520e06, 0x21a0c65d, 0x06b96d17, 0x46a75767, + 0xcf02c36e, 0x0ca6817a, 0x69a9f228, 0x604b2924, + 0x05b67b42, 0xb2fdbcc6, 0xbc827c40, 0x7755d5a5, + 0x446c729a, 0x2610a3bb, 0x5d499746, 0xcfd4c17f, + 0x41b48da2, 0x6352ae4c, 0x9fcd775c, 0xdfdcb4a7, + 0x49ed5ab9, 0x533bd7f3, 0x14584e56, 0xe762fb03, + 0xf3471e51, 0x4a2c30e8, 0xb1ae32a7, 0x0d1582c6, + 0xc55be929, 0xd26d0dd3, 0x72e7186b, 0xa7c43d17, + 0x6146b925, 0xb40c0951, 0x2b3f9a4a, 0xcb534ef7, + 0x9af09d74, 0x36e85a3c, 0x4a79d2ce, 0x6408aff5, + 0x89096c3d, 0x7bdb2ef2, 0xedb89859, 0xb21166c4, + 0xb8d309f2, 0xf37394a7, 0x0b591361, 0x337c0216, + 0xabeb2d2c, 0xfbdbcddc, 0x5551e35a, 0xd92c0f5b, + 0x5f6015c7, 0xa3ddd061, 0x6d57a159, 0x7ee13e22, + 0x5e512d08, 0x39e853bd, 0xc6297481, 0xb31f5924, + 0x5f08d2ca, 0x7cccdc33, 0x955a8527, 0x9be884f2, + 0x9f7874bb, 0x9f21fcab, 0x9308d3a5, 0xe5625c45, + 0xf8b3504e, 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0x8256cace, 0xfbbdac63, 0xc734da9a, + 0xb4a8f526, 0xe6d227a5, 0x3d011488, 0xff3eff57, + 0x3a324faf, 0xaf1033a3, 0xb3077715, 0x23c9c3be, + 0xf812d302, 0x4d8fe88a, 0x9dc1c6e1, 0xee236e74, + 0x8f822c36, 0x0b3ed6ab, 0xd555fd1d, 0x1daca989, + 0xae9f7a72, 0x46616396, 0x9a470312, 0x28133286, + 0x7b10aebc, 0xf4b30629, 0x3fa8ba40, 0x8efaed45, + 0xa8e05090, 0x51c5b788, 0x1682b9e4, 0x4f67e82c, + 0xcd4a14e7, 0x7df5b3f2, 0x2f7c9034, 0x0bd4550b, + 0xd33e00f0, 0xbe966778, 0x1e14d40e, 0x1993d501, + 0x9c486e64, 0x51eb5292, 0x5dadba70, 0x23eafc6c, + 0x1db15388, 0x865d280d, 0xc4d3e285, 0x8e042d8b, + 0xf8a9d18b, 0xd3df1ef8, 0xf5b6207b, 0x7583686b, + 0x7706afe1, 0x57e08980, 0x84cea65b, 0xf8021c5e, + 0xa5463cc4, 0x99a82624, 0xd4e4a886, 0x0ff8f7b9, + 0xcaa2c4b6, 0x482f8db7, 0x784c10c9, 0x0aa0b1b8, + 0x2cc2fde9, 0x3596ab68, 0x42e3d3f0, 0xf38ed328, + 0xcad1ced6, 0x0979ccf3, 0x2a7a9932, 0xfeb85ddc, + 0xc40fa608, 0x7de7a0d2, 0xf707b20d, 0x1a5853da, + 0x0e98e186, 0xcde0f0ac, 0x2ed2463a, 0xba5f396b, + 0x85ed3026, 0x3fd4bd4e, 0xb447d740, 0x0ef67e87, + 0x348c805f, 0x4e35680d, 0xf6dd8e5f, 0xcfc6077c, + 0x1975376a, 0x31207b9b, 0xc7fc6af5, 0x1bd43b17, + 0x6fdc5df4, 0x2c7aa5ab, 0x0fe3f572, 0x9c282c14, + 0x90b27771, 0x4eb288a8, 0x9cdc811c, 0x2924c9a7, + 0x68fc87a4, 0x4d12e2d5, 0xc6475d18, 0x8f9af2aa, + 0x6710c320, 0xdaad306c, 0x269e1ac5, 0x29d2f13a, + 0xa9a56ec8, 0xeca7bff1, 0xbaac79b0, 0x3d1854e1, + 0x06b9f48f, 0xb869988e, 0x97f8d733, 0x4825bbdc, + 0x0bccbc13, 0x760780f4, 0xf7ea2993, 0x6d3ff21b, + 0xae284966, 0xf5d73041, 0x7fbf9c98, 0xc6d579e9, + 0x56506d1e, 0x31024272, 0x2afc2877, 0x0c94dd6c, + 0xcecd0627, 0x8e30b86c, 0x054f67a1, 0x2ab5c5d5, + 0x76ba8a8e, 0x65ea0ef9, 0xa49df573, 0x290a5140, + 0x7bdcfcf3, 0x3c77d4d5, 0xd59eec20, 0xff9f96c9, + 0x15d037cc, 0x66395cd1, 0x0f8a8ab6, 0xbe4314a9, + 0x8c30342b, 0x3971b525, 0xea06ea91, 0x84544253, + 0x1eff733b, 0xaa099188, 0x2055367f, 0xe8363308, + 0x9e4eb127, 0x3ab2fc22, 0x56c22ad7, 0xc1720bfb, + 0x9eb6319f, 0x457ff207, 0x4546a236, 0x6582e4bf, + 0x367bb40e, 0xe60f5d4b, 0xba647634, 0x659a9a05, + 0xf73be89f, 0x3de36a5a, 0x93c7cafd, 0xb571aa54, + 0x44c5e0a9, 0x28e6301a, 0x7434b771, 0x76b4d951, + 0x7f2b8671, 0x7d595e69, 0xa584f1e4, 0xbde89668, + 0x519a0252, 0x5f9fab17, 0xe4d167b3, 0xa6f02be9, + 0x7a7ed5be, 0x07a6015b, 0xce016c33, 0xf8748be8, + 0x8cfc5eaf, 0x92dd0c5f, 0x3b4b79bb, 0x66df2875, + 0x7ed36870, 0x2304917f, 0x347755d5, 0x40b1a500, + 0x512468d5, 0x9739332d, 0xf8ecc7c2, 0xef5f56ef, + 0xc5b30b5e, 0xa20da1bb, 0x46cef6ec, 0x40fc7bcf, + 0xdda2b5c1, 0xdc98f36a, 0x40baf4f8, 0xe05dc398, + 0xd1c4c3e2, 0xbbbad97f, 0x3ae4ed7f, 0xba814de6, + 0x4feb5341, 0xfa15ac44, 0x47adf3ae, 0x51668138, + 0x0bf4984e, 0x1e6fd436, 0x92f06c54, 0x25973381, + 0x1e5ae23e, 0x4377eac0, 0x7a94a11d, 0x7116739e, + 0x3d97a447, 0x2b290945, 0xda2c1ff2, 0x6777e38d, + 0x9aaa1566, 0xf548215c, 0x2eb427d8, 0x104ffb64, + 0x0c763a06, 0x85b2e583, 0x0ea98ab6, 0x9a3fbd6f, + 0x40e07540, 0xc474bda8, 0xf21719d9, 0xb64d5bf7, + 0xddd61179, 0x66f17f41, 0x6d57e923, 0x244f118d, + 0xd7ab8a9f, 0xde8024ee, 0xd091733c, 0x1a8cf4e5, + 0xc571c64b, 0x5e4b8dc9, 0x9548ef3e, 0x9bf5e19c, + 0xa738d07d, 0xa75b60da, 0x2279f696, 0x217ca76c, + 0x656325ce, 0x6f1a8d6c, 0x371cf027, 0x347591b4, + 0x4b760e36, 0xc1b88521, 0xba1093f3, 0xb9130151, + 0xe40b0dcd, 0xb736390d, 0xc5af40bd, 0xb15a4328, + 0xe6d6fb2a, 0x2f071735, 0x84abcb79, 0x322905f5, + 0x5ce2dd3c, 0x0b91c236, 0xdcece67a, 0x1d25d21d, + 0xba764cc3, 0x93f700f7, 0xf47f3cb0, 0xf3b2aeb4, + 0x7142b7cf, 0x37ee70a8, 0x53e1e368, 0xc049aeea, + 0x68c88fdc, 0xee99d76e, 0xc82dd367, 0xa4c37b86, + 0xde251d78, 0xcea1927b, 0x2efcb03e, 0x157f0c3b, + 0x67a66e90, 0x4b087e83, 0x04fc4347, 0x2a70ace3, + 0x3bd596c3, 0xb56ce5b6, 0xe787b59f, 0xb86f1af9, + 0x66e14369, 0x43b472c1, 0x38cdc303, 0x167cffe8, + 0x4c93771b, 0xdc6ce475, 0xbd4fd57e, 0x8ba74cf1, diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index ef79cac..f74e6b6 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -21,7 +21,7 @@ #include "microcode-M32306c2_ffff0003.h" #include "microcode-M3240660_ffff000b.h" #include "microcode-M7240650_ffff000a.h" -#include "microcode-M7240651_00000006.h" +#include "microcode-M7240651_00000008.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

1 0

New patch to review for coreboot: 355778a ARM: Update the size/location of the coreboot tables so we can boot again
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4128 -gerrit commit 355778a3241990d353e7172365e837140be87411 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 11 22:44:37 2013 -0700 ARM: Update the size/location of the coreboot tables so we can boot again Change-Id: I3235f42c7faaf28a63455162ea55dc1a6bebd1f5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-by: Hung-Te Lin <hungte(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48290 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/coreboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index 9545f29..414b7fa 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -283,7 +283,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0xbff00000), 0x100000, info); + int ret = cb_parse_header(phys_to_virt(0xbc000000), 0x4000000, info); return (ret == 1) ? 0 : -1; }

1 0

New patch to review for coreboot: 8acd856 butterfly: Log EC shutdown reason in ELOG
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4127 -gerrit commit 8acd85623f6467ff582742f035357426ff22192b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 26 14:53:42 2012 -0800 butterfly: Log EC shutdown reason in ELOG The EC saves its last "shutdown reason" for the system in EC RAM that we can read back and log on boot. The decode for the "reason" field will be added to mosys. Change-Id: I834d39122e45262ef8e7ba59201accbee5857aac Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48323 Reviewed-by: David James <davidjames(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/elog.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index e6c84f3..b813a10 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -141,6 +141,9 @@ struct elog_event_data_me_extended { /* Last post code from previous boot */ #define ELOG_TYPE_LAST_POST_CODE 0xa3 +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size);

1 0

New patch to review for coreboot: cc0bb6f Stout: Add EC error reporting
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4126 -gerrit commit cc0bb6f347d25fe1eb54337d5f42e3039163ea16 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Sep 24 22:14:24 2012 -0600 Stout: Add EC error reporting Capture very early EC errors in the ELOG and power off the system. Change-Id: Ida98f81b1ac1f6b3ba16c0b98e5c64756606fd58 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48318 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/elog.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/elog.h b/src/include/elog.h index a65893c..e6c84f3 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -87,6 +87,7 @@ #define EC_EVENT_KEYBOARD_RECOVERY 0x0f #define EC_EVENT_THERMAL_SHUTDOWN 0x10 #define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 /* Power */ #define ELOG_TYPE_POWER_FAIL 0x92

1 0

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coreboot-gerrit November 2013