coreboot-gerrit November 2013

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New patch to review for coreboot: 4177728 smi: Update mainboard_smi_gpi() to have 32bit argument
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4145 -gerrit commit 417772819fbbf4e1adc8f0c082778f564da3f48d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 29 15:04:30 2013 -0700 smi: Update mainboard_smi_gpi() to have 32bit argument With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smm_module_handler.c | 2 +- src/include/cpu/x86/smm.h | 4 ++-- src/mainboard/getac/p470/smihandler.c | 2 +- src/mainboard/google/butterfly/mainboard_smi.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/parrot/smihandler.c | 2 +- src/mainboard/google/stout/mainboard_smi.c | 2 +- src/mainboard/lenovo/t60/smihandler.c | 2 +- src/mainboard/lenovo/x60/smihandler.c | 2 +- src/mainboard/roda/rk9/smihandler.c | 2 +- src/mainboard/samsung/lumpy/smihandler.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 116dafa..444e335 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -165,6 +165,6 @@ int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } void __attribute__((weak)) cpu_smi_handler(void) {} void __attribute__((weak)) northbridge_smi_handler() {} void __attribute__((weak)) southbridge_smi_handler() {} -void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cacbff0..607c0f0 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -387,7 +387,7 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); -void mainboard_smi_gpi(u16 gpi_sts); +void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); #else @@ -395,7 +395,7 @@ void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_are void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); int __attribute__((weak)) mainboard_smi_apmc(u8 data); void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); #endif /* CONFIG_SMM_MODULES */ diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 6122c82..c66abad 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -180,7 +180,7 @@ static void mainboard_smi_hotkey(u8 hotkey) printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey); } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { u8 source, hotkey; send_ec_oem_command(0x5c); diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index e2f00e1..a40e428 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -52,7 +52,7 @@ int mainboard_io_trap_handler(int smif) return 1; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts); } diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index a4c4a50..3785121 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -80,7 +80,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events */ diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a5f6ba2..72a3a1b 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -125,7 +125,7 @@ static u8 mainboard_smi_ec(void) return src; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { u32 pm1_cnt; diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 0f2ecd5..44dc46e 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -72,7 +72,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events */ diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index f4bad8b..093996b 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -152,7 +152,7 @@ static void mainboard_smi_handle_ec_sci(void) } } -void mainboard_smi_gpi(u16 gpi) +void mainboard_smi_gpi(u32 gpi) { if (gpi & (1 << 12)) mainboard_smi_handle_ec_sci(); diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 5a7130f..090f037 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -158,7 +158,7 @@ static void mainboard_smi_handle_ec_sci(void) } } -void mainboard_smi_gpi(u16 gpi) +void mainboard_smi_gpi(u32 gpi) { if (gpi & (1 << 12)) mainboard_smi_handle_ec_sci(); diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index fe68c4b..baa038e 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -50,7 +50,7 @@ int mainboard_io_trap_handler(int smif) return 1; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << 1)) { printk(BIOS_DEBUG, "EC/SMI\n"); diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 9306a02..417ccd8 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -70,7 +70,7 @@ static u8 mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(u16 gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending EC requests */

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New patch to review for coreboot: ccc89fc elog: Make sure the elog data structures are initialized in elog_clear.
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4144 -gerrit commit ccc89fc7ae090f1c044b9dd9a502a11754085d46 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 25 17:21:58 2013 -0700 elog: Make sure the elog data structures are initialized in elog_clear. If elog_clear is called before other elog functions, for instance if it's called through an SMI immediately after the system boots, then the elog data structures won't have been set up and the system will go off the deep end. This change adds a call to elog_init to elog_clear to make sure things things are always initialized before we start using them. Before this change, this command would cause the system to lock up if run immediately after boot: echo 1 > /sys/firmware/gsmi/clear_eventlog After this change, that results in the log being cleared correctly. Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49303 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/drivers/elog/elog.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 6e89b5f..6de5123 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -746,6 +746,10 @@ int elog_clear(void) elog_debug("elog_clear()\n"); + /* Make sure ELOG structures are initialized */ + if (elog_init() < 0) + return -1; + /* Erase flash area */ elog_flash_erase_area();

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New patch to review for coreboot: baad7c1 haswell: Configure PCH power sharing for ULT
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4143 -gerrit commit baad7c15e19618c866eb5b0399b6931d4f11e788 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 26 10:35:19 2013 -0700 haswell: Configure PCH power sharing for ULT This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 2 + src/cpu/intel/haswell/haswell_init.c | 69 +++++++++++++++++++++++++++++- src/southbridge/intel/lynxpoint/finalize.c | 3 ++ src/southbridge/intel/lynxpoint/pch.h | 2 + 4 files changed, 75 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 96f94eb..7dfba86 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -107,6 +107,8 @@ #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb /* Errors are returned back in bits 7:0. */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 0b7a898..071135c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -274,6 +274,71 @@ static void calibrate_24mhz_bclk(void) MCHBAR32(BIOS_MAILBOX_DATA)); } +static u32 pcode_mailbox_read(u32 command) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return 0; + } + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return 0; + } + + /* Read mailbox */ + return MCHBAR32(BIOS_MAILBOX_DATA); +} + +static void configure_pch_power_sharing(void) +{ + u32 pch_power, pch_power_ext, pmsync, pmsync2; + int i; + + /* Read PCH Power levels from PCODE */ + pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); + pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); + + printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", + pch_power, pch_power_ext); + + pmsync = RCBA32(PMSYNC_CONFIG); + pmsync2 = RCBA32(PMSYNC_CONFIG2); + + /* Program PMSYNC_TPR_CONFIG PCH power limit values + * pmsync[0:4] = mailbox[0:5] + * pmsync[8:12] = mailbox[6:11] + * pmsync[16:20] = mailbox[12:17] + */ + for (i = 0; i < 3; i++) { + u32 level = pch_power & 0x3f; + pch_power >>= 6; + pmsync &= ~(0x1f << (i * 8)); + pmsync |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG) = pmsync; + + /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values + * pmsync2[0:4] = mailbox[23:18] + * pmsync2[8:12] = mailbox_ext[6:11] + * pmsync2[16:20] = mailbox_ext[12:17] + * pmsync2[24:28] = mailbox_ext[18:22] + */ + pmsync2 &= ~0x1f; + pmsync2 |= pch_power & 0x1f; + + for (i = 1; i < 4; i++) { + u32 level = pch_power_ext & 0x3f; + pch_power_ext >>= 6; + pmsync2 &= ~(0x1f << (i * 8)); + pmsync2 |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG2) = pmsync2; +} + int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -574,8 +639,10 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); x86_mtrr_check(); - if (is_ult()) + if (is_ult()) { calibrate_24mhz_bclk(); + configure_pch_power_sharing(); + } /* Call through the cpu driver's initialization. */ cpu_initialize(0); diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index d9bc225..d81f90e 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -54,6 +54,9 @@ void intel_pch_finalize_smm(void) /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + /* PMSYNC */ + RCBA32_OR(PMSYNC_CONFIG, (1 << 31)); + /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 4bdb926..58b07d1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -574,6 +574,8 @@ void set_gpio(int gpio_num, int value); #define D19IR 0x3168 /* 16bit */ #define ACPIIRQEN 0x31e0 /* 32bit */ #define OIC 0x31fe /* 16bit */ +#define PMSYNC_CONFIG 0x33c4 /* 32bit */ +#define PMSYNC_CONFIG2 0x33cc /* 32bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8

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New patch to review for coreboot: b6bf75a lynxpoint: Updates to power management and clock gating
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4142 -gerrit commit b6bf75a44ae640635bffc4240f8d10b0ed7240b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 26 10:41:33 2013 -0700 lynxpoint: Updates to power management and clock gating Slight tweaks found when looking at latest ref code when investigating package C-state issues. A few bits in the clock gating register don't match the documentation and are also cleaned up. Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49330 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index be68549..c3b5322 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -304,7 +304,7 @@ static void lpt_pm_init(struct device *dev) const struct rcba_config_instruction lpt_lp_pm_rcba[] = { RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), /* 4 */ - RCBA_RMW_REG_32(0x1100, ~0, 0x0000c000), /* 5 */ + RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), /* 5 */ RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), /* 6 */ RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), /* 7 */ RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), /* 8? */ @@ -343,7 +343,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = { RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4610), /* Power Optimizer */ + RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), /* 21? */ @@ -377,6 +377,10 @@ static void lpt_lp_pm_init(struct device *dev) data |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = data; + /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ + if (RCBA32(FD) & PCH_DISABLE_ADSPD) + RCBA32_OR(0x2b1c, (1 << 29)); + /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); @@ -451,12 +455,15 @@ static void enable_lp_clock_gating(device_t dev) reg32 &= ~(1 << 29); // LPC Dynamic else reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1 << 30); // LP LPC + reg32 |= (1 << 31); // LP LPC + reg32 |= (1 << 30); // LP BLA reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 26); // LP LPC + reg32 |= (1 << 26); // Generic Platform Event Clock + if (RCBA32(BUC) & PCH_DISABLE_GBE) + reg32 |= (1 << 23); // GbE Static reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 16); // PCIe Dynamic + reg32 |= (1 << 16); // PCI Dynamic RCBA32(CG) = reg32; RCBA32_OR(0x3434, 0x7); // LP LPC @@ -466,7 +473,7 @@ static void enable_lp_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0UL, 0x00007001); - pch_iobp_update(0xCE00C000, ~0UL, 0x00000001); + pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 } static void pch_set_acpi_mode(void)

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New patch to review for coreboot: 0cdd6d0 x86: use proper types for interrupt callbacks
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4141 -gerrit commit 0cdd6d04441003aaf57d52fbefb8228cf5c444aa Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 23 10:25:34 2013 -0500 x86: use proper types for interrupt callbacks The mainboard_interrupt_handlers() argument for the function pointer was using void * as the type. This does not allow the compiler to catch type differences for the arguments. Thus, some code has been committed which violates the new interrupt callbacks not taking any arguments. Make sure the compiler provides a type checking benefit. Change-Id: Ie20699a368e70c33a9a9912e0fcd63f1e6bb4f18 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48970 --- src/arch/x86/include/arch/interrupt.h | 4 ++-- src/device/oprom/realmode/x86.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 8c9b4a9..9753c50 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -23,9 +23,9 @@ /* setup interrupt handlers for mainboard */ #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE -extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)); #elif CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/oprom/yabel/biosemu.h> #else -static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +static inline void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { } #endif diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 338294d..4385c03 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -118,7 +118,7 @@ static int intXX_unknown_handler(void) } /* setup interrupt handlers for mainboard */ -void mainboard_interrupt_handlers(int intXX, void *intXX_func) +void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { intXX_handler[intXX] = intXX_func; }

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New patch to review for coreboot: 2bb3729 Unify and clean up remaining INT15 handlers
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4140 -gerrit commit 2bb3729d8db44ffefa2eee4465574baf2ccfaed8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 23 15:23:15 2013 -0700 Unify and clean up remaining INT15 handlers Some handlers still had 2 variants, others were incorrectly guarded by CONFIG_ variables. This patch straightens them out. This does not touch the siemens/sitemp_g1p1 which provides an interestingly complex solution for the int15 handler. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I5d74fdf7c2ab1faa96ebc2b5ca5c69398449b069 Reviewed-on: https://gerrit.chromium.org/gerrit/48979 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/ibase/mb899/mainboard.c | 6 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 4 +- src/mainboard/roda/rk886ex/mainboard.c | 4 +- src/mainboard/samsung/lumpy/mainboard.c | 134 ++++----------------------- src/mainboard/samsung/stumpy/mainboard.c | 111 ++++------------------ src/mainboard/thomson/ip1000/mainboard.c | 6 +- 7 files changed, 49 insertions(+), 218 deletions(-) diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 4fc7d04..dbbc598 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -20,13 +20,13 @@ #include <types.h> #include <device/device.h> #include <console/console.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> #include <arch/io.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -213,7 +213,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 92704c9..5f7d224 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -156,7 +156,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 061944a..0bee70e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -37,7 +37,7 @@ #define BOOT_DISPLAY_EFP2 (1 << 6) #define BOOT_DISPLAY_LCD2 (1 << 7) -#if CONFIG_VGA_ROM_RUN +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { /* This int15 handler is Intel IGD. specific. Other chipsets need other @@ -221,7 +221,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 575aa9b..9504701 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -60,7 +60,7 @@ static void backlight_enable(void) #define BOOT_DISPLAY_EFP2 (1 << 6) #define BOOT_DISPLAY_LCD2 (1 << 7) -#if CONFIG_VGA_ROM_RUN +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { /* This int15 handler is Intel IGD. specific. Other chipsets need other @@ -124,7 +124,7 @@ static void mainboard_enable(device_t dev) /* Disable Dummy DCC -> GP45 = 1 */ outb(inb(0x60f) | (1 << 5), 0x60f); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index be9a046..c1749f7 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -49,15 +49,15 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { int res=0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, X86_EAX & 0xffff); + __func__, X86_AX); - switch(X86_EAX & 0xffff) { + switch(X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -66,10 +66,8 @@ static int int15_handler(void) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; + X86_AX = 0x005f; + X86_CL = 0x00; res = 1; break; case 0x5f35: @@ -84,10 +82,8 @@ static int int15_handler(void) * bit 6 = EFP2 * * bit 7 = LFP2 */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; case 0x5f51: @@ -98,138 +94,46 @@ static int int15_handler(void) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0001; + X86_AX = 0x005f; + X86_CX = 0x0001; res = 1; break; case 0x5f70: - switch ((X86_ECX >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; case 1: /* Set Mux */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_EAX = 0x005f; + X86_ECX = 0x0000; res = 1; break; case 2: /* Get SG/Non-SG mode */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; default: /* FIXME: Interrupt was not handled, but return success? */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_ECX >> 8) & 0xff)); + X86_CH); return 1; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default - */ - X86_AX = 0x005f; - X86_CL = 0x00; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0000; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 1; - break; - case 0x5f70: - switch (X86_CH) { - case 0: - /* Get Mux */ - printk(BIOS_DEBUG, "Get Mux\n"); - X86_AX = 0x005f; - X86_CL = 0; - break; - case 1: - printk(BIOS_DEBUG, "Set Mux\n"); - /* Set Mux */ - X86_AX = 0x005f; - X86_CX = 0; - break; - case 2: - printk(BIOS_DEBUG, "Get SG Mode\n"); - /* Get SG/Non-SG mode */ - X86_AX = 0x005f; - X86_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - X86_CH); - return 0; - } - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - X86_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -302,7 +206,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index cbf5af7..30612db 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -42,15 +42,15 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { int res=0; printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, X86_EAX & 0xffff); + __func__, X86_AX); - switch(X86_EAX & 0xffff) { + switch(X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: @@ -59,10 +59,8 @@ static int int15_handler(void) * bit 0 = Centering (do not set with bit1 or bit2) * 0 = video bios default */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffffff00; - X86_ECX |= 0x01; + X86_AX = 0x005f; + X86_CL = 0x01; res = 1; break; case 0x5f35: @@ -77,10 +75,8 @@ static int int15_handler(void) * bit 6 = EFP2 * * bit 7 = LFP2 */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; case 0x5f51: @@ -91,115 +87,46 @@ static int int15_handler(void) * 02h = SVDO-LVDS, LFP driven by SVDO decoder * 03h = eDP, LFP Driven by Int-DisplayPort encoder */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0003; + X86_AX = 0x005f; + X86_CX = 0x0003; res = 1; break; case 0x5f70: - switch ((X86_ECX >> 8) & 0xff) { + switch (X86_CH) { case 0: /* Get Mux */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; case 1: /* Set Mux */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; case 2: /* Get SG/Non-SG mode */ - X86_EAX &= 0xffff0000; - X86_EAX |= 0x005f; - X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; + X86_AX = 0x005f; + X86_CX = 0x0000; res = 1; break; default: /* FIXME: Interrupt was not handled, but return sucess? */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_ECX >> 8) & 0xff)); + X86_CH); return 1; } break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } #endif -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL -static int int15_handler(void) -{ - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - */ - X86_AX = 0x005f; - X86_CX = 0x0001; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) * - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0000; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 3; - break; - case 0x5f70: - /* Unknown */ - X86_AX = 0x005f; - X86_CX = 0; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", - X86_AX); - return 0; - } - - /* Interrupt handled */ - return 1; -} -#endif - /* Audio Setup */ extern const u32 * cim_verb_data; @@ -220,7 +147,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 909c9f6..a23c6db 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <device/device.h> #include <delay.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN #include <x86emu/x86emu.h> #endif #include <arch/io.h> @@ -86,7 +86,7 @@ static void flash_gpios(void) } -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -141,7 +141,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif

1 0

New patch to review for coreboot: 6a7dfb2 cbmem utility: compatibility with older coreboot versions
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4139 -gerrit commit 6a7dfb2ec77be337a29f08e3f2179d8010fd2125 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 19 14:22:29 2013 -0700 cbmem utility: compatibility with older coreboot versions Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot table entries from a pointer to a uint64_t. This change was introduced to make the cbmem utility work on both 32bit and 64bit userland. Unfortunately, this broke the cbmem utility running on older versions of coreboot because they were still providing a 32bit only field for the address while the cbmem utility would now take the following 4 bytes as upper 32bits of a pointer that can obviously not be mmapped. This change checks if the size of the lb_cbmem_ref structure provided by coreboot is smaller than expected, and if so, ignore the upper 32bit of the address read. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: If4c8e9b72b2a38c961c11d7071b728e61e5f1d18 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 74e0fd4..e05a72a 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <inttypes.h> #include <getopt.h> #include <errno.h> #include <fcntl.h> @@ -128,6 +129,25 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of + * systems out there with a firmware that does not produce the right + * lb_cbmem_ref structure. Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret.cbmem_addr = (uint32_t)ret.cbmem_addr; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; @@ -184,12 +204,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: {

1 0

New patch to review for coreboot: 49cb209 lynxpoint: Rework LP GPIO handling
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4138 -gerrit commit 49cb209bd4b0cfe4020c7914a1dce3ad93ec7ec5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 13:43:23 2013 -0700 lynxpoint: Rework LP GPIO handling This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this. Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare. Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/wtm2/gpio.h | 439 +++++++----------------------- src/southbridge/intel/lynxpoint/lp_gpio.c | 18 +- src/southbridge/intel/lynxpoint/lp_gpio.h | 53 +++- 3 files changed, 156 insertions(+), 354 deletions(-) diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h index 179259c..884fd66 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.h @@ -22,348 +22,103 @@ #include "southbridge/intel/lynxpoint/lp_gpio.h" -const struct pch_lp_gpio_map mainboard_gpio_map[] = { - /* LPSS_UART1_RXD */ - { .gpio = 0, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_TXD */ - { .gpio = 1, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_RTS_N_R */ - { .gpio = 2, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_CTS_N */ - { .gpio = 3, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C0_SDA_R */ - { .gpio = 4, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C0_SCL */ - { .gpio = 5, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C1_SDA */ - { .gpio = 6, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C1_SCL */ - { .gpio = 7, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_WAKE_N */ - { .gpio = 8, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* ACCEL_INT2_MCP (NGFF_SLTA_UART_WAKE_N) */ - { .gpio = 9, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* SMC_RUNTIME_SCI_N */ - { .gpio = 10, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_ACPI, - .route = GPIO_ROUTE_SCI }, - /* AMB_THRM_R_N */ - { .gpio = 11, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_LANPHY_ENABLE */ - { .gpio = 12, - .conf0 = GPIO_MODE_NATIVE }, - /* USB32_P0_PWREN */ - { .gpio = 13, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SH_INT_ACCEL_DRDY_USB_INT_N */ - { .gpio = 14, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* LAN_PWREN_N */ - { .gpio = 15, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* LAN_RST_N */ - { .gpio = 16, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* CRIT_TEMP_REP_R_N (NGFF_SLTB_CARD_PRESENT_SSD_N) */ - { .gpio = 17, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW }, - /* TBT_FORCE_PWR */ - { .gpio = 18, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* EC_IN_RW */ - { .gpio = 19, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE, - .owner = GPIO_OWNER_GPIO }, - /* CK_REQ_P2_NGFFSLTA_N_R */ - { .gpio = 20, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_PCIE_LAN_REQ_N */ - { .gpio = 21, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_REQ_P4_TBT_N */ - { .gpio = 22, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_REQ_P5_N */ - { .gpio = 23, - .conf0 = GPIO_MODE_NATIVE }, - /* ME_PG_LED (NGFF_SLTB_WWN_CRD_PRSNT) */ - { .gpio = 24, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB_WAKEOUT_N */ - { .gpio = 25, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE }, - /* NFC_IRQ_MGP5 */ - { .gpio = 26, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* SMC_WAKE_SCI_N */ - { .gpio = 27, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE }, - /* PCH_NFC_RESET */ - { .gpio = 28, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PCH_SLP_WLAN_N */ - { .gpio = 29, - .conf0 = GPIO_MODE_NATIVE }, - /* SUS_PWR_ACK_R */ - { .gpio = 30, - .conf0 = GPIO_MODE_NATIVE }, - /* AC_PRESENT_R */ - { .gpio = 31, - .conf0 = GPIO_MODE_NATIVE }, - /* PM_CKRUN_N */ - { .gpio = 32, - .conf0 = GPIO_MODE_NATIVE }, - /* SATA0_PHYSLP */ - { .gpio = 33, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* ESATA_DET_N */ - { .gpio = 34, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SATA_DIRECT_PRSNT_R_N */ - { .gpio = 35, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SSD_SATA2_PCIE1_DET_N */ - { .gpio = 36, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SSD_SATA3_PCIE0_DET_N */ - { .gpio = 37, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SATA1_PHYSLP_DIRECT */ - { .gpio = 38, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* SMC_EXTSMI_N_R */ - { .gpio = 39, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_ACPI, - .route = GPIO_ROUTE_SMI }, - /* USB_OC_0_1_R_N */ - { .gpio = 40, - .conf0 = GPIO_MODE_NATIVE }, - /* USB_OC_2_6_R_N */ - { .gpio = 41, - .conf0 = GPIO_MODE_NATIVE }, - /* TBT_CIO_PLUG_SMI_N_R */ - { .gpio = 42, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB32_P1_PWREN */ - { .gpio = 43, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SENSOR_HUB_RST_N */ - { .gpio = 44, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* GYRO_INT2_MCP_R (TBT_WAKE_Q_N) */ - { .gpio = 45, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SNSR_HUB_PWREN */ - { .gpio = 46, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SPI_TPM_HDR_IRQ_N */ - { .gpio = 47, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* PCIE_TBT_RST_N */ - { .gpio = 48, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* COMBO_JD */ - { .gpio = 49, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* TOUCH_PANEL_INTR_N */ - { .gpio = 50, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* PCH_WIFI_RF_KILL_N */ - { .gpio = 51, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* TOUCH_PNL_RST_N_R */ - { .gpio = 52, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SNSR_HUB_I2C_WAKE / ALS_INT_MCP (NGFF_SLTB_WWAN_SSD_DET2) */ - { .gpio = 53, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO }, - /* NGFF_SLTB_SSD_MC_WAKE_N */ - { .gpio = 54, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO }, - /* TOUCHPAD_INTR_N */ - { .gpio = 55, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* NGFF_SLTB_WWAN_SSD_DET1 */ - { .gpio = 56, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SLTB_WWAN_PWREN */ - { .gpio = 57, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SLATEMODE_HALLOUT_R */ - { .gpio = 58, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB2_CAM_PWREN */ - { .gpio = 59, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB_CR_PWREN_N */ - { .gpio = 60, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_SUS_STAT_N */ - { .gpio = 61, - .conf0 = GPIO_MODE_NATIVE }, - /* SUS_CK */ - { .gpio = 62, - .conf0 = GPIO_MODE_NATIVE }, - /* SLP_S5_R_N */ - { .gpio = 63, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_CLK_CMNHDR_R */ - { .gpio = 64, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_CMD_CMNHDR_R */ - { .gpio = 65, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D0_CMNHDR_R */ - { .gpio = 66, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D1_CMNHDR_R */ - { .gpio = 67, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D2_CMNHDR_R */ - { .gpio = 68, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D3_CMNHDR_R1 */ - { .gpio = 69, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_PWREN_N_R (SDIO_POWER_EN) */ - { .gpio = 70, - .conf0 = GPIO_MODE_NATIVE }, - /* MPHY_PWREN */ - { .gpio = 71, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_BATLOW_R_N */ - { .gpio = 72, - .conf0 = GPIO_MODE_NATIVE }, - /* PCH_NOT_N */ - { .gpio = 73, - .conf0 = GPIO_MODE_NATIVE }, - /* SML1_DATA */ - { .gpio = 74, - .conf0 = GPIO_MODE_NATIVE }, - /* SML1_CK */ - { .gpio = 75, - .conf0 = GPIO_MODE_NATIVE }, - /* PCH_AUDIO_PWR_R */ - { .gpio = 76, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* PC_SLTB_SSD_RST_N_R */ - { .gpio = 77, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_EXTTS0_EC_N */ - { .gpio = 78, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SIO1007_IRQ_N */ - { .gpio = 79, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* PM_EXTTS1_R_N */ - { .gpio = 80, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* PCH_HDA_SPKR */ - { .gpio = 81, - .conf0 = GPIO_MODE_NATIVE }, - /* H_RCIN_N */ - { .gpio = 82, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_CS_R_N */ - { .gpio = 83, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_CLK_R */ - { .gpio = 84, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_MISO_R */ - { .gpio = 85, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_MOSI_BBS0_R */ - { .gpio = 86, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_CS_R_N */ - { .gpio = 87, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_CLK_R */ - { .gpio = 88, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_MISO_R */ - { .gpio = 89, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_RST_N */ - { .gpio = 90, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* LPSS_UART0_RXD */ - { .gpio = 91, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_TXD */ - { .gpio = 92, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_RTS_N */ - { .gpio = 93, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_CTS_N */ - { .gpio = 94, - .conf0 = GPIO_MODE_NATIVE }, - /* END */ - { .gpio = GPIO_LIST_END } +static const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ + LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ + LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ + LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ + LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ + LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ + LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ + LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ + LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ + LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ + LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ + LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ + LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ + LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ + LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ + LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ + LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ + LP_GPIO_INPUT, /* 19: EC_IN_RW */ + LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ + LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ + LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ + LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ + LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ + LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ + LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ + LP_GPIO_INPUT, /* 34: ESATA_DET_N */ + LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ + LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ + LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ + LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ + LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ + LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ + LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ + LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ + LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ + LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ + LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ + LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ + LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ + LP_GPIO_INPUT, /* 49: COMBO_JD */ + LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ + LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ + LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ + LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ + LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ + LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ + LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ + LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ + LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ + LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ + LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ + LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + LP_GPIO_NATIVE, /* 62: SUS_CK */ + LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ + LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ + LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ + LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ + LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ + LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ + LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ + LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ + LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ + LP_GPIO_NATIVE, /* 74: SML1_DATA */ + LP_GPIO_NATIVE, /* 75: SML1_CK */ + LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ + LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ + LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ + LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ + LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ + LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + LP_GPIO_NATIVE, /* 82: H_RCIN_N */ + LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ + LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ + LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ + LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ + LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ + LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ + LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ + LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ + LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ + LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ + LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ + LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ + LP_GPIO_END }; #endif diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 604423a..b90e5ba 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -45,19 +45,19 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) u32 irqen[3] = {0}; u32 reset[3] = {0}; u32 blink = 0; - int set, bit; + int set, bit, gpio = 0; - for (config = map; config->gpio != GPIO_LIST_END; config++) { - if (config->gpio > MAX_GPIO_NUMBER) - continue; + for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) { + if (gpio > MAX_GPIO_NUMBER) + break; /* Setup Configuration registers 1 and 2 */ - outl(config->conf0, gpio_base + GPIO_CONFIG0(config->gpio)); - outl(config->conf1, gpio_base + GPIO_CONFIG1(config->gpio)); + outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio)); + outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio)); /* Determine set and bit based on GPIO number */ - set = config->gpio >> 5; - bit = config->gpio % 32; + set = gpio >> 5; + bit = gpio % 32; /* Apply settings to set specific bits */ owner[set] |= config->owner << bit; @@ -83,7 +83,7 @@ int get_gpio(int gpio_num) { u16 gpio_base = get_gpio_base(); - if (gpio_num < MAX_GPIO_NUMBER) + if (gpio_num > MAX_GPIO_NUMBER) return 0; return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 9666adc..48a23cb 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -36,7 +36,7 @@ #define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8)) #define MAX_GPIO_NUMBER 94 /* zero based */ -#define GPIO_LIST_END 0xff +#define GPIO_LIST_END 0xffffffff /* conf0 */ @@ -54,8 +54,10 @@ #define GPI_LEVEL (1 << 30) -#define GPO_LEVEL_LOW (0 << 31) -#define GPO_LEVEL_HIGH (1 << 31) +#define GPO_LEVEL_SHIFT 31 +#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT) /* conf1 */ @@ -91,6 +93,51 @@ #define GPIO_RESET_PWROK 0 #define GPIO_RESET_RSMRST 1 +#define LP_GPIO_END \ + { .conf0 = GPIO_LIST_END } + +#define LP_GPIO_NATIVE \ + { .conf0 = GPIO_MODE_NATIVE } + +#define LP_GPIO_UNUSED \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + +#define LP_GPIO_ACPI_SCI \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ + .owner = GPIO_OWNER_ACPI, \ + .route = GPIO_ROUTE_SCI } + +#define LP_GPIO_ACPI_SMI \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_ACPI, \ + .route = GPIO_ROUTE_SMI } + +#define LP_GPIO_INPUT \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_GPIO } + +#define LP_GPIO_IRQ_EDGE \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ + .owner = GPIO_OWNER_GPIO, \ + .irqen = GPIO_IRQ_ENABLE } + +#define LP_GPIO_IRQ_LEVEL \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \ + .owner = GPIO_OWNER_GPIO, \ + .irqen = GPIO_IRQ_ENABLE } + +#define LP_GPIO_OUT_HIGH \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + +#define LP_GPIO_OUT_LOW \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + struct pch_lp_gpio_map { u8 gpio; u32 conf0;

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New patch to review for coreboot: c0290d3 lynxpoint: Add a function to set an individual GPIO
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4137 -gerrit commit c0290d3dec750d62685e93b0474d96d24c80424a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 13:44:37 2013 -0700 lynxpoint: Add a function to set an individual GPIO This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/gpio.c | 19 +++++++++++++++++++ src/southbridge/intel/lynxpoint/lp_gpio.c | 14 ++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 4 ++++ 3 files changed, 37 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index b492068..34157a1 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -109,3 +109,22 @@ unsigned get_gpios(const int *gpio_num_array) } return vector; } + +void set_gpio(int gpio_num, int value) +{ + static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_basde + gpio_reg_offsets[index]); + config &= ~(1 << bit); + config |= value << bit; + outl(config, gpio_base + gpio_reg_offsets[index]); +} diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index a6e4f5c..604423a 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -107,3 +107,17 @@ unsigned get_gpios(const int *gpio_num_array) } return vector; } + +void set_gpio(int gpio_num, int value) +{ + u16 gpio_base = get_gpio_base(); + u32 conf0; + + if (gpio_num > MAX_GPIO_NUMBER) + return; + + conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num)); + conf0 &= ~GPO_LEVEL_MASK; + conf0 |= value << GPO_LEVEL_SHIFT; + outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num)); +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c049573..4bdb926 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -193,6 +193,10 @@ int get_gpio(int gpio_num); * the array of gpio pin numbers to scan, terminated by -1. */ unsigned get_gpios(const int *gpio_num_array); +/* + * set GPIO pin value + */ +void set_gpio(int gpio_num, int value); #endif #define MAINBOARD_POWER_OFF 0

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New patch to review for coreboot: cf4ef7d haswell: calibrate 24MHz clock against BCLK
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4136 -gerrit commit cf4ef7d90b247fbb24fb2b3afd198cc70d8cd98f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 10 14:59:21 2013 -0500 haswell: calibrate 24MHz clock against BCLK On haswell ULT systems there is a 24MHz clock that continuously runs when deep package c-states are entered. The 100MHz BCLK is shut down in the lower c-states. When the package wakes back up a conversion formula needs to be applied. The 24MHz calibration is done using the internal PCODE unit. Change-Id: I6be7702fb1de1429273724536f5af9125b98da64 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48292 Tested-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/haswell/haswell.h | 19 ++++++++++++ src/cpu/intel/haswell/haswell_init.c | 60 ++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index ab1cef4..96f94eb 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -100,6 +100,25 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +/* PCODE MMIO communications live in the MCHBAR. */ +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +/* Errors are returned back in bits 7:0. */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 +/* Data is passed through bits 31:0 of the data register. */ +#define BIOS_MAILBOX_DATA 0x5da0 + /* Region of SMM space is reserved for multipurpose use. It falls below * the IED region and above the SMM handler. */ #define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5b53afe..0b7a898 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -34,6 +34,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include <delay.h> #include <pc80/mc146818rtc.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -217,6 +218,62 @@ static int is_ult(void) return ult; } +/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly + * when a core is woken up. */ +static int pcode_ready(void) +{ + int wait_count; + const int delay_step = 10; + + wait_count = 0; + do { + if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) + return 0; + wait_count += delay_step; + udelay(delay_step); + } while (wait_count < 1000); + + return -1; +} + +static void calibrate_24mhz_bclk(void) +{ + int err_code; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return; + } + + /* A non-zero value initiates the PCODE calibration. */ + MCHBAR32(BIOS_MAILBOX_DATA) = ~0; + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return; + } + + err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + err_code); + + /* Read the calibrated value. */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); + return; + } + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + MCHBAR32(BIOS_MAILBOX_DATA)); +} + int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -517,6 +574,9 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); x86_mtrr_check(); + if (is_ult()) + calibrate_24mhz_bclk(); + /* Call through the cpu driver's initialization. */ cpu_initialize(0); }

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coreboot-gerrit November 2013