Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4174
-gerrit
commit bb70f61af70b255176330b04d50cf32aec19f3a2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri May 17 11:56:09 2013 -0700
libpayload (EHCI): correctly align PORTSC
Two structures in the USB EHCI stack were pointing
to hardware but not marked attribute((packed)) hence
leaving it to GCC to correctly align the data structures.
Next, the number of reserved bytes in hc_op_t was wrong
(but implicitly aligned to the correct values on x86)
It seems this worked fine on x86, but on ARM it was doing
the wrong thing.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d
Reviewed-on: https://gerrit.chromium.org/gerrit/55555
Commit-Queue: Stefan Reinauer <reinauer(a)google.com>
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Tested-by: Stefan Reinauer <reinauer(a)google.com>
---
payloads/libpayload/drivers/usb/ehci_private.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h
index 3b9faf6..3365be1 100644
--- a/payloads/libpayload/drivers/usb/ehci_private.h
+++ b/payloads/libpayload/drivers/usb/ehci_private.h
@@ -78,10 +78,10 @@ typedef volatile struct {
u32 ctrldssegment;
u32 periodiclistbase;
u32 asynclistaddr;
- u8 res1[0x3f-0x1c];
+ u8 res1[0x40-0x1c];
u32 configflag;
portsc_t portsc[0];
-} hc_op_t;
+} __attribute__ ((packed)) hc_op_t;
typedef volatile struct {
#define QTD_TERMINATE 1
@@ -130,7 +130,7 @@ typedef volatile struct {
#define QH_PIPE_MULTIPLIER_SHIFT 30
volatile u32 current_td_ptr;
volatile qtd_t td;
-} ehci_qh_t;
+} __attribute__ ((packed)) ehci_qh_t;
typedef struct ehci {
hc_cap_t *capabilities;
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4172
-gerrit
commit c323d9db27311ba04123d235adc0f95c3a7c1f86
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed May 15 17:02:23 2013 -0700
slippy: set PWM values
The dev screen was not displaying properly. With the
PWM values programmed the screen displays correctly.
Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51472
---
src/mainboard/google/slippy/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 143147f..29c4763 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -9,6 +9,10 @@ chip northbridge/intel/haswell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4171
-gerrit
commit c1823cb069789273287a8beace3a62aac5b783ef
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 15 15:05:38 2013 -0700
slippy: Put SerialIO devices in PCI mode
The device at function 0 also needs to be enabled
or the kernel will ignore all other functions.
00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03)
00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03)
00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03)
Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51370
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/slippy/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 665e6dc..143147f 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -56,13 +56,13 @@ chip northbridge/intel/haswell
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
+ register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 off end # Serial I/O DMA
+ device pci 15.0 on end # Serial I/O DMA
device pci 15.1 on end # I2C0
device pci 15.2 on end # I2C1
device pci 15.3 off end # GSPI0
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4167
-gerrit
commit aa2b1fe0530d3106d86e59791d49e18f8bf0914d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 10 11:00:56 2013 -0700
slippy: Add EC to the device tree
This lets the keyboard init get called properly.
Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50853
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/slippy/devicetree.cb | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 5fb3cb4..665e6dc 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -84,7 +84,15 @@ chip northbridge/intel/haswell
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on end # LPC bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal