coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c37b05c nvramtool: write size field more obviously
by gerrit＠coreboot.org 18 Nov '13

18 Nov '13

the following patch was just integrated into master: commit c37b05c41339acbeee00bd65c13b8a97b16854ce Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Nov 11 15:16:53 2013 +0100 nvramtool: write size field more obviously The field wasn't initialized in RAM first and later overwritten in a somewhat twisted way (that relied on the size field coming after the tag field in the struct). Change-Id: Ibe931b297df51e3c46ae163e059338781f5a27e2 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/4087 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4087 for details. -gerrit

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New patch to review for coreboot: 283b446 slippy: Clean up for easier porting
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4183 -gerrit commit 283b446cb567d6e5c4f101fc67c3c7d56cf32217 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 22 16:13:49 2013 -0700 slippy: Clean up for easier porting Minor tweaks to variable names in the slippy mainboard that make it easier to base a new board from without as much renaming. Also properly set up the thermal variables for the thermal zone that is defined in ACPI instead of using the generic setup from WTM2. Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56328 --- src/mainboard/google/slippy/acpi_tables.c | 23 +++++------------- src/mainboard/google/slippy/ec.c | 14 +++++------ src/mainboard/google/slippy/ec.h | 18 +++++++------- src/mainboard/google/slippy/gpio.h | 2 +- src/mainboard/google/slippy/mainboard.c | 2 +- src/mainboard/google/slippy/smihandler.c | 6 ++--- src/mainboard/google/slippy/thermal.h | 40 ++++++++++--------------------- 7 files changed, 40 insertions(+), 65 deletions(-) diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index f816257..7a3ccea 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -44,29 +44,18 @@ unsigned long acpi_create_slic(unsigned long current); static void acpi_update_thermal_table(global_nvs_t *gnvs) { - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; - gnvs->f4pw = FAN4_PWM; + gnvs->tmps = CTDP_SENSOR_ID; - gnvs->f3of = FAN3_THRESHOLD_OFF; - gnvs->f3on = FAN3_THRESHOLD_ON; - gnvs->f3pw = FAN3_PWM; + gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; + gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON; - gnvs->f2of = FAN2_THRESHOLD_OFF; - gnvs->f2on = FAN2_THRESHOLD_ON; - gnvs->f2pw = FAN2_PWM; - - gnvs->f1of = FAN1_THRESHOLD_OFF; - gnvs->f1on = FAN1_THRESHOLD_ON; - gnvs->f1pw = FAN1_PWM; - - gnvs->f0of = FAN0_THRESHOLD_OFF; - gnvs->f0on = FAN0_THRESHOLD_ON; - gnvs->f0pw = FAN0_PWM; + gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; + gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; } static void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 3c25987..0919f0f 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -24,25 +24,25 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" -void slippy_ec_init(void) +void mainboard_ec_init(void) { - printk(BIOS_DEBUG, "slippy_ec_init\n"); + printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); /* Restore SCI event mask on resume. */ if (acpi_slp_type == 3) { - google_chromeec_log_events(SLIPPY_EC_LOG_EVENTS | - SLIPPY_EC_S3_WAKE_EVENTS); + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); /* Disable SMI and wake events */ google_chromeec_set_smi_mask(0); /* Clear pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(SLIPPY_EC_SCI_EVENTS); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { - google_chromeec_log_events(SLIPPY_EC_LOG_EVENTS | - SLIPPY_EC_S5_WAKE_EVENTS); + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); } /* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h index 312e79f..11d2453 100644 --- a/src/mainboard/google/slippy/ec.h +++ b/src/mainboard/google/slippy/ec.h @@ -17,15 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SLIPPY_EC_H -#define SLIPPY_EC_H +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H #include <ec/google/chromeec/ec_commands.h> #define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ #define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ -#define SLIPPY_EC_SCI_EVENTS \ +#define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ @@ -37,26 +37,26 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) -#define SLIPPY_EC_SMI_EVENTS \ +#define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) /* EC can wake from S5 with lid or power button */ -#define SLIPPY_EC_S5_WAKE_EVENTS \ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* EC can wake from S3 with lid or power button or key press */ -#define SLIPPY_EC_S3_WAKE_EVENTS \ - (SLIPPY_EC_S5_WAKE_EVENTS |\ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) /* Log EC wake events plus EC shutdown events */ -#define SLIPPY_EC_LOG_EVENTS \ +#define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) #ifndef __ACPI__ -extern void slippy_ec_init(void); +extern void mainboard_ec_init(void); #endif #endif diff --git a/src/mainboard/google/slippy/gpio.h b/src/mainboard/google/slippy/gpio.h index cc74674..7fb670b 100644 --- a/src/mainboard/google/slippy/gpio.h +++ b/src/mainboard/google/slippy/gpio.h @@ -20,7 +20,7 @@ #ifndef SLIPPY_GPIO_H #define SLIPPY_GPIO_H -#include "southbridge/intel/lynxpoint/lp_gpio.h" +struct pch_lp_gpio_map; const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index c13d0bb..0159bd0 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -142,7 +142,7 @@ static void verb_setup(void) static void mainboard_init(device_t dev) { - slippy_ec_init(); + mainboard_ec_init(); } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 01e763e..7b7dd69 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -117,7 +117,7 @@ void mainboard_smi_sleep(u8 slp_typ) while (google_chromeec_get_event() != 0); /* Enable wake events */ - google_chromeec_set_wake_mask(SLIPPY_EC_S3_WAKE_EVENTS); + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); } #define APMC_FINALIZE 0xcb @@ -143,13 +143,13 @@ int mainboard_smi_apmc(u8 apmc) google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(SLIPPY_EC_SCI_EVENTS); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); break; case APM_CNT_ACPI_DISABLE: google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(SLIPPY_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; break; } return 0; diff --git a/src/mainboard/google/slippy/thermal.h b/src/mainboard/google/slippy/thermal.h index cb67d80..fceaeca 100644 --- a/src/mainboard/google/slippy/thermal.h +++ b/src/mainboard/google/slippy/thermal.h @@ -20,38 +20,24 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff +/* Config TDP Sensor ID */ +#define CTDP_SENSOR_ID 1 /* PECI */ + +/* Config TDP Nominal */ +#define CTDP_NOMINAL_THRESHOLD_OFF 0 +#define CTDP_NOMINAL_THRESHOLD_ON 0 + +/* Config TDP Down */ +#define CTDP_DOWN_THRESHOLD_OFF 80 +#define CTDP_DOWN_THRESHOLD_ON 90 /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 104 /* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +#define PASSIVE_TEMPERATURE 100 /* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 +#define MAX_TEMPERATURE 105 #endif

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New patch to review for coreboot: 05b364e lynxpoint: fix mem corruption during ssdt2 gen
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4182 -gerrit commit 05b364e0aa283d43f75df1933cdf8369fc1670a8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 22 15:28:20 2013 -0500 lynxpoint: fix mem corruption during ssdt2 gen The ssdt2 generation code was calling acpigen_patch_len(). However, none of the entries had AML object lengths that needed patching. That resulted in the following message: ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c', line 52 Additionally, this caused an errant write to a memory address whose value was in the variable ltop. This was the 0 address. Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56299 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/lynxpoint/acpi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index ccf4323..b619e6e 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -88,7 +88,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) len += acpi_create_serialio_ssdt_entry(id, gnvs); - acpigen_patch_len(len-1); /* (Re)calculate length and checksum. */ current = (unsigned long)acpigen_get_current();

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New patch to review for coreboot: 76ef370 lynxpoint: Fix XHCI controller device in ACPI
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4181 -gerrit commit 76ef370726a095310d1657ba7871b164e7c1b2d2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 22 09:51:11 2013 -0700 lynxpoint: Fix XHCI controller device in ACPI The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/usb.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index cf3e6a0..5c1f6a5 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -23,11 +23,11 @@ // EHCI Controller 0:1d.0 -Device (EHC1) +Device (EHCI) { Name(_ADR, 0x001d0000) - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake // Leave USB ports on for to allow Wake from USB @@ -55,13 +55,13 @@ Device (EHC1) } } -// EHCI #2 Controller 0:1a.0 +// XHCI Controller 0:14.0 -Device (EHC2) +Device (XHCI) { - Name(_ADR, 0x001a0000) + Name(_ADR, 0x00140000) - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake // Leave USB ports on for to allow Wake from USB

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New patch to review for coreboot: 903933a lynxpoint: Enable SerialIO clock in PCI mode
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4180 -gerrit commit 903933ab980e87312e7594e765e437e7242ca86d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 16:37:40 2013 -0700 lynxpoint: Enable SerialIO clock in PCI mode The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 26 ++++++++++++++++++++----- src/southbridge/intel/lynxpoint/pch.h | 6 ++++++ src/southbridge/intel/lynxpoint/serialio.c | 31 ++++++++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cc3718d..58c68cd 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -83,10 +83,18 @@ u16 get_gpiobase(void) #ifndef __SMM__ +/* Put device in D3Hot Power State */ +static void pch_enable_d3hot(device_t dev) +{ + u32 reg32 = pci_read_config32(dev, PCH_PCS); + reg32 |= PCH_PCS_PS_D3HOT; + pci_write_config32(dev, PCH_PCS, reg32); +} + /* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(unsigned devfn) +static void pch_hide_devfn(device_t dev) { - switch (devfn) { + switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ RCBA32_OR(FD, PCH_DISABLE_ADSPD); break; @@ -94,24 +102,31 @@ static void pch_hide_devfn(unsigned devfn) RCBA32_OR(FD, PCH_DISABLE_XHCI); break; case PCI_DEVFN(21, 0): /* DMA */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ @@ -127,6 +142,7 @@ static void pch_hide_devfn(unsigned devfn) RCBA32_OR(FD2, PCH_DISABLE_KT); break; case PCI_DEVFN(23, 0): /* SDIO */ + pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ @@ -146,7 +162,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ - RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); break; case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); @@ -404,7 +420,7 @@ static void pch_pcie_enable(device_t dev) new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); + pch_hide_devfn(dev); } else { int fn; @@ -463,7 +479,7 @@ void pch_enable(device_t dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); + pch_hide_devfn(dev); } else { /* Enable SERR */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ca1d8b1..b01fdc0 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -218,6 +218,10 @@ void set_gpio(int gpio_num, int value); #define SEE (1 << 1) #define PERE (1 << 0) +/* Power Management Control and Status */ +#define PCH_PCS 0x84 +#define PCH_PCS_PS_D3HOT 3 + #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) @@ -377,6 +381,8 @@ void set_gpio(int gpio_num, int value); #define SIO_ID_UART1 6 /* D21:F6 */ #define SIO_ID_SDIO 7 /* D23:F0 */ +#define SIO_REG_PPR_CLOCK 0x800 +#define SIO_REG_PPR_CLOCK_EN (1 << 0) #define SIO_REG_PPR_RST 0x804 #define SIO_REG_PPR_RST_ASSERT 0x3 #define SIO_REG_PPR_GEN 0x808 diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 11d6a36..8257cc2 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -29,6 +29,22 @@ #include "pch.h" #include "nvs.h" +/* Set D3Hot Power State in ACPI mode */ +static void serialio_enable_d3hot(struct device *dev) +{ + u32 reg32 = pci_read_config32(dev, PCH_PCS); + reg32 |= PCH_PCS_PS_D3HOT; + pci_write_config32(dev, PCH_PCS, reg32); +} + +/* Enable clock in PCI mode */ +static void serialio_enable_clock(struct resource *bar0) +{ + u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK); + reg32 |= SIO_REG_PPR_CLOCK_EN; + write32(bar0->base + SIO_REG_PPR_CLOCK, reg32); +} + /* Put Serial IO D21:F0-F6 device into desired mode. */ static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) { @@ -143,9 +159,15 @@ static void serialio_init(struct device *dev) struct southbridge_intel_lynxpoint_config *config = dev->chip_info; struct resource *bar0, *bar1; int sio_index = -1; + u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); + /* Ensure memory and bus master are enabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); if (!bar0) @@ -154,6 +176,11 @@ static void serialio_init(struct device *dev) if (!bar1) return; + if (!config->sio_acpi_mode) + serialio_enable_clock(bar0); + else if (dev->path.pci.devfn != PCI_DEVFN(21, 0)) + serialio_enable_d3hot(dev); /* all but SDMA */ + switch (dev->path.pci.devfn) { case PCI_DEVFN(21, 0): /* SDMA */ sio_index = SIO_ID_SDMA; @@ -241,9 +268,9 @@ static struct pci_operations pci_ops = { }; static struct device_operations device_ops = { - .read_resources = pci_bus_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = serialio_init, .ops_pci = &pci_ops, };

1 0

New patch to review for coreboot: 4ce0b78 libpayload: Fix xcompile
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4179 -gerrit commit 4ce0b7871b289f032cfeaf7e69b741e1a3e19aab Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 21 12:15:50 2013 -0700 libpayload: Fix xcompile The architecture name for our ARM port is armv7, not arm. Hence, none of those flags were ever actually used. Fix the architecture name and remove the flags, they should not be set in xcompile, but in the Makefile, like in coreboot. Change-Id: Id9c5db7ebceafddb58a1ce1988417f09c074ba6c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56084 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/util/xcompile/xcompile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile index 58f086f..09c1879 100644 --- a/payloads/libpayload/util/xcompile/xcompile +++ b/payloads/libpayload/util/xcompile/xcompile @@ -106,12 +106,9 @@ detect_special_flags() { CFLAGS="$CFLAGS -Wl,--build-id=none" case "$architecture" in - arm ) + armv7 ) # testcc "$CC" "$CFLAGS -mcpu=cortex-a9" && # CFLAGS="$CFLAGS -mcpu=cortex-a9" - testcc "$CC" \ -"$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux -march=armv7" && -CFLAGS="$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux -march=armv7" ;; esac }

1 0

New patch to review for coreboot: 7366469 slippy: Run EC init as part of mainboard init step
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4178 -gerrit commit 736646929654cc598e81d0a7ed350d21ce88fcb5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 10:11:07 2013 -0700 slippy: Run EC init as part of mainboard init step This will log and clear EC events so they do not take effect when the SMI handler is enabled. Change-Id: I5ef563f7cedc8977410cc3f69e2655fc4e14c9eb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56055 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/mainboard.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index c91be19..c13d0bb 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -35,6 +35,7 @@ #include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> +#include "ec.h" void mainboard_suspend_resume(void) { @@ -139,11 +140,17 @@ static void verb_setup(void) cim_verb_data_size = sizeof(mainboard_cim_verb_data); } +static void mainboard_init(device_t dev) +{ + slippy_ec_init(); +} + // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->init = mainboard_init; #if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler);

1 0

New patch to review for coreboot: d79cd2b slippy: Enable EC SMI
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4177 -gerrit commit d79cd2b432efeeaf7c27fef2ffb4ac0ff9d410df Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 09:28:28 2013 -0700 slippy: Enable EC SMI Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC. 1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/slippy/devicetree.cb | 3 ++- src/southbridge/intel/lynxpoint/lp_gpio.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 29c4763..fc6462c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -49,7 +49,8 @@ chip northbridge/intel/haswell register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" - register "alt_gp_smi_en" = "0x0000" + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 48a23cb..d9927dc 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -110,7 +110,7 @@ .route = GPIO_ROUTE_SCI } #define LP_GPIO_ACPI_SMI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ .owner = GPIO_OWNER_ACPI, \ .route = GPIO_ROUTE_SMI }

1 0

New patch to review for coreboot: ad47960 slippy: Update interrupt routing
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4176 -gerrit commit ad479604070f343bda241d7cea8a559978334907 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 21 08:05:39 2013 -0700 slippy: Update interrupt routing The SerialIO devices have specific requirements for PCI interrupt mode to use PIRQ{E,F,G,H} that are not being met. D21:F0 uses PIRQE, which must not be shared with other PCH D21:F1-F6 share PIRQF, which must not be shared with other PCH D23:F0 uses PIRQH, which must not be shared with other PCH - Fix D20IR -> D20IP typo - Remove D25/EHCI2 as it does not exist - Reorder other interrupts to clear PIRQE/PIRQF/PIRQH Check device interrupts in the kernel 0: IO-APIC-edge timer 1: IO-APIC-edge i8042 8: IO-APIC-edge rtc0 9: IO-APIC-fasteoi acpi 16: IO-APIC-fasteoi ath9k 18: IO-APIC-fasteoi i801_smbus 19: IO-APIC-fasteoi ehci_hcd:usb1 21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1 40: PCI-MSI-edge PCIe PME 41: PCI-MSI-edge i915 42: PCI-MSI-edge ahci 43: PCI-MSI-edge xhci_hcd 44: PCI-MSI-edge snd_hda_intel Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56028 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- .../google/slippy/acpi/haswell_pci_irqs.asl | 51 ++++++++++++---------- src/mainboard/google/slippy/romstage.c | 30 ++++++------- 2 files changed, 42 insertions(+), 39 deletions(-) diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl index a8b6b5f..82a2eba 100644 --- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl @@ -29,26 +29,26 @@ Method(_PRT) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, 0, 22 }, // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, // EHCI 0:1d.0 Package() { 0x001dffff, 0, 0, 19 }, // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 16 }, + Package() { 0x0014ffff, 0, 0, 18 }, // LPC devices 0:1f.0 Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, Package() { 0x001fffff, 3, 0, 16 }, // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 16 }, - Package() { 0x0015ffff, 1, 0, 17 }, - Package() { 0x0015ffff, 2, 0, 18 }, - Package() { 0x0015ffff, 3, 0, 19 }, + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 16 }, + Package() { 0x0017ffff, 0, 0, 23 }, }) } Else { Return (Package() { @@ -57,19 +57,26 @@ Method(_PRT) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, }) } } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index a02a84d..01f613d 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -35,13 +35,12 @@ const struct rcba_config_instruction rcba_config[] = { /* * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQA + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQG (MSI) */ @@ -53,21 +52,18 @@ const struct rcba_config_instruction rcba_config[] = { (INTB << D28IP_P4IP)), RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),

1 0

New patch to review for coreboot: 2e2b6cb libpayload: Add USB support for non-PCI controllers
by Stefan Reinauer 18 Nov '13

18 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4175 -gerrit commit 2e2b6cb639d9a9adef7f51ac66221031c5f86ca8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 2 16:16:41 2013 -0700 libpayload: Add USB support for non-PCI controllers Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 --- payloads/libpayload/Config.in | 28 ++++++++++++++++-- payloads/libpayload/drivers/usb/ehci.c | 41 ++++++++++++++++---------- payloads/libpayload/drivers/usb/ehci.h | 3 +- payloads/libpayload/drivers/usb/ehci_private.h | 1 - payloads/libpayload/drivers/usb/ehci_rh.c | 2 ++ payloads/libpayload/drivers/usb/ohci.c | 24 +++++++++++---- payloads/libpayload/drivers/usb/ohci.h | 5 ++-- payloads/libpayload/drivers/usb/ohci_private.h | 1 - payloads/libpayload/drivers/usb/uhci.c | 11 +++---- payloads/libpayload/drivers/usb/uhci.h | 4 +-- payloads/libpayload/drivers/usb/usbhub.c | 2 ++ payloads/libpayload/drivers/usb/usbinit.c | 33 +++++++++++++++++---- payloads/libpayload/drivers/usb/usbmsc.c | 1 + payloads/libpayload/drivers/usb/xhci.c | 36 ++++++++++++++-------- payloads/libpayload/drivers/usb/xhci.h | 5 ++-- payloads/libpayload/include/usb/usb.h | 3 +- 16 files changed, 142 insertions(+), 58 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 6610f8f..bb5176f 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -326,7 +326,7 @@ config USB config USB_UHCI bool "Support for USB UHCI controllers" - depends on USB + depends on USB && ARCH_X86 help Select this option if you are going to use USB 1.1 on an Intel based system. @@ -335,7 +335,7 @@ config USB_OHCI bool "Support for USB OHCI controllers" depends on USB help - Select this option if you are going to use USB 1.1 on an AMD based + Select this option if you are going to use USB 1.1 on a non-Intel based system. config USB_EHCI @@ -382,6 +382,30 @@ config USB_GEN_HUB bool default n if (!USB_HUB && !USB_XHCI) default y if (USB_HUB || USB_XHCI) +config USB_PCI + bool + default y if ARCH_X86 + default n + +config USB_MEMORY + bool + default y if ARCH_ARMV7 + default n + +config USB_OHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_OHCI + default 0x12120000 + +config USB_EHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_EHCI + default 0x12110000 + +config USB_XHCI_BASE_ADDRESS + hex + depends on USB_MEMORY && USB_XHCI + default 0x12000000 endmenu diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index f5c14d5..e61e806 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -69,7 +69,7 @@ static void dump_td(u32 addr) usb_debug("+---------------------------------------------------+\n"); } -#ifdef USB_DEBUG +#if 0 && defined(USB_DEBUG) static void dump_qh(ehci_qh_t *cur) { qtd_t *tmp_qtd = NULL; @@ -724,7 +724,7 @@ static u8 *ehci_poll_intr_queue(void *const queue) } hci_t * -ehci_init (pcidev_t addr) +ehci_init (void *bar) { int i; hci_t *controller = new_controller (); @@ -736,15 +736,6 @@ ehci_init (pcidev_t addr) if(!controller->instance) fatal("Not enough memory creating USB controller instance.\n"); -#define PCI_COMMAND 4 -#define PCI_COMMAND_IO 1 -#define PCI_COMMAND_MEMORY 2 -#define PCI_COMMAND_MASTER 4 - - u32 pci_command = pci_read_config32(addr, PCI_COMMAND); - pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; - pci_write_config32(addr, PCI_COMMAND, pci_command); - controller->type = EHCI; controller->start = ehci_start; @@ -760,8 +751,7 @@ ehci_init (pcidev_t addr) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; - controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, USBBASE); + controller->reg_base = (u32)(unsigned long)bar; for (i = 0; i < 128; i++) { controller->devices[i] = 0; } @@ -770,9 +760,6 @@ ehci_init (pcidev_t addr) EHCI_INST(controller)->capabilities = phys_to_virt(controller->reg_base); EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(controller->reg_base) + EHCI_INST(controller)->capabilities->caplength); - /* default value for frame length adjust */ - pci_write_config8(addr, FLADJ, FLADJ_framelength(60000)); - /* Set the high address word (aka segment) if controller is 64-bit */ if (EHCI_INST(controller)->capabilities->hccparams & 1) EHCI_INST(controller)->operation->ctrldssegment = 0; @@ -818,3 +805,25 @@ ehci_init (pcidev_t addr) return controller; } + +#ifdef CONFIG_USB_PCI +hci_t * +ehci_pci_init (pcidev_t addr) +{ + hci_t *controller; + u32 reg_base; + + u32 pci_command = pci_read_config32(addr, PCI_COMMAND); + pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; + pci_write_config32(addr, PCI_COMMAND, pci_command); + + reg_base = pci_read_config32 (addr, USBBASE); + + /* default value for frame length adjust */ + pci_write_config8(addr, FLADJ, FLADJ_framelength(60000)); + + controller = ehci_init((void *)(unsigned long)reg_base); + + return controller; +} +#endif diff --git a/payloads/libpayload/drivers/usb/ehci.h b/payloads/libpayload/drivers/usb/ehci.h index c66643c..c1b1fa9 100644 --- a/payloads/libpayload/drivers/usb/ehci.h +++ b/payloads/libpayload/drivers/usb/ehci.h @@ -33,7 +33,8 @@ #include <pci.h> #include <usb/usb.h> -hci_t *ehci_init (pcidev_t addr); +hci_t *ehci_pci_init (pcidev_t addr); +hci_t *ehci_init (void *bar); void ehci_rh_init (usbdev_t *dev); diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index 3365be1..986ee79 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -30,7 +30,6 @@ #ifndef __EHCI_PRIVATE_H #define __EHCI_PRIVATE_H -#include <pci.h> #include <usb/usb.h> #define USBBASE 0x10 diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 8982804..5c4daed 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -27,6 +27,8 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG + #include <libpayload.h> #include "ehci.h" #include "ehci_private.h" diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 95db5f4..edd275b 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -136,7 +136,7 @@ ohci_reinit (hci_t *controller) { } -#ifdef USB_DEBUG +#if 0 && defined(USB_DEBUG) /* Section 4.3.3 */ static const char *completion_codes[] = { "No error", @@ -167,7 +167,7 @@ static const char *direction[] = { #endif hci_t * -ohci_init (pcidev_t addr) +ohci_init (void *bar) { int i; @@ -201,10 +201,7 @@ ohci_init (pcidev_t addr) init_device_entry (controller, 0); OHCI_INST (controller)->roothub = controller->devices[0]; - controller->bus_address = addr; - /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 - * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ - controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear + controller->reg_base = (u32)(unsigned long)bar; OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); @@ -255,6 +252,21 @@ ohci_init (pcidev_t addr) return controller; } +#ifdef CONFIG_USB_PCI +hci_t * +ohci_pci_init (pcidev_t addr) +{ + u32 reg_base; + + /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 + * BASE ADDRESS only [31-12] bits. All other usually 0, but not all. + * OHCI mandates MMIO, so bit 0 is clear */ + reg_base = pci_read_config32 (addr, 0x10) & 0xfffff000; + + return ohci_init((void *)(unsigned long)reg_base); +} +#endif + static void ohci_shutdown (hci_t *controller) { diff --git a/payloads/libpayload/drivers/usb/ohci.h b/payloads/libpayload/drivers/usb/ohci.h index f501167..9c31d9c 100644 --- a/payloads/libpayload/drivers/usb/ohci.h +++ b/payloads/libpayload/drivers/usb/ohci.h @@ -33,8 +33,9 @@ #include <pci.h> #include <usb/usb.h> - hci_t *ohci_init (pcidev_t addr); +hci_t *ohci_pci_init (pcidev_t addr); +hci_t *ohci_init (void *bar); - void ohci_rh_init (usbdev_t *dev); +void ohci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index a32203c..b6eaf6b 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -30,7 +30,6 @@ #ifndef __OHCI_PRIVATE_H #define __OHCI_PRIVATE_H -#include <pci.h> #include <usb/usb.h> #define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit)) diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index f9c361d..b81b911 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -147,7 +147,7 @@ uhci_reinit (hci_t *controller) } hci_t * -uhci_init (pcidev_t addr) +uhci_pci_init (pcidev_t addr) { int i; u16 reg16; @@ -182,16 +182,17 @@ uhci_init (pcidev_t addr) init_device_entry (controller, 0); UHCI_INST (controller)->roothub = controller->devices[0]; - controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */ + /* ~1 clears the register type indicator that is set to 1 + * for IO space */ + controller->reg_base = pci_read_config32 (addr, 0x20) & ~1; /* kill legacy support handler */ uhci_stop (controller); mdelay (1); uhci_reg_write16 (controller, USBSTS, 0x3f); - reg16 = pci_read_config16(controller->bus_address, 0xc0); + reg16 = pci_read_config16(addr, 0xc0); reg16 &= 0xdf80; - pci_write_config16 (controller->bus_address, 0xc0, reg16); + pci_write_config16 (addr, 0xc0, reg16); UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t)); /* 4kb aligned to 4kb */ if (! UHCI_INST (controller)->framelistptr) diff --git a/payloads/libpayload/drivers/usb/uhci.h b/payloads/libpayload/drivers/usb/uhci.h index 2ef3f0b..6bb5c17 100644 --- a/payloads/libpayload/drivers/usb/uhci.h +++ b/payloads/libpayload/drivers/usb/uhci.h @@ -33,8 +33,8 @@ #include <pci.h> #include <usb/usb.h> - hci_t *uhci_init (pcidev_t addr); +hci_t *uhci_pci_init (pcidev_t addr); - void uhci_rh_init (usbdev_t *dev); +void uhci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 20e064e..4e077f6 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -27,6 +27,8 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG + #include <usb/usb.h> #include "generic_hub.h" diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 76653ff..f74a833 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG #include <libpayload-config.h> #include <usb/usb.h> #include "uhci.h" @@ -35,6 +36,7 @@ #include "xhci.h" #include <usb/usbdisk.h> +#ifdef CONFIG_USB_PCI /** * Initializes USB controller attached to PCI * @@ -58,8 +60,6 @@ static int usb_controller_initialize(int bus, int dev, int func) prog_if = (class >> 8) & 0xff; /* enable busmaster */ -#define PCI_COMMAND 4 -#define PCI_COMMAND_MASTER 4 if (devclass == 0xc03) { u32 pci_command; @@ -73,7 +73,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x00: #ifdef CONFIG_USB_UHCI usb_debug("UHCI controller\n"); - uhci_init (pci_device); + uhci_pci_init (pci_device); #else usb_debug("UHCI controller (not supported)\n"); #endif @@ -82,7 +82,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x10: #ifdef CONFIG_USB_OHCI usb_debug("OHCI controller\n"); - ohci_init(pci_device); + ohci_pci_init(pci_device); #else usb_debug("OHCI controller (not supported)\n"); #endif @@ -91,7 +91,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x20: #ifdef CONFIG_USB_EHCI usb_debug("EHCI controller\n"); - ehci_init(pci_device); + ehci_pci_init(pci_device); #else usb_debug("EHCI controller (not supported)\n"); #endif @@ -100,7 +100,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x30: #ifdef CONFIG_USB_XHCI usb_debug("xHCI controller\n"); - xhci_init(pci_device); + xhci_pci_init(pci_device); #else usb_debug("xHCI controller (not supported)\n"); #endif @@ -154,12 +154,33 @@ static void usb_scan_pci_bus(int bus) } } } +#endif + +#ifdef CONFIG_USB_MEMORY +static void usb_scan_memory(void) +{ +#ifdef CONFIG_USB_XHCI + xhci_init((void *)(unsigned long)CONFIG_USB_XHCI_BASE_ADDRESS); +#endif +#ifdef CONFIG_USB_EHCI + ehci_init((void *)(unsigned long)CONFIG_USB_EHCI_BASE_ADDRESS); +#endif +#ifdef CONFIG_USB_OHCI + ohci_init((void *)(unsigned long)CONFIG_USB_OHCI_BASE_ADDRESS); +#endif +} +#endif /** * Initialize all USB controllers attached to PCI. */ int usb_initialize(void) { +#ifdef CONFIG_USB_PCI usb_scan_pci_bus(0); +#endif +#ifdef CONFIG_USB_MEMORY + usb_scan_memory(); +#endif return 0; } diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 16af448..ad7e82f 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +//#define USB_DEBUG #include <endian.h> #include <usb/usb.h> #include <usb/usbmsc.h> diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 51f9422..aa2fe57 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -143,7 +143,7 @@ xhci_wait_ready(xhci_t *const xhci) } hci_t * -xhci_init (const pcidev_t addr) +xhci_init (const void *bar) { int i; @@ -192,14 +192,7 @@ xhci_init (const pcidev_t addr) goto _free_xhci; } - /* Now, gather information and check for compatibility */ - - controller->bus_address = addr; - controller->reg_base = pci_read_config32(addr, REG_BAR0) & ~0xf; - if (pci_read_config32(addr, REG_BAR1) > 0) { - xhci_debug("We don't do 64bit addressing\n"); - goto _free_xhci; - } + controller->reg_base = (u32)(unsigned long)bar; xhci->capreg = phys_to_virt(controller->reg_base); xhci->opreg = ((void *)xhci->capreg) + xhci->capreg->caplength; @@ -270,7 +263,6 @@ xhci_init (const pcidev_t addr) } /* Now start working on the hardware */ - if (xhci_wait_ready(xhci)) goto _free_xhci; @@ -279,8 +271,6 @@ xhci_init (const pcidev_t addr) xhci_reset(controller); xhci_reinit(controller); - xhci_switch_ppt_ports(addr); - xhci->roothub->controller = controller; xhci->roothub->init = xhci_rh_init; xhci->roothub->init(xhci->roothub); @@ -308,6 +298,28 @@ _free_controller: return NULL; } +#ifdef CONFIG_USB_PCI +hci_t * +xhci_pci_init (pcidev_t addr) +{ + u32 reg_addr; + hci_t controller; + + reg_addr = (u32)phys_to_virt(pci_read_config32 (addr, 0x10) & ~0xf); + //controller->reg_base = pci_read_config32 (addr, 0x14) & ~0xf; + if (pci_read_config32 (addr, 0x14) > 0) { + fatal("We don't do 64bit addressing.\n"); + } + + controller = xhci_init((void *)(unsigned long)reg_addr); + controller->bus_address = addr; + + xhci_switch_ppt_ports(addr); + + return controller; +} +#endif + static void xhci_reset(hci_t *const controller) { diff --git a/payloads/libpayload/drivers/usb/xhci.h b/payloads/libpayload/drivers/usb/xhci.h index b900b12..b76c982 100644 --- a/payloads/libpayload/drivers/usb/xhci.h +++ b/payloads/libpayload/drivers/usb/xhci.h @@ -33,8 +33,9 @@ #include <pci.h> #include <usb/usb.h> - hci_t *xhci_init (pcidev_t addr); +hci_t *xhci_pci_init (pcidev_t addr); +hci_t *xhci_init (void *bar); - void xhci_rh_init (usbdev_t *dev); +void xhci_rh_init (usbdev_t *dev); #endif diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ab45708..a351690 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -30,7 +30,7 @@ #ifndef __USB_H #define __USB_H #include <libpayload.h> -#include <pci.h> +#include <pci/pci.h> typedef enum { host_to_device = 0, device_to_host = 1 } dev_req_dir; typedef enum { standard_type = 0, class_type = 1, vendor_type = @@ -118,7 +118,6 @@ typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3} hc_type; struct usbdev_hc { hci_t *next; - pcidev_t bus_address; u32 reg_base; hc_type type; usbdev_t *devices[128]; // dev 0 is root hub, 127 is last addressable

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coreboot-gerrit November 2013