New subject: Change in ...coreboot[master]: soc/sifive/fu540: initialize flash

27 Dec 2018

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466
Change subject: fu540: add code to initialize flash
......................................................................
fu540: add code to initialize flash
SiFive's ZSBL has initialized flash, but only 16MB of space is
available. I fixed it to use all 32MB.
Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Signed-off-by: Xiang Wang wxjstz@126.com
---
M src/mainboard/sifive/hifive-unleashed/Makefile.inc
A src/mainboard/sifive/hifive-unleashed/bootblock.c
A src/mainboard/sifive/hifive-unleashed/flash.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/soc/sifive/fu540/Makefile.inc
A src/soc/sifive/fu540/include/soc/spi.h
A src/soc/sifive/fu540/include/soc/spi_flash.h
A src/soc/sifive/fu540/spi.c
8 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1

diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
index 27ddcba..2dac283 100644
--- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc
+++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
@@ -11,6 +11,10 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
+bootblock-y += flash.c
+bootblock-y += bootblock.c
+
+romstage-y += flash.c
 romstage-y += romstage.c
bootblock-y += memlayout.ld
diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c
new file mode 100644
index 0000000..777b2aa
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+extern void bootblock_mainboard_init(void);
+
+void bootblock_mainboard_init(void)
+{
+	flash_init();
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c
new file mode 100644
index 0000000..a29ac24
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/flash.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+
+const static spi_reg_ffmt ffmt= {
+	.cmd_en = 1,
+	.addr_len = 4,
+	.pad_cnt = 8,
+	.command_proto = SPI_PROTO_S,
+	.addr_proto = SPI_PROTO_S,
+	.data_proto = SPI_PROTO_Q,
+	.command_code = 0x6c
+};
+
+
+void flash_init(void)
+{
+	initialize_spi_flash_mmap_quad(
+			(spi_ctrl*)FU540_QSPI0,
+			clock_get_tlclk_khz(),
+			ffmt.raw_bits,
+			0x66,
+			0x99);
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 8277141..1675aca 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -21,6 +21,8 @@
 #include <soc/clock.h>
 #include <soc/sdram.h>
+extern void flash_init(void);
+
 void main(void)
 {
    console_init();
@@ -39,6 +41,7 @@
    if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
    	uart_init(CONFIG_UART_FOR_CONSOLE);
+	flash_init();
    sdram_init();
cbmem_initialize_empty();
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index 4f62f3e..83c7b1c 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -18,6 +18,7 @@
 bootblock-y += media.c
 bootblock-y += bootblock.c
 bootblock-y += clock.c
+bootblock-y += spi.c
romstage-y += uart.c
 romstage-y += clint.c
@@ -26,6 +27,7 @@
 romstage-y += cbmem.c
 romstage-y += otp.c
 romstage-y += clock.c
+romstage-y += spi.c
ramstage-y += uart.c
 ramstage-y += clint.c
@@ -34,6 +36,7 @@
 ramstage-y += cbmem.c
 ramstage-y += otp.c
 ramstage-y += clock.c
+ramstage-y += spi.c
CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h
new file mode 100644
index 0000000..c40ae7c
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_H__
+
+#include <stdint.h>
+
+#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide")
+
+typedef union
+{
+	struct
+	{
+		uint32_t pha : 1;
+		uint32_t pol : 1;
+		uint32_t reserved : 30;
+	};
+	uint32_t raw_bits;
+} spi_reg_sckmode;
+_ASSERT_SIZEOF(spi_reg_sckmode, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t mode : 2;
+		uint32_t reserved : 30;
+	};
+	uint32_t raw_bits;
+} spi_reg_csmode;
+_ASSERT_SIZEOF(spi_reg_csmode, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t cssck : 8;
+		uint32_t reserved0 : 8;
+		uint32_t sckcs : 8;
+		uint32_t reserved1 : 8;
+	};
+	uint32_t raw_bits;
+} spi_reg_delay0;
+_ASSERT_SIZEOF(spi_reg_delay0, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t intercs : 8;
+		uint32_t reserved0 : 8;
+		uint32_t interxfr : 8;
+		uint32_t reserved1 : 8;
+	};
+	uint32_t raw_bits;
+} spi_reg_delay1;
+_ASSERT_SIZEOF(spi_reg_delay1, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t proto : 2;
+		uint32_t endian : 1;
+		uint32_t dir : 1;
+		uint32_t reserved0 : 12;
+		uint32_t len : 4;
+		uint32_t reserved1 : 12;
+	};
+	uint32_t raw_bits;
+} spi_reg_fmt;
+_ASSERT_SIZEOF(spi_reg_fmt, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t data : 8;
+		uint32_t reserved : 23;
+		uint32_t full : 1;
+	};
+	uint32_t raw_bits;
+} spi_reg_txdata;
+_ASSERT_SIZEOF(spi_reg_txdata, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t data : 8;
+		uint32_t reserved : 23;
+		uint32_t empty : 1;
+	};
+	uint32_t raw_bits;
+} spi_reg_rxdata;
+_ASSERT_SIZEOF(spi_reg_rxdata, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t txmark : 3;
+		uint32_t reserved : 29;
+	};
+	uint32_t raw_bits;
+} spi_reg_txmark;
+_ASSERT_SIZEOF(spi_reg_txmark, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t rxmark : 3;
+		uint32_t reserved : 29;
+	};
+	uint32_t raw_bits;
+} spi_reg_rxmark;
+_ASSERT_SIZEOF(spi_reg_rxmark, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t en : 1;
+		uint32_t reserved : 31;
+	};
+	uint32_t raw_bits;
+} spi_reg_fctrl;
+_ASSERT_SIZEOF(spi_reg_fctrl, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t cmd_en : 1;
+		uint32_t addr_len : 3;
+		uint32_t pad_cnt : 4;
+		uint32_t command_proto : 2;
+		uint32_t addr_proto : 2;
+		uint32_t data_proto : 2;
+		uint32_t reserved : 2;
+		uint32_t command_code : 8;
+		uint32_t pad_code : 8;
+	};
+	uint32_t raw_bits;
+} spi_reg_ffmt;
+_ASSERT_SIZEOF(spi_reg_ffmt, 4);
+
+
+typedef union
+{
+	struct
+	{
+		uint32_t txwm : 1;
+		uint32_t rxwm : 1;
+		uint32_t reserved : 30;
+	};
+	uint32_t raw_bits;
+} spi_reg_ie;
+typedef spi_reg_ie spi_reg_ip;
+_ASSERT_SIZEOF(spi_reg_ie, 4);
+_ASSERT_SIZEOF(spi_reg_ip, 4);
+
+#undef _ASSERT_SIZEOF
+
+
+/**
+ * SPI control register memory map.
+ *
+ * All functions take a pointer to a SPI device's control registers.
+ */
+typedef volatile struct
+{
+	uint32_t sckdiv;
+	spi_reg_sckmode sckmode;
+	uint32_t reserved08;
+	uint32_t reserved0c;
+
+	uint32_t csid;
+	uint32_t csdef;
+	spi_reg_csmode csmode;
+	uint32_t reserved1c;
+
+	uint32_t reserved20;
+	uint32_t reserved24;
+	spi_reg_delay0 delay0;
+	spi_reg_delay1 delay1;
+
+	uint32_t reserved30;
+	uint32_t reserved34;
+	uint32_t reserved38;
+	uint32_t reserved3c;
+
+	spi_reg_fmt fmt;
+	uint32_t reserved44;
+	spi_reg_txdata txdata;
+	spi_reg_rxdata rxdata;
+
+	spi_reg_txmark txmark;
+	spi_reg_rxmark rxmark;
+	uint32_t reserved58;
+	uint32_t reserved5c;
+
+	spi_reg_fctrl fctrl;
+	spi_reg_ffmt ffmt;
+	uint32_t reserved68;
+	uint32_t reserved6c;
+
+	spi_reg_ie ie;
+	spi_reg_ip ip;
+} spi_ctrl;
+
+
+void spi_tx(spi_ctrl* spictrl, uint8_t in);
+uint8_t spi_rx(spi_ctrl* spictrl);
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in);
+
+// Inlining header functions in C
+// https://stackoverflow.com/a/23699777/7433423
+
+/**
+ * Get smallest clock divisor that divides input_khz to a quotient less than or
+ * equal to max_target_khz;
+ */
+static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz)
+{
+	// f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1
+	//
+	// The nearest integer solution for div requires rounding up as to not exceed
+	// max_target_khz.
+	//
+	// div = ceil(f_in / (2*f_sck)) - 1
+	//     = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1
+	//
+	// This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed
+	// 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+	unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz);
+	// Avoid underflow
+	if (quotient == 0)
+		return 0;
+	return quotient - 1;
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */
diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h
new file mode 100644
index 0000000..9926b82
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi_flash.h
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+
+#include <soc/spi.h>
+#include <stdint.h>
+
+#define SPI_PROTO_S             0
+#define SPI_PROTO_D             1
+#define SPI_PROTO_Q             2
+
+/**
+ * Set up SPI for direct, non-memory-mapped access.
+ */
+
+static inline int initialize_spi_flash_direct(
+		spi_ctrl* spictrl,
+		unsigned int spi_clk_input_khz,
+		unsigned int command_enable,
+		unsigned int command_reset)
+{
+  // Max desired SPI clock is 10MHz
+  spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+  spictrl->fctrl.en = 0;
+
+  spi_txrx(spictrl, command_enable);
+  spi_txrx(spictrl, command_reset);
+
+  return 0;
+}
+
+static inline int _initialize_spi_flash_mmap(
+		spi_ctrl* spictrl,
+		unsigned int spi_clk_input_khz,
+		uint32_t ffmt_rawbits,
+		unsigned int command_enable,
+		unsigned int command_reset)
+{
+  // Max desired SPI clock is 10MHz
+  spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+  spictrl->fctrl.en = 0;
+
+  spi_txrx(spictrl, command_enable);
+  spi_txrx(spictrl, command_reset);
+
+  spictrl->ffmt.raw_bits = ffmt_rawbits;
+
+  spictrl->fctrl.en = 1;
+  __asm__ __volatile__ ("fence io, io");
+  return 0;
+}
+
+
+static inline int initialize_spi_flash_mmap_single(
+		spi_ctrl* spictrl,
+		unsigned int spi_clk_input_khz,
+		uint32_t ffmt_rawbits,
+		unsigned int command_enable,
+		unsigned int command_reset)
+{
+  return _initialize_spi_flash_mmap(
+		  spictrl,
+		  spi_clk_input_khz,
+		  ffmt_rawbits,
+		  command_enable,
+		  command_reset);
+}
+
+
+static inline int initialize_spi_flash_mmap_quad(
+		spi_ctrl* spictrl,
+		unsigned int spi_clk_input_khz,
+		uint32_t ffmt_rawbits,
+		unsigned int command_enable,
+		unsigned int command_reset)
+{
+  return _initialize_spi_flash_mmap(
+		  spictrl,
+		  spi_clk_input_khz,
+		  ffmt_rawbits,
+		  command_enable,
+		  command_reset);
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */
+
diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
new file mode 100644
index 0000000..01a58dd
--- /dev/null
+++ b/src/soc/sifive/fu540/spi.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/spi.h>
+
+/**
+ * Wait until SPI is ready for transmission and transmit byte.
+ */
+void spi_tx(spi_ctrl* spictrl, uint8_t in)
+{
+#if __riscv_atomic
+	int32_t r;
+	do {
+		asm volatile (
+			"amoor.w %0, %2, %1\n"
+			: "=r" (r), "+A" (spictrl->txdata.raw_bits)
+			: "r" (in)
+		);
+	} while (r < 0);
+#else
+	while ((int32_t) spictrl->txdata.raw_bits < 0);
+	spictrl->txdata.data = in;
+#endif
+}
+
+
+/**
+ * Wait until SPI receive queue has data and read byte.
+ */
+uint8_t spi_rx(spi_ctrl* spictrl)
+{
+	int32_t out;
+	while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0);
+	return (uint8_t) out;
+}
+
+
+/**
+ * Transmit a byte and receive a byte.
+ */
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in)
+{
+	spi_tx(spictrl, in);
+	return spi_rx(spictrl);
+}
+
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/30466
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Gerrit-Change-Number: 30466
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang wxjstz@126.com
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: fu540: add code to initialize flash