Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
mb/google/hatch: modify PCIe ports setting for mushu
1. Enabled PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to prot 7 3. Enabled PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/1
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index c623fde..c584515 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -63,6 +63,28 @@ .fall_time_ns = 120, }, }" + + # Enable Root port 13(x4) for dGPU. + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 5 + register "PcieClkSrcClkReq[5]" = "5" + + # PCIe port 3 reserve for GPU REFCLK + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + # RP 3 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "2" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 7 for M.2 E-key WLAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # RP 7 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3"
# GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 66: trailing whitespace
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 74: trailing whitespace
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 81: trailing whitespace
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#2).
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
mb/google/hatch: modify PCIe ports setting for mushu
1. Enabled PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to prot 7 3. Enabled PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#4).
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
mb/google/hatch: modify PCIe ports setting for mushu
1. Enabled PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to prot 7 3. Enabled PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/4
EricR Lai has uploaded a new patch set (#5) to the change originally created by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch/variants/mushu: modify PCIe ports setting ......................................................................
mb/google/hatch/variants/mushu: modify PCIe ports setting
1. Enabled PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to prot 7 3. Enabled PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/5
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch/variants/mushu: modify PCIe ports setting ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 75: # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = " PCIE#3 seems to be connected to test points?
How is this connected to the GPU REFCLK?
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 80: 2 This should be 4 according to my discussion with shanthi.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch/variants/mushu: modify PCIe ports setting ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 74: : # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = "1" : # RP 3 uses CLK SRC 2 : register "PcieClkSrcUsage[2]" = "2" : register "PcieClkSrcClkReq[2]" = "2" Sorry, updating the last comment. Is PCIe port 3 being used for testing at the moment? if that's the case, then can we not commit the changes for now? This is not consistent with the current schematics.
BTW, you'll have to update the corresponding PCI configs with the fit tool as well.
Hello EricR Lai, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#6).
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
mb/google/hatch: modify PCIe ports setting for mushu
1. Enabled PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to prot 7 3. Enabled PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
Patch Set 6:
(8 comments)
Next time, please do two commits.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@7 PS6, Line 7: mb/google/hatch: modify PCIe ports setting for mushu Please be specific.
Enable dGPU and WLAN devices
Also, I believe Chromium devices use specific prefixes for variants.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@9 PS6, Line 9: Enabled Enable
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@10 PS6, Line 10: prot port
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@11 PS6, Line 11: Enabled Enable
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: 13(x4) Please add a space before (.
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: # Enable Root port 13(x4) for dGPU. Please remove the dot at the end.
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 75: # PCIe port 8 reserve for GPU REFCLK … reserve*d* for …
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 87: register "PcieClkSrcClkReq[3]" = "3" Shouldn’t this be sorted according to port numbers?
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
Patch Set 6:
(1 comment)
Patch Set 5:
(1 comment)
I have uploaded new patch set to modify PCI configs. https://chrome-internal-review.googlesource.com/c/chromeos/overlays/baseboar...
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 80: 2
This should be 4 according to my discussion with shanthi.
Updated as patch set 6.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@7 PS6, Line 7: mb/google/hatch: modify PCIe ports setting for mushu
Please be specific. […]
mb/google/hatch/var/mushu: Correct PCIe port configuration
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 87: register "PcieClkSrcClkReq[3]" = "3"
Shouldn’t this be sorted according to port numbers?
I agree. Current order is [13, 8, 7], but it would be more logical to use [7, 8, 13]
Hello EricR Lai, Angel Pons, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#7).
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 3. Enable PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 66: trailing whitespace
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 73: trailing whitespace
Hello EricR Lai, Angel Pons, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#8).
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 3. Enable PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/8
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 8:
Still wondering about my question in patch set #5 below?
Line 80: Sorry, updating the last comment. Is PCIe port 3 being used for testing at the moment? if that's the case, then can we not commit the changes for now? This is not consistent with the current schematics.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38399/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/8//COMMIT_MSG@7 PS8, Line 7: mb/google/hatch: Correct PCIe ports setting for mushu Also, seems like some of the previous updates have been reverted again. Can you please rebase before uploading your patches please?
Thanks!
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 8:
(8 comments)
Patch Set 8:
Still wondering about my question in patch set #5 below?
Line 80: Sorry, updating the last comment. Is PCIe port 3 being used for testing at the moment? if that's the case, then can we not commit the changes for now? This is not consistent with the current schematics.
I have changed from PCIe port 3 to PCIe port 8 in patch set #8. But this is just reserved and not being used at the moment. I will remove it in next patch.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@7 PS6, Line 7: mb/google/hatch: modify PCIe ports setting for mushu
mb/google/hatch/var/mushu: Correct PCIe port configuration
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@9 PS6, Line 9: Enabled
Enable
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@10 PS6, Line 10: prot
port
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@11 PS6, Line 11: Enabled
Enable
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: # Enable Root port 13(x4) for dGPU.
Please remove the dot at the end.
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: 13(x4)
Please add a space before (.
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 75: # PCIe port 8 reserve for GPU REFCLK
… reserve*d* for …
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 87: register "PcieClkSrcClkReq[3]" = "3"
I agree. […]
Done
Hello EricR Lai, Angel Pons, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#9).
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 3. Enable PCIe port for GPU REFCLK
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/9
Hello EricR Lai, Angel Pons, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38399
to look at the new patch set (#10).
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/10
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 10: Code-Review+2
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 10:
Please resolve all your comments. Thanks!
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 10:
(1 comment)
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38399/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/8//COMMIT_MSG@7 PS8, Line 7: mb/google/hatch: Correct PCIe ports setting for mushu
Also, seems like some of the previous updates have been reverted again. […]
Done
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 10:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 66:
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 74:
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/38399/1/src/mainboard/google/hatch/... PS1, Line 81:
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 75: # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = "
PCIE#3 seems to be connected to test points? […]
Done
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 80: 2
Updated as patch set 6.
Done
https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... PS5, Line 74: : # PCIe port 3 reserve for GPU REFCLK : register "PcieRpEnable[2]" = "1" : register "PcieRpLtrEnable[2]" = "1" : # RP 3 uses CLK SRC 2 : register "PcieClkSrcUsage[2]" = "2" : register "PcieClkSrcClkReq[2]" = "2"
Sorry, updating the last comment. […]
Done
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 66:
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/38399/7/src/mainboard/google/hatch/... PS7, Line 73:
trailing whitespace
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399 Reviewed-by: Shelley Chen shchen@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index c623fde..f50bab2 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -64,6 +64,21 @@ }, }"
+ # PCIe port 7 for M.2 E-key WLAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # RP 7 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable Root port 13 (x4) for dGPU + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 5 + register "PcieClkSrcClkReq[5]" = "5" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"
-
Amanda Hwang (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)
-
EricR Lai (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Shelley Chen (Code Review)